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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@37 b871894f-2f95-9b40-918c-086798483c85
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nakasima 2008-11-27 01:24:13 +00:00
parent a05abb3291
commit 55cb7d8f4f
6 changed files with 1023 additions and 6 deletions
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506
trunk/include/ctr/hw/ARM11/arm11_reg.h Normal file
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/*---------------------------------------------------------------------------*
Project: CtrFirm - include - ctr - HW - ARM11
File: arm11_reg.h
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-11-27#$
$Rev: 37 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
#ifndef CTR_HW_ARM11_REG_H_
#define CTR_HW_ARM11_REG_H_
#ifndef SDK_ASM
#include <ctr/hw/common/arm_reg_common.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define HW_ARM11_CLOCK_MAX ?
#define HW_CPU_CLOCK_MAX HW_ARM11_CLOCK_MAX
#define HW_MPCORE_IC_SIZE 0x4000 // Inst Cache
#define HW_MPCORE_DC_SIZE 0x4000 // Data Cache
#define HW_MPCORE_CACHE_LINE_SIZE 32
#define HW_IC_SIZE HW_MPCORE_IC_SIZE
#define HW_DC_SIZE HW_MPCORE_DC_SIZE
#define HW_CACHE_LINE_SIZE HW_MPCORE_CACHE_LINE_SIZE
//**********************************************************************
// Coprocessor Control Bits
//**********************************************************************
//----------------------------------------------------------------------
// System Control Coprocessor
//----------------------------------------------------------------------
// Register 1.0 : Master Control
#ifdef SDK_ARMULATOR
#define HW_C1_0_SB1 0x00004078 // Should be 1
#else
#define HW_C1_0_SB1 0x000040f8 // Should be 1
#endif
#define HW_C1_FORCE_AP_BIT 0x20000000 // AP[0] used as Access Bit
#define HW_C1_TEX_CB_REMAP 0x10000000 // Remap registers are used for remapping
#define HW_C1_NMFI_FIQ 0x08000000 // FIQs behave as NMFIs
#define HW_C1_EXCEPT_LITTLE_ENDIAN 0x00000000 // CPSR E bit is set to 0 on taking an exception
#define HW_C1_EXCEPT_BIG_ENDIAN 0x00000200 // CPSR E bit is set to 1 on taking an exception
#define HW_C1_MMU_V6 0x00800000 // MMUv6 selected (Subpage AP bits disabled)
#define HW_C1_MMU_V5 0x00000000 // MMUv5 selected (Subpage AP bits enabled)
#define HW_C1_UNALIGN_ACCESS_ENABLE 0x00400000 // Unaligned data and mixed-endian data access enable
#define HW_C1_LD_INTERWORK_DISABLE 0x00008000 // Loads to PC do not set the T bit (ARMv4 behavior)
#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // High exception vectors selected (CTR default)
#define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // Low exception vectors selected
#define HW_C1_IC_ENABLE 0x00001000 // Instruction Cache enabled
#define HW_C1_DC_ENABLE 0x00000004 // Data Cache enabled
#define HW_C1_BR_PREDICT_ENABLE 0x00000800 // Branch prediction enable
#define HW_C1_ROM_PROTECT_ENABLE 0x00000200 // ROM protection enable (Deprecated)
#define HW_C1_MMU_PROTECT_ENABLE 0x00000100 // MMU System protection enable (Deprecated)
#define HW_C1_ALIGN_FAULT_ENABLE 0x00000002 // Strict alignment fault checking enabled (Higher than UNALIGN)
#define HW_C1_MMU_ENABLE 0x00000001 // MMU enable
#define HW_C1_IC_ENABLE_SFT 12
#define HW_C1_DC_ENABLE_SFT 2
// Register 1.1 : Auxiliary Control
#define HW_C1_SMP_MODE 0x00000020 // SMP mode (Invalid for CTR)
#define HW_C1_AMP_MODE 0x00000000 // AMP mode (Invalid for CTR)
#define HW_C1_EXCLUSIVE_L1C_L2C 0x00000010 // L1 and L2 caches are exclusive (Invalid for CTR)
#define HW_C1_BR_FOLDING_ENABLE 0x00000008 // Branch instruction folding enable
#define HW_C1_SBR_PREDICT_ENABLE 0x00000004 // Static branch prediction enable
#define HW_C1_DBR_PREDICT_ENABLE 0x00000002 // Dynamic branch prediction enable
#define HW_C1_RETURN_STACK_ENABLE 0x00000001 // Return stack enable
// Register 1.2 : VFP Access Permission Control
#ifndef SDK_ASM
#define HW_C1_VFP_AP_PACK( vfp_float, vfp_double ) \
\
( ((vfp_float) << HW_C1_AP_CP10_SFT) \
| ((vfp_double) << HW_C1_AP_CP11_SFT) )
#endif
#define HW_C1_AP_CP10_MASK 0x00300000 // Permit access to CP10
#define HW_C1_AP_CP11_MASK 0x00C00000 // CP11
#define HW_C1_AP_CP10_SFT 20
#define HW_C1_AP_CP11_SFT 22
#define HW_C1_AP_NA 0 // Access denied
#define HW_C1_AP_SVR 1 // Supervisor access only
#define HW_C1_AP_PRIV 3 // Full access
// Register 2.0.0/1 : MMU L1 Table Base
#define HW_C2_0_T1_BASE_MASK_MAX 0xffffff80 // Pointer to the level one translation table when Boundary = 0 or VA = 0
#define HW_C2_0_T1_BASE_MASK_MIN 0xffffc000
#define HW_C2_1_T1_BASE_MASK 0xffffc000 // when Boundary > 0 and VA > 0
#define HW_C2_WALK_L2C_CA_MASK 0x00000018 // L2 Cache cachable attributes for page table walking (Invalid for CTR)
#define HW_C2_WALK_ON_SHARED_MEM 0x00000002 // Page table walk is to shared memory
#define HW_C2_WALK_L2C_CA_SFT 3
#define HW_C2_WALK_L2C_CA_NC 0 // L2 Cache Noncachable (Invalid for CTR)
#define HW_C2_WALK_L2C_CA_WB_WA 1 // L2 Cache Cachable Write-Back cached, Write Allocate (Invalid for CTR)
// Register 2.0.2 : MMU L1 Table Boundary
#define HW_C2_V5_T1_BOUNBRY_MASK 0x00000007 // the size of the first-level translation table base boundary for MMUv5
#define HW_C2_V5_T1_BOUNBRY_16KB 0 // 16KB
#define HW_C2_V5_T1_BOUNBRY_8KB 1 // 8KB
#define HW_C2_V5_T1_BOUNBRY_4KB 2 // 4KB
#define HW_C2_V5_T1_BOUNBRY_2KB 3 // 2KB
#define HW_C2_V5_T1_BOUNBRY_1KB 4 // 1KB
#define HW_C2_V5_T1_BOUNBRY_512B 5 // 512B
#define HW_C2_V5_T1_BOUNBRY_256B 6 // 256B
#define HW_C2_V5_T1_BOUNBRY_128B 7 // 128B
// Register 3 : Domain Access Control
#ifndef SDK_ASM
#define HW_C3_DOMAIN_PACK( d0, d1, d2, d3, d4, d5, d6, d7, \
d8, d9, d10, d11, d12, d13, d14, d15 ) \
\
( ((d0) << HW_C3_DM0_SFT) \
| ((d1) << HW_C3_DM1_SFT) \
| ((d2) << HW_C3_DM2_SFT) \
| ((d3) << HW_C3_DM3_SFT) \
| ((d4) << HW_C3_DM4_SFT) \
| ((d5) << HW_C3_DM5_SFT) \
| ((d6) << HW_C3_DM6_SFT) \
| ((d7) << HW_C3_DM7_SFT) \
| ((d8) << HW_C3_DM8_SFT) \
| ((d9) << HW_C3_DM9_SFT) \
| ((d10) << HW_C3_DM10_SFT) \
| ((d11) << HW_C3_DM11_SFT) \
| ((d12) << HW_C3_DM12_SFT) \
| ((d13) << HW_C3_DM13_SFT) \
| ((d14) << HW_C3_DM14_SFT) \
| ((d15) << HW_C3_DM15_SFT) )
#endif
#ifndef SDK_ASM
#define HW_C3_DOMAIN_ID_SFT( no ) ( (no) * 2 )
#endif
#define HW_C3_DM0_SFT 0 // Domain 0
#define HW_C3_DM1_SFT 2 // 1
#define HW_C3_DM2_SFT 4 // 2
#define HW_C3_DM3_SFT 6 // 3
#define HW_C3_DM4_SFT 8 // 4
#define HW_C3_DM5_SFT 10 // 5
#define HW_C3_DM6_SFT 12 // 6
#define HW_C3_DM7_SFT 14 // 7
#define HW_C3_DM8_SFT 16 // 8
#define HW_C3_DM9_SFT 18 // 9
#define HW_C3_DM10_SFT 20 // 10
#define HW_C3_DM11_SFT 22 // 11
#define HW_C3_DM12_SFT 24 // 12
#define HW_C3_DM13_SFT 26 // 13
#define HW_C3_DM14_SFT 28 // 14
#define HW_C3_DM15_SFT 30 // 15
#define HW_C3_DM_AP_NA 0 // Any access generates a domain fault
#define HW_C3_DM_AP_CLIENT 1 // Permit clients to access a domain
#define HW_C3_DM_AP_MANAGER 3 // Permit managers to access a domain
// Register 5 : Data/Instruction Fault Status
#define HW_C5_FAULT_DOMAIN_ID_MASK 0x000000f0 // Domain's specify at data fault
#define HW_C5_FAULT_STATUS_MASK 0x0000040f // Fault status
#define HW_C5_FAULT_AXI_SLVERR 0x00001000 // AXI abort marked as SLVERR
#define HW_C5_FAULT_AXI_DECERR 0x00000000 // DECERR
#define HW_C5_FAULT_WRITE 0x00000800 // Write access caused the abort
#define HW_C5_FAULT_READ 0x00000000 // Read access
#define HW_C5_FAULT_DOMAIN_ID_SFT 4
#define HW_C5_ALIGN_FAULT 0x001 // Alignment fault
#define HW_C5_ICACHE_OP_FAULT 0x004 // Instruction cache maintenance operation fault
#define HW_C5_SECTION_TRANS_FAULT 0x005 // Section translation fault
#define HW_C5_SECTION_ACCESS_FAULT 0x003 // Section access bit fault
#define HW_C5_SECTION_DOMAIN_FAULT 0x009 // Section domain fault
#define HW_C5_SECTION_AP_FAULT 0x00d // Section permission fault
#define HW_C5_PAGE_TRANS_FAULT 0x007 // Page translation fault
#define HW_C5_PAGE_ACCESS_FAULT 0x006 // Page access bit fault
#define HW_C5_PAGE_DOMAIN_FAULT 0x00b // Page domain fault
#define HW_C5_PAGE_AP_FAULT 0x00f // Page permission fault
#define HW_C5_EA1_EXT_ABORT 0x00c // First-level external abort on translation
#define HW_C5_EA2_EXT_ABORT 0x00e // Second-level external abort on translation
#define HW_C5_PRECISE_EXT_ABORT 0x008 // Precise external abort
#define HW_C5_IMPRECISE_EXT_ABORT 0x106 // Imprecise external abort
#define HW_C5_DEGUB_EVENT_ABORT 0x002 // Debug event abort
// Register 7.0 : Wait for interrupt
// Register 7.5 : Prefetch Buffer / Branch Target Cache Operation
// Register 7.10 : Data Memory Barrier / Drain Synchronization Barrier (Wait for Write Buffer Empty)
// Register 7.5/6/7/10/14 : Cache Operations
#define HW_C7_IC_MVA_MASK 0xffffffe0 // Instruction cache's modified virtual address (per 32B)
#define HW_C7_DC_MVA_MASK 0xffffffe0 // Data cache's modified virtual address (per 32B)
#define HW_C7_BC_MVA_MASK 0xfffffff8 // Modified virtual address of Branch Target Cache (per 8B)
#define HW_C7_IC_IDX_MASK 0x00001fe0 // Instruction cache's address index (per 32B)
#define HW_C7_DC_IDX_MASK 0x00001fe0 // Data cache's address index (per 32B)
#define HW_C7_CACHE_WAY_NO_MASK 0xc0000000 // Number of cache way
#define HW_C7_CACHE_IDX_SFT 5
#define HW_C7_CACHE_WAY_NO_SFT 30
// Register 7.4/8 : VA to PA operations
#define HW_C7_VA_SRC_MASK 0xfffffc00 // Virtual address (per 1KB)
#define HW_C7_PA_DEST_MASK 0xfffff000 // Physical address (per 4KB)
#define HW_C7_PA_RGT_MASK 0x000000c0 // Region Type
#define HW_C7_PA_L1C_CA_MASK 0x00000030 // L1 Cache attributes
#define HW_C7_PA_L2C_CA_MASK 0x0000000c // L2 Cache attributes (Invalid for CTR)
#define HW_C7_PA_SHAREABLE 0x00000100 // Shareable
#define HW_C7_PA_AXI_SLVERR 0x00000040 // AXI abort marked as SLVERR
#define HW_C7_PA_AXI_DECERR 0x00000000 // DECERR
#define HW_C7_PA_FSR_ALIAS_MASK 0x0000003e // Fault Status Register Alias
#define HW_C7_PA_ABORT 0x00000001 // Abort
#define HW_C7_PA_RGT_TYPE_SFT 6
#define HW_C7_PA_L1C_CA_SFT 4
#define HW_C7_PA_L2C_CA_SFT 2
#define HW_C7_PA_SHAREABLE_SFT 8
#define HW_C7_PA_FSR_ALIAS_SFT 1
#define HW_C7_RGT_STRONG_ORDER 0 // Strongly ordered Region
#define HW_C7_RGT_DEVICE 1 // Device Region
#define HW_C7_RGT_NORMAL 2 // Normal Region
#define HW_C7_CA_NC 0 // Noncachable
#define HW_C7_CA_WB_WA 1 // Write-back Write-allocate
#define HW_C7_CA_WT_RA 2 // Write-through Read-allocate-only
#define HW_C7_CA_WB_RA 3 // Write-back Read-allocate
// Register 8 : TLB Operations
#define HW_C8_TLB_MVA_MASK 0xfffffc00 // Modified virtual address (per 1KB)
#define HW_C8_TLB_ASID_MASK 0x000000ff // Application Space ID
// Register 9 : Data Cache Lockdown
#define HW_C9_DCL_WAY0 0x00000001 // Lockdown Way0
#define HW_C9_DCL_WAY1 0x00000002 // Way1
#define HW_C9_DCL_WAY2 0x00000004 // Way2
#define HW_C9_DCL_WAY3 0x00000008 // Way3
// Register 10.0 : TLB Lockdown
#define HW_C10_TLBL_PRESERVE 0x00000001 // Preserve bit
#define HW_C10_TLBL_VICTIM_MASK 0x1c000000 // Victim
#define HW_C10_TLBL_VICTIM_SFT 26
// Register 10.2.0 : Region Type Remap for Primary Region
#define HW_C10_PRGT_SH_ON_NML_S1 0x00080000 // Remaps shareable attribute when S = 1, for Normal regions
#define HW_C10_PRGT_SH_ON_NML_S0 0x00040000 // when S = 0, for Normal regions
#define HW_C10_PRGT_SH_ON_DEV_S1 0x00020000 // when S = 1, for Device regions
#define HW_C10_PRGT_SH_ON_DEV_S0 0x00010000 // when S = 0, for Device regions
#define HW_C10_PRGT_TCB2_000_MASK 0x0000c000 // Remaps {TEX[0], C, B} = 000 for primary region
#define HW_C10_PRGT_TCB_101_MASK 0x00000c00 // Remaps {TEX[0], C, B} = 101
#define HW_C10_PRGT_TCB_100_MASK 0x00000300 // Remaps {TEX[0], C, B} = 100
#define HW_C10_PRGT_TCB_011_MASK 0x000000c0 // Remaps {TEX[0], C, B} = 011
#define HW_C10_PRGT_TCB_010_MASK 0x00000030 // Remaps {TEX[0], C, B} = 010
#define HW_C10_PRGT_TCB_001_MASK 0x0000000c // Remaps {TEX[0], C, B} = 001
#define HW_C10_PRGT_TCB_000_MASK 0x00000003 // Remaps {TEX[0], C, B} = 000
#define HW_C10_PRGT_TCB2_000_SFT 14
#define HW_C10_PRGT_TCB_101_SFT 10
#define HW_C10_PRGT_TCB_100_SFT 8
#define HW_C10_PRGT_TCB_011_SFT 6
#define HW_C10_PRGT_TCB_010_SFT 4
#define HW_C10_PRGT_TCB_001_SFT 2
#define HW_C10_PRGT_TCB_000_SFT 0
#define HW_C10_PRGT_STRONG_ORDER 0 // Strongly ordered Region
#define HW_C10_PRGT_DEVICE 1 // Device Region
#define HW_C10_PRGT_NORMAL 2 // Normal Region
// Register 10.2.1 : Region Attribute Remap for Normal Region
#define HW_C10_NCA_L2C_TCB_111_MASK 0xc0000000 // Remaps L2 Cache attribute for normal region {TEX[0], C, B} = 111
#define HW_C10_NCA_L2C_TCB_101_MASK 0x0c000000 // {TEX[0], C, B} = 101
#define HW_C10_NCA_L2C_TCB_100_MASK 0x03000000 // {TEX[0], C, B} = 100
#define HW_C10_NCA_L2C_TCB_011_MASK 0x00c00000 // {TEX[0], C, B} = 011
#define HW_C10_NCA_L2C_TCB_010_MASK 0x00300000 // {TEX[0], C, B} = 010
#define HW_C10_NCA_L2C_TCB_001_MASK 0x000c0000 // {TEX[0], C, B} = 001
#define HW_C10_NCA_L2C_TCB_000_MASK 0x00030000 // {TEX[0], C, B} = 000
#define HW_C10_NCA_L1C_TCB_111_MASK 0x0000c000 // Remaps L1 Cache attribute for normal region {TEX[0], C, B} = 111
#define HW_C10_NCA_L1C_TCB_101_MASK 0x00000c00 // {TEX[0], C, B} = 101
#define HW_C10_NCA_L1C_TCB_000_MASK 0x00000300 // {TEX[0], C, B} = 000
#define HW_C10_NCA_L1C_TCB_001_MASK 0x000000c0 // {TEX[0], C, B} = 001
#define HW_C10_NCA_L1C_TCB_010_MASK 0x00000030 // {TEX[0], C, B} = 010
#define HW_C10_NCA_L1C_TCB_011_MASK 0x0000000c // {TEX[0], C, B} = 011
#define HW_C10_NCA_L1C_TCB_100_MASK 0x00000003 // {TEX[0], C, B} = 100
#define HW_C10_NCA_L2C_TCB_111_SFT 30
#define HW_C10_NCA_L2C_TCB_101_SFT 26
#define HW_C10_NCA_L2C_TCB_100_SFT 24
#define HW_C10_NCA_L2C_TCB_011_SFT 22
#define HW_C10_NCA_L2C_TCB_010_SFT 20
#define HW_C10_NCA_L2C_TCB_001_SFT 18
#define HW_C10_NCA_L2C_TCB_000_SFT 16
#define HW_C10_NCA_L1C_TCB_111_SFT 14
#define HW_C10_NCA_L1C_TCB_101_SFT 10
#define HW_C10_NCA_L1C_TCB_000_SFT 8
#define HW_C10_NCA_L1C_TCB_010_SFT 4
#define HW_C10_NCA_L1C_TCB_011_SFT 2
#define HW_C10_NCA_L1C_TCB_100_SFT 0
#define HW_C10_NCA_NC 0 // Noncachable
#define HW_C10_NCA_WB_WA 1 // Write-back Write-allocate
// Register 13.0.0 : FCSE Process ID (Not Recommended for MPCore)
#define HW_C13_FCSE_PID_MASK 0xfe000000 // FCSE Process ID
#define HW_C13_FCSE_PID_SFT 25
// Register 13.0.1 : Context ID
#define HW_C13_CONTEXT_PROCID_MASK 0xffffff00 // Process ID
#define HW_C13_CONTEXT_ASID_MASK 0x000000ff // Application Space ID
#define HW_C13_CONTEXT_PROCID_SFT 8
// Register 13.0.2/3/4 : Thread ID
// Register 15.12.0 : Performance Monitor Control
#define HW_C15_COUNT0_EVT_MASK 0x0ff00000 // Identifies the source of events for Count Register 0
#define HW_C15_COUNT1_EVT_MASK 0x000ff000 // for Count Register 1
#define HW_C15_CYCLE_COUNT_OVERFLOW 0x00000400 // Cycle Counter overflow
#define HW_C15_COUNT1_OVERFLOW 0x00000200 // Count Register 1 overflow
#define HW_C15_COUNT0_OVERFLOW 0x00000100 // Count Register 0 overflow
#define HW_C15_CYCLE_COUNT_IE 0x00000040 // Cycle Counter interrupt enable
#define HW_C15_COUNT1_IE 0x00000020 // Count Register 1 interrupt enable
#define HW_C15_COUNT0_IE 0x00000010 // Count Register 0 interrupt enable
#define HW_C15_CYCLE_COUNT_DIV64 0x00000008 // Cycle Counter counts every 64th processor clock cycle
#define HW_C15_CYCLE_COUNT_RESET 0x00000004 // Cycle Counter Reset on Write
#define HW_C15_COUNT01_RESET 0x00000002 // Counter Register 0/1 Reset on Write
#define HW_C15_COUNT_ENABLE 0x00000001 // All three counters enable
#define HW_C15_COUNT0_EVT_SFT 20
#define HW_C15_COUNT1_EVT_SFT 12
#define HW_C15_EVT_IC_MISS 0x00 // Instruction cache miss
#define HW_C15_EVT_IFETCH_STALL 0x01 // Instruction fetch stall
#define HW_C15_EVT_DATA_STALL 0x02 // Data stall
#define HW_C15_EVT_ITLB_MISS 0x03 // Instruction MicroTLB miss
#define HW_C15_EVT_DTLB_MISS 0x04 // Data MicroTLB miss
#define HW_C15_EVT_MIGHT_BR_MISS 0x05 // Branch might have changed program flow
#define HW_C15_EVT_BR_NOT_PREDICT 0x06 // Branch not predicted
#define HW_C15_EVT_BR_PREDICT_MISS 0x07 // Branch predict miss
#define HW_C15_EVT_INST_EXEC 0x08 // Instruction executed
#define HW_C15_EVT_FOLD_INST_EXEC 0x09 // Folded instruction executed
#define HW_C15_EVT_DC_READ 0x0a // Data cache read
#define HW_C15_EVT_DC_MISS 0x0b // Data cache miss
#define HW_C15_EVT_DC_WRITE 0x0c // Data cache write
#define HW_C15_EVT_DC_WRITE_MISS 0x0d // Data cache write miss
#define HW_C15_EVT_DC_LINE_EVICT 0x0e // Data cache line eviction
#define HW_C15_EVT_SW_CHANGE_PC 0x0f // Software changed the PC and there is not a mode change
#define HW_C15_EVT_MTLB_MISS 0x10 // Main TLB miss
#define HW_C15_EVT_EXMEM_REQ 0x11 // External memory request (Cache Refill, Noncachable, Write-Back)
#define HW_C15_EVT_LSQ_FULL_STALL 0x12 // Stall because of Load Store Unit request queue being full
#define HW_C15_EVT_STB_DRAIN_TIMES 0x13 // Store buffer drain times
#define HW_C15_EVT_STB_MERGED 0x14 // Store buffer write is merged
#define HW_C15_EVT_LSU_SAFE_MODE 0x15 // Load Store Unit is in safe mode
#define HW_C15_EVT_INC_EACH_CYCLE 0xff // An increment each cycle
// Register 15.1.0 : Main TLB Debug Control
#define HW_C15_MTLB_LD_ENABLE 0x00000000 // Main TLB load enabled
#define HW_C15_MTLB_LD_DISABLE 0x00000030 // Main TLB load disabled
// Register 15.4 : Select TLB lockdown entry operations
#define HW_C15_TLBL_SEL_ENTRY_IDX 0x0000003f // Set-associative region index
#define HW_C15_TLBL_LKABLE_IDX 0x80000000 // Lockable region index
#define HW_C15_TLBL_ASSOC_WAY_MASK 0x00000020 // if ASSOCIATIVE, Way index
#define HW_C15_TLBL_ASSOC_SET_MASK 0x0000001f // if ASSOCIATIVE, Set index
#define HW_C15_TLBL_LKABLE_ET_MASK 0x00000003 // if LOCKABLE, Lockable entry
// Register 15.5 : TLB Lockdown VA operations
#define HW_C15_TLBL_VPN_MASK 0xfffff000 // TLB Virtual page number (per 4KB)
#define HW_C15_TLBL_MSID_MASK 0x000003ff // Memory space ID
#define HW_C15_TLBL_VPN_SFT 12
#define HW_C15_TLBL_MSID_GLOBAL 0x200 // Global entries
#define HW_C15_TLBL_MSID_ASID_MASK 0x0ff // Application Space ID entries
// Register 15.6 : TLB Lockdown PA operations
#define HW_C15_TLBL_PPN_MASK 0xfffff000 // TLB Physical page number (per 4KB)
#define HW_C15_TLBL_PSIZE_MASK 0x000000c0 // Page size
#define HW_C15_TLBL_APX_MASK 0x0000000e // Access Permissions Extension
#define HW_C15_TLBL_LOCKED_VALID 0x00000001 // Locked and valid
#define HW_C15_TLBL_PPN_SFT 12
#define HW_C15_TLBL_PSIZE_SFT 6
#define HW_C15_TLBL_APX_SFT 1
#define HW_C15_PSIZE_4KB 1 // 4KB page
#define HW_C15_PSIZE_64KB 2 // 64KB page
#define HW_C15_PSIZE_1MB 3 // 1MB page
#define HW_C15_PSIZE_16MB 0 // 16MB page
#define HW_C15_APX_NA 0 // Access denied
#define HW_C15_APX_S_RW_U_NA 1 // Supervisor access only
#define HW_C15_APX_S_RW_U_RO 2 // Supervisor full access, User read only
#define HW_C15_APX_ALL 3 // Full access
#define HW_C15_APX_S_RO_U_NA 5 // Supervisor read only
#define HW_C15_APX_S_RO_U_RO 6 // Supervisor/User read only
// Register 15.7 : TLB Lockdown Attributes
/*
#define HW_C15_TLBL_SP4_AP_MASK 0xc0000000 // Permissions for the 4th subpage (for MMUv5)
#define HW_C15_TLBL_SP3_AP_MASK 0x30000000 // Permissions for the 3rd subpage (for MMUv5)
#define HW_C15_TLBL_SP2_AP_MASK 0x0c000000 // Permissions for the 2nd subpage (for MMUv5)
#define HW_C15_TLBL_SP_VALID 0x02000000 // Subpages are supported (for MMUv5)
*/
#define HW_C15_TLBL_SP_INVALID 0x00000000 // Subpages are not supported (for MMUv6)
#define HW_C15_TLBL_DOMAIN_MASK 0x00000780 // Domain number of the TLB entry
#define HW_C15_TLBL_XN 0x00000040 // Execute Never
#define HW_C15_TLBL_RGT_MASK 0x0000003e // Region Type
#define HW_C15_TLBL_SHARED 0x00000001 // Shared
/*
#define HW_C15_TLBL_SP4_AP_SFT 30
#define HW_C15_TLBL_SP3_AP_SFT 28
#define HW_C15_TLBL_SP2_AP_SFT 26
*/
#define HW_C15_TLBL_DOMAIN_SFT 7
#define HW_C15_TLBL_RGT_SFT 1
#define HW_C15_TLBL_CBA_L1C_SFT 1
#define HW_C15_TLBL_CBA_L2C_SFT 3
#define HW_C15_SP_AP_NA 0 // Access denied (not use S, R)
#define HW_C15_SP_AP_S_RW_U_NA 1 // Supervisor access only
#define HW_C15_SP_AP_S_RW_U_RO 2 // Supervisor full access, User read only
#define HW_C15_SP_AP_ALL 3 // Full access
#define HW_C15_RGT_STRONG_ORDER 0x00 // Strongly Ordered, regardless of the S bit in the page table
#define HW_C15_RGT_SHARED_DEVICE 0x01 // Shared Device, regardless of the S bit in the page table
#define HW_C15_RGT_NSHARED_DEVICE 0x08 // Non-Shared Device, regardless of the S bit in the page table
#define HW_C15_RGT_L1C_NC_NB 0x10 // L1C Noncachable, Unbuffered
#define HW_C15_RGT_L1C_WB_WA 0x11 // L1C Write-back Write-allocate, Buffered
#define HW_C15_RGT_L1L2C_NC 0x04 // L1C and L2C Noncachable
#define HW_C15_RGT_L1L2C_WB_WA 0x07 // L1C and L2C Write-Back, Allocate on Write
#ifdef __cplusplus
} // extern "C"
#endif
// CTR_HW_ARM11_REG_H_
#endif

13
trunk/include/ctr/hw/ARM11/mmap_global.h
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@ -10,9 +10,9 @@
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: #$
$Rev: $
$Author: $
$Date:: 2008-11-27#$
$Rev: 37 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
#ifndef CTR_HW_ARM11_MMAP_GLOBAL_H_
#define CTR_HW_ARM11_MMAP_GLOBAL_H_
@ -75,9 +75,12 @@ extern "C" {
#define HW_MPCORE_REG_SIZE 0x20000
//----------------------------- System ROM
#define HW_BIOS 0x00000000
#define HW_BIOS 0xffff0000
#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
#define HW_BIOS_SIZE 0x00010000
#define HW_BIOS_EX HW_BIOS_END
#define HW_BIOS_EX_END (HW_BIOS_EX + HW_BIOS_EX_SIZE)
#define HW_BIOS_SIZE 0x00008000
#define HW_BIOS_EX_SIZE 0x00008000
#define HW_RESET_VECTOR HW_BIOS

327
trunk/include/ctr/hw/ARM11/mmu_table.h Normal file
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@ -0,0 +1,327 @@
/*---------------------------------------------------------------------------*
Project: CtrFirm - include - ctr - HW - ARM11
File: mmu_table.h
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-11-27#$
$Rev: 37 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
#ifndef CTR_HW_ARM11_MMU_TABLE_H_
#define CTR_HW_ARM11_MMU_TABLE_H_
#ifndef SDK_ASM
#include <ctr/types.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
// MMUv6 Table Structure
#ifndef SDK_ASM
typedef struct
{
u32 sb0_0:1;
u32 sb1_1:1;
u32 bafferable:1;
u32 cacheable:1;
u32 executeNever:1;
u32 ignored:4;
u32 notifyEcc:1;
u32 permission:2;
u32 memoryTypeEx:3;
u32 permissionEx:1;
u32 shared:1;
u32 notGlobal:1;
u32 sb1_18:1;
u32 sb0_19_23:3;
u32 base:8;
}
OSMMUv6SuperSection, OSMMUv6Section16MB;
typedef struct
{
u32 sb0_0:1;
u32 sb1_1:1;
u32 bafferable:1;
u32 cacheable:1;
u32 executeNever:1;
u32 domain:4;
u32 notifyEcc:1;
u32 permission:2;
u32 memoryTypeEx:3;
u32 permissionEx:1;
u32 shared:1;
u32 notGlobal:1;
u32 sb0_18_19:2;
u32 base:12;
}
OSMMUv6Section, OSMMUv6Section1MB;
typedef struct
{
u32 sb1_0:1;
u32 sb0_1_4:4;
u32 domain:4;
u32 notifyEcc:1;
u32 base:12;
}
OSMMUv6CoarsePage;
typedef struct
{
u32 sb1_0:1;
u32 sb0_1:1;
u32 bafferable:1;
u32 cacheable:1;
u32 permission:2;
u32 sb0_6_8:3;
u32 permissionEx:1;
u32 shared:1;
u32 notGlobal:1;
u32 memoryTypeEx:3;
u32 executeNever:1;
u32 base:16;
}
OSMMUv6LargePage, OSMMUv6Page64KB;
typedef struct
{
u32 executeNever:1;
u32 sb1_1:1;
u32 bafferable:1;
u32 cacheable:1;
u32 permission:2;
u32 memoryTypeEx:3;
u32 permissionEx:1;
u32 shared:1;
u32 notGlobal:1;
u32 base:20;
}
OSMMUv6SmallPage, OSMMUv6Page4KB;
#endif // SDK_ASM
// MMUv6 Table Formats
// Supersection
#ifndef SDK_ASM
#define HW_MMU6_T1_SUSEC_PACK( paddr, apx, rgt, nglobal, sh, xn ) \
\
( ((paddr) & HW_MMU6_T1_SUSEC_BASE_MASK) \
| ((apx) << HW_MMU6_T1_APX_SFT) \
| ((rgt) << HW_MMU6_T1_RGT_SFT) \
| ((nglobal) ? HW_MMU6_T1_NGLOBAL : 0) \
| ((sh) ? HW_MMU6_T1_SHARED : 0) \
| ((xn) ? HW_MMU6_T1_XN : 0) \
| HW_MMU6_T1_SUSEC_SB1 )
#endif
#define HW_MMU6_T1_SUSEC_SB1 0x00040002 // Should be 1
#define HW_MMU6_T1_SUSEC_BASE_MASK 0xff000000 // Base address (per 16MB)
#define HW_MMU6_T1_SUSEC_BASE_SFT 24
#define HW_MMU6_T1_SUSEC_SIZE 0x01000000
#define HW_MMU6_T1_SUSEC_ALIAS_SIZE 0x00100000
// Section
#ifndef SDK_ASM
#define HW_MMU6_T1_SEC_PACK( paddr, apx, rgt, nglobal, sh, xn, domain ) \
\
( ((paddr) & HW_MMU6_T1_SEC_BASE_MASK) \
| ((apx) << HW_MMU6_T1_APX_SFT) \
| ((rgt) << HW_MMU6_T1_RGT_SFT) \
| ((nglobal) ? HW_MMU6_T1_NGLOBAL : 0) \
| ((sh) ? HW_MMU6_T1_SHARED : 0) \
| ((xn) ? HW_MMU6_T1_XN : 0) \
| ((domain) << HW_MMU6_T1_DOMAIN_SFT) \
| HW_MMU6_T1_SEC_SB1 )
#endif
#define HW_MMU6_T1_SEC_SB1 0x00000002 // Should be 1
#define HW_MMU6_T1_SEC_BASE_MASK 0xfff00000 // Base address (per 1MB)
#define HW_MMU6_T1_SEC_BASE_SFT 20
#define HW_MMU6_T1_SEC_SIZE 0x00100000
// Coarse page table
#ifndef SDK_ASM
#define HW_MMU6_T1_COURSE_PACK( paddr, domain ) \
\
( ((paddr) & HW_MMU6_T1_CORS_MASK) \
| ((domain) << HW_MMU6_T1_DOMAIN_SFT) \
| HW_MMU6_T1_CORS_SB1 )
#endif
#define HW_MMU6_T1_CORS_SB1 0x00000001 // Should be 1
#define HW_MMU6_T1_CORS_MASK 0xfffffc00 // Coarse page table address (per 1KB)
#define HW_MMU6_T1_CORS_SFT 12
#define HW_MMU6_T1_CORS_SIZE 0x00000400
// Supersection/Section/Coarse Common
#define HW_MMU6_T1_ECC_E 0x00000200 // ECC enable
// Section/Coarse Common
#define HW_MMU6_T1_DOMAIN_MASK 0x000001e0 // Domain
#define HW_MMU6_T1_DOMAIN_SFT 5
// Supersection/Section Common
#define HW_MMU6_T1_NGLOBAL 0x00020000 // Not Global (at subpages disabled)
#define HW_MMU6_T1_GLOBAL 0x00000000 // Global
#define HW_MMU6_T1_ASID_ENABLE HW_MMU6_T1_NGLOBAL
#define HW_MMU6_T1_SHARED 0x00010000 // Shared (Normal region only, at subpages disabled)
#define HW_MMU6_T1_APX_MASK 0x00008c00 // Access Permissions Extension (at subpages disabled)
#define HW_MMU6_T1_XN 0x00000010 // Execute Never (at subpages disabled)
#define HW_MMU6_T1_RGT_MASK 0x0000700c // Region Type
#define HW_MMU6_T1_APX_SFT 10
#define HW_MMU6_T1_RGT_SFT 2
#define HW_MMU6_T1_APX_NA HW_MMU6_APX_NA
#define HW_MMU6_T1_APX_S_RW_U_NA HW_MMU6_APX_S_RW_U_NA
#define HW_MMU6_T1_APX_S_RW_U_RO HW_MMU6_APX_S_RW_U_RO
#define HW_MMU6_T1_APX_ALL HW_MMU6_APX_ALL
#define HW_MMU6_T1_APX_S_RO_U_NA HW_MMU6_APX_S_RO_U_NA
#define HW_MMU6_T1_APX_S_RO_U_RO HW_MMU6_APX_S_RO_U_RO
#define HW_MMU6_T1_RGT_STRONG_ORDER 0x0000 // Strongly Ordered, regardless of the S bit in the page table
#define HW_MMU6_T1_RGT_SHARED_DEV 0x0001 // Shared Device, regardless of the S bit in the page table
#define HW_MMU6_T1_RGT_NSHARED_DEV 0x0800 // Non-Shared Device, regardless of the S bit in the page table
#define HW_MMU6_T1_RGT_L1C_NC_NB 0x1000 // L1C Noncachable, Unbuffered
#define HW_MMU6_T1_RGT_L1C_WB_WA 0x1001 // L1C Write-back Write-allocate, Buffered
#define HW_MMU6_T1_RGT_L1L2C_NC 0x0400 // L1C and L2C Noncachable
#define HW_MMU6_T1_RGT_L1L2C_WB_WA 0x0403 // L1C and L2C Write-Back, Allocate on Write
// MMUv6 L2 Table Formats
// Large page
#ifndef SDK_ASM
#define HW_MMU6_T2_LP_PACK( paddr, apx, rgt, nglobal, sh, xn ) \
\
( ((paddr) & HW_MMU6_T2_LP_BASE_MASK) \
| ((apx) << HW_MMU6_T2_APX_SFT) \
| ((rgt) << HW_MMU6_T2_LP_RGT_SFT) \
| ((nglobal) ? HW_MMU6_T2_NGLOBAL : 0) \
| ((sh) ? HW_MMU6_T2_SHARED : 0) \
| ((xn) ? HW_MMU6_T2_LP_XN : 0) \
| HW_MMU6_T2_LP_SB1 )
#endif
#define HW_MMU6_T2_LP_SB1 0x00000001 // Should be 1
#define HW_MMU6_T2_LP_BASE_MASK 0xffff0000 // Base address (per 64KB)
#define HW_MMU6_T2_LP_XN 0x00008000 // Execute Never (at subpages disabled)
#define HW_MMU6_T2_LP_RGT_MASK 0x0000700c // Region Type
#define HW_MMU6_T2_LP_BASE_SFT 16
#define HW_MMU6_T2_LP_RGT_SFT 2
#define HW_MMU6_T2_LP_RGT_STRONG_ORDER HW_MMU6_T1_RGT_STRONG_ORDER
#define HW_MMU6_T2_LP_RGT_SHARED_DEV HW_MMU6_T1_RGT_SHARED_DEV
#define HW_MMU6_T2_LP_RGT_NSHARED_DEV HW_MMU6_T1_RGT_NSHARED_DEV
#define HW_MMU6_T2_LP_RGT_L1C_NC_NB HW_MMU6_T1_RGT_L1C_NC_NB
#define HW_MMU6_T2_LP_RGT_L1C_WB_WA HW_MMU6_T1_RGT_L1C_WB_WA
#define HW_MMU6_T2_LP_RGT_L1L2C_NC HW_MMU6_T1_RGT_L1L2C_NC
#define HW_MMU6_T2_LP_RGT_L1L2C_WB_WA HW_MMU6_T1_RGT_L1L2C_WB_WA
#define HW_MMU6_T2_LP_SIZE 0x00010000
#define HW_MMU6_T2_LP_ALIAS_SIZE 0x00001000
// Small page
#ifndef SDK_ASM
#define HW_MMU6_T2_SP_PACK( paddr, apx, rgt, nglobal, sh, xn ) \
\
( ((paddr) & HW_MMU6_T2_SP_BASE_MASK) \
| ((apx) << HW_MMU6_T2_APX_SFT) \
| ((rgt) << HW_MMU6_T2_SP_RGT_SFT) \
| ((nglobal) ? HW_MMU6_T2_NGLOBAL : 0) \
| ((sh) ? HW_MMU6_T2_SHARED : 0) \
| ((xn) ? HW_MMU6_T2_SP_XN : 0) \
| HW_MMU6_T2_SP_SB1 )
#endif
#define HW_MMU6_T2_SP_SB1 0x00000002 // Should be 1
#define HW_MMU6_T2_SP_BASE_MASK 0xfffff000 // Base address (per 4KB)
#define HW_MMU6_T2_SP_XN 0x00000001 // Execute Never (at subpages disabled)
#define HW_MMU6_T2_SP_RGT_MASK 0x000001cc // Region Type
#define HW_MMU6_T2_SP_BASE_SFT 12
#define HW_MMU6_T2_SP_RGT_SFT 2
#define HW_MMU6_T2_SP_RGT_STRONG_ORDER 0x00 // Strongly Ordered, regardless of the S bit in the page table
#define HW_MMU6_T2_SP_RGT_SHARED_DEV 0x01 // Shared Device, regardless of the S bit in the page table
#define HW_MMU6_T2_SP_RGT_NSHARED_DEV 0x20 // Non-Shared Device, regardless of the S bit in the page table
#define HW_MMU6_T2_SP_RGT_L1C_NC_NB 0x40 // L1C Noncachable, Unbuffered
#define HW_MMU6_T2_SP_RGT_L1C_WB_WA 0x41 // L1C Write-back Write-allocate, Buffered
#define HW_MMU6_T2_SP_RGT_L1L2C_NC 0x10 // L1C and L2C Noncachable
#define HW_MMU6_T2_SP_RGT_L1L2C_WB_WA 0x13 // L1C and L2C Write-Back, Allocate on Write
#define HW_MMU6_T2_SP_SIZE 0x00001000
// LargePage/SmallPage Common
#define HW_MMU6_T2_NGLOBAL 0x00000800 // Not Global (at subpages disabled)
#define HW_MMU6_T2_GLOBAL 0x00000000 // Global
#define HW_MMU6_T2_ASID_ENABLE HW_MMU6_T2_NGLOBAL
#define HW_MMU6_T2_SHARED 0x00000400 // Shared (Normal region only, at subpages disabled)
#define HW_MMU6_T2_APX_MASK 0x00000230 // Access Permissions Extension (at subpages disabled)
#define HW_MMU6_T2_APX_SFT 4
#define HW_MMU6_T2_APX_NA HW_MMU6_APX_NA
#define HW_MMU6_T2_APX_S_RW_U_NA HW_MMU6_APX_S_RW_U_NA
#define HW_MMU6_T2_APX_S_RW_U_RO HW_MMU6_APX_S_RW_U_RO
#define HW_MMU6_T2_APX_ALL HW_MMU6_APX_ALL
#define HW_MMU6_T2_APX_S_RO_U_NA HW_MMU6_APX_S_RO_U_NA
#define HW_MMU6_T2_APX_S_RO_U_RO HW_MMU6_APX_S_RO_U_RO
// Supersection/Section/Coarse/LargePage/SmallPage Common
#define HW_MMU6_APX_NA 0x00 // Access denied
#define HW_MMU6_APX_S_RW_U_NA 0x01 // Supervisor access only
#define HW_MMU6_APX_S_RW_U_RO 0x02 // Supervisor full access, User read only
#define HW_MMU6_APX_ALL 0x03 // Full access
#define HW_MMU6_APX_S_RO_U_NA 0x21 // Supervisor read only
#define HW_MMU6_APX_S_RO_U_RO 0x23 // Supervisor/User read only
#define HW_MMU6_CBA_NC_NB 0 // Noncachable, Unbuffered
#define HW_MMU6_CBA_WB_WA 1 // Write-back Write-allocate, Buffered
#ifdef __cplusplus
} // extern "C"
#endif
// CTR_HW_ARM11_MMU_TABLE_H_
#endif

104
trunk/include/ctr/hw/ARM11/vfp.h Normal file
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@ -0,0 +1,104 @@
/*---------------------------------------------------------------------------*
Project: CtrFirm - include - ctr - HW - ARM11
File: vfp.h
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-11-27#$
$Rev: 37 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
#ifndef CTR_HW_ARM11_VFP_H_
#define CTR_HW_ARM11_VFP_H_
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------------------------
// VFP Control Registers
//----------------------------------------------------------------------
// Floating-Point Exception Register
#define HW_FPEXC_EXCEPTION_STATE 0x80000000 // in exception state
#define HW_FPEXC_VFP_ENABLE 0x40000000 // VFP enable
#define HW_FPEXC_FPINST2_VALID 0x10000000 // FPINST2 instruction valid flag
#define HW_FPEXC_VEC_ITR_MASK 0x00000700 // Vector iteration count
#define HW_FPEXC_INPUT_EXCEPTION 0x00000080 // Input exception flag
#define HW_FPEXC_POTENT_UNDERFLOW 0x00000008 // Potential underflow flag
#define HW_FPEXC_POTENT_OVERFLOW 0x00000004 // Potential overflow flag
#define HW_FPEXC_POTENT_INVALID 0x00000001 // Potential invalid operation flag
#define HW_FPEXC_VEC_ITR_SFT 8
// Floating-Point Status and Control Register
#define HW_FPSCR_N_FLAG 0x80000000 // Negative/Less than flag
#define HW_FPSCR_Z_FLAG 0x40000000 // Zero flag
#define HW_FPSCR_C_FLAG 0x20000000 // Carry/Borrow/Extend flag
#define HW_FPSCR_V_FLAG 0x10000000 // Overflow flag
#define HW_FPSCR_DEFAULT_NAN_MODE 0x02000000 // Default NaN mode (for std mode & fast mode)
#define HW_FPSCR_FLASH_TO_ZERO_MODE 0x01000000 // Flush-to-zero mode (for std mode & fast mode)
#define HW_FPSCR_ROUND_MODE_MASK 0x00c00000 // Rounding mode
#define HW_FPSCR_VEC_STRIDE_MASK 0x00300000 // Vector stride
#define HW_FPSCR_VEC_LENGTH_MASK 0x00070000 // Vector length
#define HW_FPSCR_IDE_ENABLE 0x00008000 // Input Subnormal exception enable
#define HW_FPSCR_IXE_ENABLE 0x00001000 // Inexact exception enable
#define HW_FPSCR_UFE_ENABLE 0x00000800 // Underflow exception enable
#define HW_FPSCR_OFE_ENABLE 0x00000400 // Overflow exception enable
#define HW_FPSCR_DZE_ENABLE 0x00000200 // Division by Zero exception enable
#define HW_FPSCR_IOE_ENABLE 0x00000100 // Invalid Operation exception enable
#define HW_FPSCR_IDC 0x00000080 // Input Subnormal cumulative flag
#define HW_FPSCR_IXC 0x00000010 // Inexact cumulative flag
#define HW_FPSCR_UFC 0x00000008 // Underflow cumulative flag
#define HW_FPSCR_OFC 0x00000004 // Overflow cumulative flag
#define HW_FPSCR_DZC 0x00000002 // Division by Zero cumulative flag
#define HW_FPSCR_IOC 0x00000001 // Invalid Operation cumulative flag
#define HW_FPSCR_ROUND_MODE_SFT 22
#define HW_FPSCR_VEC_STRIDE_SFT 20
#define HW_FPSCR_VEC_LENGTH_SFT 16
#define HW_FPSCR_ROUND_NEAR_MODE 0 // Round to nearest mode
#define HW_FPSCR_ROUND_PLUS_MODE 1 // Round towards plus infinity mode
#define HW_FPSCR_ROUND_MINUS_MODE 2 // Round towards minus infinity mode
#define HW_FPSCR_ROUND_ZERO_MODE 3 // Round towards zero mode
#define HW_FPSCR_VEC_STRIDE_1 0 // Vector stride 1
#define HW_FPSCR_VEC_STRIDE_2 3 // Vector stride 2
#define HW_FPSCR_VEC_LENGTH_1 0 // Vector length 1
#define HW_FPSCR_VEC_LENGTH_2 1 // Vector length 2
#define HW_FPSCR_VEC_LENGTH_3 2 // Vector length 3
#define HW_FPSCR_VEC_LENGTH_4 3 // Vector length 4
#define HW_FPSCR_VEC_LENGTH_5 4 // Vector length 5
#define HW_FPSCR_VEC_LENGTH_6 5 // Vector length 6
#define HW_FPSCR_VEC_LENGTH_7 6 // Vector length 7
#define HW_FPSCR_VEC_LENGTH_8 7 // Vector length 8
// Floating-Point Instruction Register
// Floating-Point Instruction Register 2
#ifdef __cplusplus
} // extern "C"
#endif
// CTR_HW_ARM11_VFP_H_
#endif

5
trunk/include/ctr/hw/ARM9/mmap_global.h
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@ -68,7 +68,10 @@ extern "C" {
//----------------------------- System ROM
#define HW_BIOS 0xffff0000
#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
#define HW_BIOS_SIZE 0x00010000
#define HW_BIOS_EX HW_BIOS_END
#define HW_BIOS_EX_END (HW_BIOS_EX + HW_BIOS_EX_SIZE)
#define HW_BIOS_SIZE 0x00008000
#define HW_BIOS_EX_SIZE 0x00008000
#define HW_RESET_VECTOR HW_BIOS

74
trunk/include/ctr/hw/common/arm_reg_common.h Normal file
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@ -0,0 +1,74 @@
/*---------------------------------------------------------------------------*
Project: CtrFirm - include - ctr - HW - common
File: arm_reg_common.h
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-11-27#$
$Rev: 37 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
#ifndef CTR_HW_ARM_REG_COMMON_H_
#define CTR_HW_ARM_REG_COMMON_H_
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------------------------
// Program Status Register
//----------------------------------------------------------------------
#define HW_PSR_CPU_MODE_MASK 0x1f // CPU mode
#define HW_PSR_USR_MODE 0x10 // User mode
#define HW_PSR_FIQ_MODE 0x11 // FIQ mode
#define HW_PSR_IRQ_MODE 0x12 // IRQ mode
#define HW_PSR_SVC_MODE 0x13 // Supervisor mode
#define HW_PSR_ABORT_MODE 0x17 // Abort mode (prefetch/Data)
#define HW_PSR_UNDEF_MODE 0x1b // Undefined instruction mode
#define HW_PSR_SYS_MODE 0x1f // System mode
#define HW_PSR_ARM_STATE 0x0 // ARM state
#define HW_PSR_THUMB_STATE 0x20 // Thumb state
#define HW_PSR_FIQ_DISABLE 0x40 // FIQ Disable
#define HW_PSR_IRQ_DISABLE 0x80 // IRQ Disable
#define HW_PSR_IRQ_FIQ_DISABLE 0xc0 // IRQ & FIQ Disable
#ifdef SDK_ARM9
#else // SDK_ARM11
#define HW_PSR_IMPRECISE_ABORT 0x00000100 // Imprecise Abort
#define HW_PSR_DATA_LITTLE_ENDIAN 0x00000000 // Data Little Endian
#define HW_PSR_DATA_BIG_ENDIAN 0x00000200 // Data Big Endian
#define HW_PSR_SIMD_GE0 0x00010000 // SIMD greater-than-or-equal
#define HW_PSR_SIMD_GE1 0x00020000
#define HW_PSR_SIMD_GE2 0x00040000
#define HW_PSR_SIMD_GE3 0x00080000
#define HW_PSR_JAVA_STATE 0x01000000 // JAVA state
#endif // SDK_ARM11
#define HW_PSR_Q_FLAG 0x08000000 // Sticky Overflow (Q) flag
#define HW_PSR_V_FLAG 0x10000000 // Overflow flag
#define HW_PSR_C_FLAG 0x20000000 // Carry/Borrow/Extend flag
#define HW_PSR_Z_FLAG 0x40000000 // Zero flag
#define HW_PSR_N_FLAG 0x80000000 // Negative/Less than flag
#ifdef __cplusplus
} // extern "C"
#endif
// CTR_HW_ARM_REG_COMMON_H_
#endif