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small fix

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@250 4ee2a332-4b2b-5046-8439-1ba90f034370
This commit is contained in:
yutaka 2007-08-24 02:40:12 +00:00
parent 48d5840321
commit fe768963d2
1 changed files with 4 additions and 4 deletions
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8
build/libraries/camera/ARM7/MT9V113-MTM10-3.ini
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@ -180,7 +180,7 @@ BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0021 //PLL Dividers = 0x21 REG = 0x0010, 0x0021 //PLL Dividers = 0x21
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0 REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 1 // Allow PLL to lock DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
@ -358,7 +358,7 @@ BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0335 //PLL Dividers = 0x335 REG = 0x0010, 0x0335 //PLL Dividers = 0x335
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0 REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 1 // Allow PLL to lock DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
@ -643,7 +643,7 @@ BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0010 //PLL Dividers = 0x10 REG = 0x0010, 0x0010 //PLL Dividers = 0x10
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0 REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 1 // Allow PLL to lock DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
@ -820,7 +820,7 @@ BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0110 //PLL Dividers = 0x110 REG = 0x0010, 0x0110 //PLL Dividers = 0x110
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0 REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 1 // Allow PLL to lock DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF