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fe768963d2
twl_wrapsdk/build/libraries/camera/ARM7/MT9V113-MTM10-3.ini
yutaka fe768963d2 small fix 
git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@250 4ee2a332-4b2b-5046-8439-1ba90f034370
2007-08-24 02:40:12 +00:00

1389 lines
49 KiB
INI
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;**************************************************************************************
; Copyright 2006 Micron Technology, Inc. All rights reserved.
;
;
; No permission to use, copy, modify, or distribute this software and/or
; its documentation for any purpose has been granted by Micron Technology, Inc.
; If any such permission has been granted ( by separate agreement ), it
; is required that the above copyright notice appear in all copies and
; that both that copyright notice and this permission notice appear in
; supporting documentation, and that the name of Micron Technology, Inc. or any
; of its trademarks may not be used in advertising or publicity pertaining
; to distribution of the software without specific, written prior permission.
;
;
; This software and any associated documentation are provided "AS IS" and
; without warranty of any kind. MICRON TECHNOLOGY, INC. EXPRESSLY DISCLAIMS
; ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO, NONINFRINGEMENT
; OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
; FOR A PARTICULAR PURPOSE. MICRON DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED
; IN THIS SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS SOFTWARE
; WILL BE UNINTERRUPTED OR ERROR-FREE. FURTHERMORE, MICRON DOES NOT WARRANT OR
; MAKE ANY REPRESENTATIONS REGARDING THE USE OR THE RESULTS OF THE USE OF ANY
; ACCOMPANYING DOCUMENTATION IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY,
; OR OTHERWISE.
;**************************************************************************************/
;
; Default INI file for the MI-0380-REV1
; <<< MT9V113-MTM10.ini >>>
; $Revision: 1.3 $
; $Date: 2007/04/22 07:13:21 $
;
; This file holds groups of register presets (sections) specific for this sensor. The
; presets allow you to overwrite the power-on default settings with optimized register
; settings.
; The [Default Registers] section contains all optimized register settings for running
; the sensor in the demo environment. Other sections include settings optimized for a
; variety of situations like: Running at different master clock speeds, running under
; different lighting situations, running with different lenses, etc.
; Most of the demonstration software (DevWare, SensorDemo, ...) make use of this file
; to load and store the user presets.
;
; Keyname description:
; REG = assign a new register value
; BITFIELD = do a READ-MODIFY-WRITE to part of a register. The part is defined as a mask.
; LOAD = load an alternate section from this section
; STATE = set non-register state
; DELAY = delay a certain amount of milliseconds before continuing
;
; Keyname format:
; REG = [<page>,] <address>, <value> //<comment>
; BITFIELD = [<page>,] <address>, <mask>, <value>
; Some examples:
; BITFIELD=2, 0x05, 0x0020, 1 //for register 5 on page 2, set the 6th bit to 1
; BITFIELD=0x06, 0x000F, 0 //for register 6, clear the first 4 bits
; LOAD = <section>
; STATE = <state>, <value>
; DELAY = <milliseconds>
;
; <page> Optional address space for this register. Some sensors (mostly SOC's)
; have multiple register pages (see the sensor spec or developer's guide)
; <address> the register address
; <value> the new value to assign to the register
; <mask> is the part of a register value that needs to be updated with a new value
; <section> the name of another section to load
; <state> non-register program state names [do not modify]
; <milliseconds> wait for this ammount of milliseconds before continuing
; <comment> Some form of C-style comments are supported in this .ini file
;
;*************************************************************************************/
[Default Registers]
LOAD=Initialize Camera
LOAD=Image Setting ExtClk=16.75MHz Op_Pix=16.75MHz
//LOAD=Image Setting ExtClk=12MHz Op_Pix=24MHz
//LOAD=Image Setting ExtClk=6.75MHz Op_Pix=27.5MHz 15fps
//LOAD=Image Setting ExtClk=16.76MHz Op_Pix=27.5MHz 15fps
//LOAD=Image Setting ExtClk=16.76MHz Op_Pix=8.38MHz
LOAD=Lens Correction
LOAD=Auto Exposure
LOAD=Auto White Balance
LOAD=Gamma Correction
LOAD=Sharpness : 0
//LOAD=Refresh
LOAD=Image Size : QVGA
[Initialize Camera]
REG = 0x001A, 0x0003// Activate Soft Reset & MIPI Reset
DELAY = 1 // Wait 1ms for internal reset cycle (6000 EXTCLK cycles) using a 6.75Mhz clock this will be approx 0.88ms
REG = 0x001A, 0x0000 // Deactivate both soft reset, MIPI reset
DELAY = 1
REG = 0x0018, 0x4028 // Enable STANDBY mode, Bit(3)
//REG = 0x001A, 0x0200 // Enable parallel port:bit(9) & Output enable: Bit(8) // Yutaka: no output
REG = 0x001E, 0x0777 // Program to slowest SLEW rate
REG = 0x0016, 0x42DF // Invert PIXCLK output to interface with Micron DEMO2 board
// Enable EXTCLK bit9
////////////////////////////////////////////////////////////////////////////////
; This file was generated by: MT9V113 (SOC0380) Register Wizard
; Version: 2.8.0.53 Build Date: 06/06/2007
;
; [PLL PARAMETERS]
;
; Bypass PLL: Unchecked
; Input Frequency: 6.750
; Use Min Freq.: Unchecked
; Target System Frequency: 27.844
; Target VCO Frequency: Unspecified
; "M" Value: Unspecified
; "N" Value: Unspecified
;
; Target PLL Frequency: 27.500 MHz
; MT9V113 Input Clock Frequency: 6.750 MHz
; MT9V113 Internal Clock Frequency: 27.844 MHz
; MT9V113 SOC Clock Frequency: 27.844 MHz
; M = 33
; N = 0
; Fpdf = 6.750 MHz
; Fvco = 445.500 MHz
;
; [CONTEXT A PARAMETERS]
;
; Requested Frames Per Second: 14.645
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context B Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 68.2827 msec
; Max Frame Clocks: 950623.0 clocks (13.922 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 641 blank = 1129 total
; Extra Delay: 5 clocks
;
; Actual Frame Clocks: 950623 clocks
; Row Time: 60.480 usec / 842 clocks
; Frame time: 68.282685 msec
; Frames per Sec: 14.645 fps
;
; 50Hz Flicker Period: 165.34 lines
; 60Hz Flicker Period: 137.79 lines
;
; [CONTEXT B PARAMETERS]
;
; Requested Frames Per Second: 14.645
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context A Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 68.2827 msec
; Max Frame Clocks: 950623.0 clocks (13.922 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 641 blank = 1129 total
; Extra Delay: 5 clocks
;
; Actual Frame Clocks: 950623 clocks
; Row Time: 60.480 usec / 842 clocks
; Frame time: 68.282685 msec
; Frames per Sec: 14.645 fps
;
; 50Hz Flicker Period: 165.34 lines
; 60Hz Flicker Period: 137.79 lines
;
;
[Image Setting ExtClk=6.75MHz Op_Pix=27.5MHz 15fps]
BITFIELD= 0x14, 1, 1 // Bypass PLL
BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0021 //PLL Dividers = 0x21
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
REG = 0x98C, 0x2703 //Output Width (A)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2705 //Output Height (A)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x2707 //Output Width (B)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2709 //Output Height (B)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x270D //Row Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x270F //Column Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2711 //Row End (A)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2713 //Column End (A)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x2715 //Row Speed (A)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x2717 //Read Mode (A)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x2719 //sensor_fine_correction (A)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x271B //sensor_fine_IT_min (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271D //sensor_fine_IT_max_margin (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271F //Frame Lines (A)
REG = 0x990, 0x0469 // = 1129
REG = 0x98C, 0x2721 //Line Length (A)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2723 //Row Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2725 //Column Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2727 //Row End (B)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2729 //Column End (B)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x272B //Row Speed (B)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x272D //Read Mode (B)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x272F //sensor_fine_correction (B)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x2731 //sensor_fine_IT_min (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2733 //sensor_fine_IT_max_margin (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2735 //Frame Lines (B)
REG = 0x990, 0x0469 // = 1129
REG = 0x98C, 0x2737 //Line Length (B)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2739 //Crop_X0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273B //Crop_X1 (A)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x273D //Crop_Y0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273F //Crop_Y1 (A)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x2747 //Crop_X0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x2749 //Crop_X1 (B)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x274B //Crop_Y0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x274D //Crop_Y1 (B)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x222D //R9 Step
REG = 0x990, 0x008A // = 138
REG = 0x98C, 0xA408 //search_f1_50
REG = 0x990, 0x19 // = 25
REG = 0x98C, 0xA409 //search_f2_50
REG = 0x990, 0x1C // = 28
REG = 0x98C, 0xA40A //search_f1_60
REG = 0x990, 0x1F // = 31
REG = 0x98C, 0xA40B //search_f2_60
REG = 0x990, 0x22 // = 34
REG = 0x98C, 0x2411 //R9_Step_60_A
REG = 0x990, 0x008A // = 138
REG = 0x98C, 0x2413 //R9_Step_50_A
REG = 0x990, 0x00A5 // = 165
REG = 0x98C, 0x2415 //R9_Step_60_B
REG = 0x990, 0x008A // = 138
REG = 0x98C, 0x2417 //R9_Step_50_B
REG = 0x990, 0x00A5 // = 165
REG = 0x98C, 0xA40D //Stat_min
REG = 0x990, 0x02 // = 2
REG = 0x98C, 0xA410 //Min_amplitude
REG = 0x990, 0x01 // = 1
////////////////////////////////////////////////////////////////////////////////
; This file was generated by: MT9V113 (SOC0380) Register Wizard
; Version: 2.9.0.2 Build Date: 06/29/2007
;
; [PLL PARAMETERS]
;
; Bypass PLL: Unchecked
; Input Frequency: 16.760
; Use Min Freq.: Unchecked
; Target System Frequency: 27.759
; Target VCO Frequency: Unspecified
; "M" Value: Unspecified
; "N" Value: Unspecified
;
; Target PLL Frequency: 27.500 MHz
; MT9V113 Input Clock Frequency: 16.760 MHz
; MT9V113 Internal Clock Frequency: 27.759 MHz
; MT9V113 SOC Clock Frequency: 27.759 MHz
; M = 53
; N = 3
; Fpdf = 4.190 MHz
; Fvco = 444.140 MHz
;
; [CONTEXT A PARAMETERS]
;
; Requested Frames Per Second: 15.000
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context B Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 66.6667 msec
; Max Frame Clocks: 925291.6 clocks (13.879 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 610 blank = 1098 total
; Extra Delay: 775 clocks
;
; Actual Frame Clocks: 925291 clocks
; Row Time: 60.666 usec / 842 clocks
; Frame time: 66.666619 msec
; Frames per Sec: 15 fps
;
; 50Hz Flicker Period: 164.84 lines
; 60Hz Flicker Period: 137.37 lines
;
; [CONTEXT B PARAMETERS]
;
; Requested Frames Per Second: 15.000
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context A Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 66.6667 msec
; Max Frame Clocks: 925291.6 clocks (13.879 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 610 blank = 1098 total
; Extra Delay: 775 clocks
;
; Actual Frame Clocks: 925291 clocks
; Row Time: 60.666 usec / 842 clocks
; Frame time: 66.666619 msec
; Frames per Sec: 15 fps
;
; 50Hz Flicker Period: 164.84 lines
; 60Hz Flicker Period: 137.37 lines
;
;
[Image Setting ExtClk=16.76MHz Op_Pix=27.5MHz 15fps]
BITFIELD= 0x14, 1, 1 // Bypass PLL
BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0335 //PLL Dividers = 0x335
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
REG = 0x98C, 0x2703 //Output Width (A)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2705 //Output Height (A)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x2707 //Output Width (B)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2709 //Output Height (B)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x270D //Row Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x270F //Column Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2711 //Row End (A)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2713 //Column End (A)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x2715 //Row Speed (A)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x2717 //Read Mode (A)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x2719 //sensor_fine_correction (A)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x271B //sensor_fine_IT_min (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271D //sensor_fine_IT_max_margin (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271F //Frame Lines (A)
REG = 0x990, 0x044A // = 1098
REG = 0x98C, 0x2721 //Line Length (A)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2723 //Row Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2725 //Column Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2727 //Row End (B)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2729 //Column End (B)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x272B //Row Speed (B)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x272D //Read Mode (B)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x272F //sensor_fine_correction (B)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x2731 //sensor_fine_IT_min (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2733 //sensor_fine_IT_max_margin (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2735 //Frame Lines (B)
REG = 0x990, 0x044A // = 1098
REG = 0x98C, 0x2737 //Line Length (B)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2739 //Crop_X0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273B //Crop_X1 (A)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x273D //Crop_Y0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273F //Crop_Y1 (A)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x2747 //Crop_X0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x2749 //Crop_X1 (B)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x274B //Crop_Y0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x274D //Crop_Y1 (B)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x222D //R9 Step
REG = 0x990, 0x0089 // = 137
REG = 0x98C, 0xA408 //search_f1_50
REG = 0x990, 0x19 // = 25
REG = 0x98C, 0xA409 //search_f2_50
REG = 0x990, 0x1C // = 28
REG = 0x98C, 0xA40A //search_f1_60
REG = 0x990, 0x1F // = 31
REG = 0x98C, 0xA40B //search_f2_60
REG = 0x990, 0x22 // = 34
REG = 0x98C, 0x2411 //R9_Step_60_A
REG = 0x990, 0x0089 // = 137
REG = 0x98C, 0x2413 //R9_Step_50_A
REG = 0x990, 0x00A5 // = 165
REG = 0x98C, 0x2415 //R9_Step_60_B
REG = 0x990, 0x0089 // = 137
REG = 0x98C, 0x2417 //R9_Step_50_B
REG = 0x990, 0x00A5 // = 165
REG = 0x98C, 0xA40D //Stat_min
REG = 0x990, 0x02 // = 2
REG = 0x98C, 0xA410 //Min_amplitude
REG = 0x990, 0x01 // = 1
////////////////////////////////////////////////////////////////////////////////
[Image Setting ExtClk=16.76MHz Op_Pix=8.38MHz]
BITFIELD= 0x14, 1, 1 // Bypass PLL
BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0518 // PLL DIVIDERS (N=5, M=24)
REG = 0x0012, 0x0000 // PLL P3 DIVIDERS
REG = 0x0014, 0x2147 // Enable PLL and start initialization [1]
DELAY = 10 // Wait for 10us to get PLL lock
REG = 0x0014, 0x2047 // Reset the PLL internal counter [8]
DELAY = 10 // Wait for 10us
REG = 0x0014, 0x2046 // Turn off PLL initialization process [0]
DELAY = 10 // Wait for 10us
REG = 0x0016, 0x42DF // Invert Pixclk output to interface with DEMO2 board [14]
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
REG = 0x98C, 0x2703 //Output Width (A)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2705 //Output Height (A)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x2707 //Output Width (B)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2709 //Output Height (B)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x270D //Row Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x270F //Column Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2711 //Row End (A)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2713 //Column End (A)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x2715 //Row Speed (A)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x2717 //Read Mode (A)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x2719 //sensor_fine_correction (A)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x271B //sensor_fine_IT_min (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271D //sensor_fine_IT_max_margin (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271F //Frame Lines (A)
REG = 0x990, 0x02D2 // = 722
REG = 0x98C, 0x2721 //Line Length (A)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2723 //Row Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2725 //Column Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2727 //Row End (B)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2729 //Column End (B)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x272B //Row Speed (B)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x272D //Read Mode (B)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x272F //sensor_fine_correction (B)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x2731 //sensor_fine_IT_min (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2733 //sensor_fine_IT_max_margin (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2735 //Frame Lines (B)
REG = 0x990, 0x02D2 // = 722
REG = 0x98C, 0x2737 //Line Length (B)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2739 //Crop_X0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273B //Crop_X1 (A)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x273D //Crop_Y0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273F //Crop_Y1 (A)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x2747 //Crop_X0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x2749 //Crop_X1 (B)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x274B //Crop_Y0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x274D //Crop_Y1 (B)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x222D //R9 Step
REG = 0x990, 0x0058 // = 88
REG = 0x98C, 0xA408 //search_f1_50
REG = 0x990, 0x0F // = 15
REG = 0x98C, 0xA409 //search_f2_50
REG = 0x990, 0x12 // = 18
REG = 0x98C, 0xA40A //search_f1_60
REG = 0x990, 0x13 // = 19
REG = 0x98C, 0xA40B //search_f2_60
REG = 0x990, 0x16 // = 22
REG = 0x98C, 0x2411 //R9_Step_60_A
REG = 0x990, 0x0058 // = 88
REG = 0x98C, 0x2413 //R9_Step_50_A
REG = 0x990, 0x006A // = 106
REG = 0x98C, 0x2415 //R9_Step_60_B
REG = 0x990, 0x0058 // = 88
REG = 0x98C, 0x2417 //R9_Step_50_B
REG = 0x990, 0x006A // = 106
REG = 0x98C, 0xA40D //Stat_min
REG = 0x990, 0x02 // = 2
REG = 0x98C, 0xA410 //Min_amplitude
REG = 0x990, 0x01 // = 1
////////////////////////////////////////////////////////////////////////////////
; This file was generated by: MT9V113 (SOC0380) Register Wizard
; Version: 2.9.0.2 Build Date: 06/29/2007
;
; [PLL PARAMETERS]
;
; Bypass PLL: Unchecked
; Input Frequency: 12.000
; Use Min Freq.: Unchecked
; Target System Frequency: 24.000
; Target VCO Frequency: Unspecified
; "M" Value: Unspecified
; "N" Value: Unspecified
;
; Target PLL Frequency: 24 MHz
; MT9V113 Input Clock Frequency: 12 MHz
; MT9V113 Internal Clock Frequency: 24 MHz
; MT9V113 SOC Clock Frequency: 24 MHz
; M = 16
; N = 0
; Fpdf = 12 MHz
; Fvco = 384 MHz
;
; [CONTEXT A PARAMETERS]
;
; Requested Frames Per Second: 15.000
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context B Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 66.6667 msec
; Max Frame Clocks: 800000.0 clocks (12 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 462 blank = 950 total
; Extra Delay: 100 clocks
;
; Actual Frame Clocks: 800000 clocks
; Row Time: 70.167 usec / 842 clocks
; Frame time: 66.666667 msec
; Frames per Sec: 15 fps
;
; 50Hz Flicker Period: 142.52 lines
; 60Hz Flicker Period: 118.76 lines
;
; [CONTEXT B PARAMETERS]
;
; Requested Frames Per Second: 14.645
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context A Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 68.2827 msec
; Max Frame Clocks: 819392.2 clocks (12 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 485 blank = 973 total
; Extra Delay: 126 clocks
;
; Actual Frame Clocks: 819392 clocks
; Row Time: 70.167 usec / 842 clocks
; Frame time: 68.282667 msec
; Frames per Sec: 14.645 fps
;
; 50Hz Flicker Period: 142.52 lines
; 60Hz Flicker Period: 118.76 lines
;
;
[Image Setting ExtClk=12MHz Op_Pix=24MHz]
BITFIELD= 0x14, 1, 1 // Bypass PLL
BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0010 //PLL Dividers = 0x10
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
REG = 0x98C, 0x2703 //Output Width (A)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2705 //Output Height (A)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x2707 //Output Width (B)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2709 //Output Height (B)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x270D //Row Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x270F //Column Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2711 //Row End (A)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2713 //Column End (A)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x2715 //Row Speed (A)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x2717 //Read Mode (A)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x2719 //sensor_fine_correction (A)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x271B //sensor_fine_IT_min (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271D //sensor_fine_IT_max_margin (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271F //Frame Lines (A)
REG = 0x990, 0x03B6 // = 950
REG = 0x98C, 0x2721 //Line Length (A)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2723 //Row Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2725 //Column Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2727 //Row End (B)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2729 //Column End (B)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x272B //Row Speed (B)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x272D //Read Mode (B)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x272F //sensor_fine_correction (B)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x2731 //sensor_fine_IT_min (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2733 //sensor_fine_IT_max_margin (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2735 //Frame Lines (B)
REG = 0x990, 0x03CD // = 973
REG = 0x98C, 0x2737 //Line Length (B)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2739 //Crop_X0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273B //Crop_X1 (A)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x273D //Crop_Y0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273F //Crop_Y1 (A)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x2747 //Crop_X0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x2749 //Crop_X1 (B)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x274B //Crop_Y0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x274D //Crop_Y1 (B)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x222D //R9 Step
REG = 0x990, 0x0077 // = 119
REG = 0x98C, 0xA408 //search_f1_50
REG = 0x990, 0x15 // = 21
REG = 0x98C, 0xA409 //search_f2_50
REG = 0x990, 0x18 // = 24
REG = 0x98C, 0xA40A //search_f1_60
REG = 0x990, 0x1A // = 26
REG = 0x98C, 0xA40B //search_f2_60
REG = 0x990, 0x1D // = 29
REG = 0x98C, 0x2411 //R9_Step_60_A
REG = 0x990, 0x0077 // = 119
REG = 0x98C, 0x2413 //R9_Step_50_A
REG = 0x990, 0x008F // = 143
REG = 0x98C, 0x2415 //R9_Step_60_B
REG = 0x990, 0x0077 // = 119
REG = 0x98C, 0x2417 //R9_Step_50_B
REG = 0x990, 0x008F // = 143
REG = 0x98C, 0xA40D //Stat_min
REG = 0x990, 0x02 // = 2
REG = 0x98C, 0xA410 //Min_amplitude
REG = 0x990, 0x01 // = 1
////////////////////////////////////////////////////////////////////////////////
; This file was generated by: MT9V113 (SOC0380) Register Wizard
; Version: 2.9.0.2 Build Date: 06/29/2007
;
; [PLL PARAMETERS]
;
; Bypass PLL: Unchecked
; Input Frequency: 20.000
; Use Min Freq.: Unchecked
; Target System Frequency: 20.000
; Target VCO Frequency: Unspecified
; "M" Value: Unspecified
; "N" Value: Unspecified
;
; Target PLL Frequency: 20 MHz
; MT9V113 Input Clock Frequency: 20 MHz
; MT9V113 Internal Clock Frequency: 20 MHz
; MT9V113 SOC Clock Frequency: 20 MHz
; M = 16
; N = 1
; Fpdf = 10 MHz
; Fvco = 320 MHz
;
; [CONTEXT A PARAMETERS]
;
; Requested Frames Per Second: 15.000
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context B Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 66.6667 msec
; Max Frame Clocks: 666666.6 clocks (10 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 303 blank = 791 total
; Extra Delay: 644 clocks
;
; Actual Frame Clocks: 666666 clocks
; Row Time: 84.200 usec / 842 clocks
; Frame time: 66.666600 msec
; Frames per Sec: 15 fps
;
; 50Hz Flicker Period: 118.76 lines
; 60Hz Flicker Period: 98.97 lines
;
; [CONTEXT B PARAMETERS]
;
; Requested Frames Per Second: 14.645
; Output Columns: 640
; Output Rows: 480
; Allow Skipping: Unchecked
; Use Context A Line Time: Unchecked
; Low Power: Unchecked
; Blanking Computation: HB Min then VB
;
; Max Frame Time: 68.2827 msec
; Max Frame Clocks: 682826.9 clocks (10 MHz)
; Pixel Clock: divided by 1
; Skip Mode: 1x cols, 1x rows, Bin Mode: No
; Horiz clks: 648 active + 194 blank = 842 total
; Vert rows: 488 active + 322 blank = 810 total
; Extra Delay: 806 clocks
;
; Actual Frame Clocks: 682826 clocks
; Row Time: 84.200 usec / 842 clocks
; Frame time: 68.282600 msec
; Frames per Sec: 14.645 fps
;
; 50Hz Flicker Period: 118.76 lines
; 60Hz Flicker Period: 98.97 lines
;
;
[Image Setting ExtClk=16.75MHz Op_Pix=16.75MHz]
BITFIELD= 0x14, 1, 1 // Bypass PLL
BITFIELD= 0X14, 2, 0 // Power-down PLL
REG = 0x0010, 0x0110 //PLL Dividers = 0x110
REG = 0x0012, 0x0000 //PLL P Dividers = 0x0
REG = 0x0014, 0x244B //PLL control: TEST_BYPASS on = 0x244B
DELAY = 5 // Allow PLL to lock
REG = 0x0014, 0x304B //PLL control: PLL_ENABLE on = 0x304B
POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20 // Verify PLL lock
BITFIELD= 0x14, 1, 0 //PLL_BYPASS_OFF
REG = 0x98C, 0x2703 //Output Width (A)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2705 //Output Height (A)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x2707 //Output Width (B)
REG = 0x990, 0x0280 // = 640
REG = 0x98C, 0x2709 //Output Height (B)
REG = 0x990, 0x01E0 // = 480
REG = 0x98C, 0x270D //Row Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x270F //Column Start (A)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2711 //Row End (A)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2713 //Column End (A)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x2715 //Row Speed (A)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x2717 //Read Mode (A)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x2719 //sensor_fine_correction (A)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x271B //sensor_fine_IT_min (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271D //sensor_fine_IT_max_margin (A)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x271F //Frame Lines (A)
REG = 0x990, 0x0317 // = 791
REG = 0x98C, 0x2721 //Line Length (A)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2723 //Row Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2725 //Column Start (B)
REG = 0x990, 0x004 // = 4
REG = 0x98C, 0x2727 //Row End (B)
REG = 0x990, 0x1EB // = 491
REG = 0x98C, 0x2729 //Column End (B)
REG = 0x990, 0x28B // = 651
REG = 0x98C, 0x272B //Row Speed (B)
REG = 0x990, 0x0001 // = 1
REG = 0x98C, 0x272D //Read Mode (B)
REG = 0x990, 0x0026 // = 38
REG = 0x98C, 0x272F //sensor_fine_correction (B)
REG = 0x990, 0x001A // = 26
REG = 0x98C, 0x2731 //sensor_fine_IT_min (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2733 //sensor_fine_IT_max_margin (B)
REG = 0x990, 0x006B // = 107
REG = 0x98C, 0x2735 //Frame Lines (B)
REG = 0x990, 0x032A // = 810
REG = 0x98C, 0x2737 //Line Length (B)
REG = 0x990, 0x034A // = 842
REG = 0x98C, 0x2739 //Crop_X0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273B //Crop_X1 (A)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x273D //Crop_Y0 (A)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x273F //Crop_Y1 (A)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x2747 //Crop_X0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x2749 //Crop_X1 (B)
REG = 0x990, 0x027F // = 639
REG = 0x98C, 0x274B //Crop_Y0 (B)
REG = 0x990, 0x0000 // = 0
REG = 0x98C, 0x274D //Crop_Y1 (B)
REG = 0x990, 0x01DF // = 479
REG = 0x98C, 0x222D //R9 Step
REG = 0x990, 0x0063 // = 99
REG = 0x98C, 0xA408 //search_f1_50
REG = 0x990, 0x11 // = 17
REG = 0x98C, 0xA409 //search_f2_50
REG = 0x990, 0x14 // = 20
REG = 0x98C, 0xA40A //search_f1_60
REG = 0x990, 0x15 // = 21
REG = 0x98C, 0xA40B //search_f2_60
REG = 0x990, 0x18 // = 24
REG = 0x98C, 0x2411 //R9_Step_60_A
REG = 0x990, 0x0063 // = 99
REG = 0x98C, 0x2413 //R9_Step_50_A
REG = 0x990, 0x0077 // = 119
REG = 0x98C, 0x2415 //R9_Step_60_B
REG = 0x990, 0x0063 // = 99
REG = 0x98C, 0x2417 //R9_Step_50_B
REG = 0x990, 0x0077 // = 119
REG = 0x98C, 0xA40D //Stat_min
REG = 0x990, 0x02 // = 2
REG = 0x98C, 0xA410 //Min_amplitude
REG = 0x990, 0x01 // = 1
[Viewfinder ON]
FIELD_WR = SEQ_CAP_MODE, VIDEO, 0 //capture parameters, VIDEO Off
REG = 0x98C, 0xA103 //Go to Preview Mode
REG = 0x990, 0x01 // = 1
[Viewfinder OFF]
FIELD_WR = SEQ_CAP_MODE, VIDEO, 1 //capture parameters, VIDEO On
REG = 0x98C, 0xA103 //Go to Capture Mode
REG = 0x990, 0x02 // = 2
[Video Capture ON]
FIELD_WR = SEQ_CAP_MODE, VIDEO, 1 //capture parameters, VIDEO On
REG = 0x98C, 0xA103 //Go to Capture Mode
REG = 0x990, 0x02 // = 2
[Video Capture OFF]
REG = 0x98C, 0xA103 //Go to Preview Mode
REG = 0x990, 0x01 // = 1
[Lens Calibration Setup]
REG=0x3330, 0x0140 //(2) OUTPUT_FORMAT_TEST
BITFIELD=0x3040, 0x002, 0
[Lens Calibration Exit]
BITFIELD=0x3040, 0x002, 1
REG=0x3330, 0x0000 //(4) OUTPUT_FORMAT_TEST
BITFIELD=0x3210, 0x08, 1
[Color Correction Setup]
// All the delay is in ms and the time has not been verified. User can either reduce and omit
// the delay depends on the system implementation.
REG = 0x098C, 0xA115 // Set capture parameter mode
REG = 0x0990, 0x02
REG = 0x098C, 0x272D // Vertical flip enabled
REG = 0x0990, 0x0026
REG = 0x098C, 0xA103 // Refresh
REG = 0x0990, 0x06
DELAY = 10
REG = 0x098C, 0xA103 // Capture mode
REG = 0x0990, 0x02
REG = 0x098C, 0xA103 // Refresh
REG = 0x0990, 0x05
DELAY = 10
REG = 0x098C, 0xAB04 // Turn off histogram stretch
REG = 0x0990, 0x00
REG = 0x098C, 0xA355 // AWB mode: lock the gain to unity
REG = 0x0990, 0x21
DELAY = 10
REG = 0x098C, 0xA102 // Turn off AWB
REG = 0x0990, 0x00
DELAY = 10
BITFIELD = 0x3210, 0x00A0, 0 // Turn off gamma correction and color correction
REG = 0x3028, 0x0008 // ANALOG_GAIN_CODE_GLOBAL
[Fixed 15fps]
REG = 0x098C, 0xA20C //(1) AE_MAX_INDEX
REG = 0x0990, 0x08
REG = 0x098C, 0x271F //(1) MODE_SENSOR_FRAME_LENGTH_A
REG = 0x0990, 0x076C
[Refresh]
REG = 0x98C, 0xA103 //Refresh Sequencer Mode
REG = 0x990, 0x06 // = 6
POLL_FIELD=SEQ_CMD, !=0, DELAY=10, TIMEOUT=50
REG = 0x98C, 0xA103 //Refresh Sequencer
REG = 0x990, 0x05 // = 5
POLL_FIELD=SEQ_CMD, !=0, DELAY=10, TIMEOUT=50
[Auto Exposure]
REG = 0x098C, 0xA207 //(2) AE_GATE
REG = 0x0990, 0x1A
REG = 0x098C, 0xA24C //(1) AE_TARGETBUFFERSPEED
REG = 0x0990, 0x10
REG = 0x098C, 0xA24F //(5) AE_BASETARGET
REG = 0x0990, 0x50
[Gamma Correction]
REG = 0x098C, 0xAB04 //(1) HG_MAX_DLEVEL
REG = 0x0990, 0x80
REG = 0x098C, 0xAB37 //(1) HG_GAMMA_MORPH_CTRL
REG = 0x0990, 0x03
REG = 0x098C, 0x2B38 //(1) HG_GAMMASTARTMORPH
REG = 0x0990, 0x0080
REG = 0x098C, 0x2B3A //(1) HG_GAMMASTOPMORPH
REG = 0x0990, 0x00B0
REG = 0x098C, 0xAB3C //(2) HG_GAMMA_TABLE_A_0
REG = 0x0990, 0x00
REG = 0x098C, 0xAB3D //(2) HG_GAMMA_TABLE_A_1
REG = 0x0990, 0x02
REG = 0x098C, 0xAB3E //(2) HG_GAMMA_TABLE_A_2
REG = 0x0990, 0x08
REG = 0x098C, 0xAB3F //(2) HG_GAMMA_TABLE_A_3
REG = 0x0990, 0x18
REG = 0x098C, 0xAB40 //(2) HG_GAMMA_TABLE_A_4
REG = 0x0990, 0x38
REG = 0x098C, 0xAB41 //(2) HG_GAMMA_TABLE_A_5
REG = 0x0990, 0x55
REG = 0x098C, 0xAB42 //(2) HG_GAMMA_TABLE_A_6
REG = 0x0990, 0x72
REG = 0x098C, 0xAB43 //(2) HG_GAMMA_TABLE_A_7
REG = 0x0990, 0x8E
REG = 0x098C, 0xAB44 //(2) HG_GAMMA_TABLE_A_8
REG = 0x0990, 0xA5
REG = 0x098C, 0xAB45 //(2) HG_GAMMA_TABLE_A_9
REG = 0x0990, 0xB6
REG = 0x098C, 0xAB46 //(2) HG_GAMMA_TABLE_A_10
REG = 0x0990, 0xC5
REG = 0x098C, 0xAB47 //(2) HG_GAMMA_TABLE_A_11
REG = 0x0990, 0xD0
REG = 0x098C, 0xAB48 //(2) HG_GAMMA_TABLE_A_12
REG = 0x0990, 0xDA
REG = 0x098C, 0xAB49 //(2) HG_GAMMA_TABLE_A_13
REG = 0x0990, 0xE2
REG = 0x098C, 0xAB4A //(2) HG_GAMMA_TABLE_A_14
REG = 0x0990, 0xE9
REG = 0x098C, 0xAB4B //(2) HG_GAMMA_TABLE_A_15
REG = 0x0990, 0xF0
REG = 0x098C, 0xAB4C //(2) HG_GAMMA_TABLE_A_16
REG = 0x0990, 0xF5
REG = 0x098C, 0xAB4D //(2) HG_GAMMA_TABLE_A_17
REG = 0x0990, 0xFA
REG = 0x098C, 0xAB4E //(2) HG_GAMMA_TABLE_A_18
REG = 0x0990, 0xFF
REG = 0x098C, 0xAB4F //(2) HG_GAMMA_TABLE_B_0
REG = 0x0990, 0x00
REG = 0x098C, 0xAB50 //(2) HG_GAMMA_TABLE_B_1
REG = 0x0990, 0x01
REG = 0x098C, 0xAB51 //(2) HG_GAMMA_TABLE_B_2
REG = 0x0990, 0x02
REG = 0x098C, 0xAB52 //(2) HG_GAMMA_TABLE_B_3
REG = 0x0990, 0x05
REG = 0x098C, 0xAB53 //(2) HG_GAMMA_TABLE_B_4
REG = 0x0990, 0x11
REG = 0x098C, 0xAB54 //(2) HG_GAMMA_TABLE_B_5
REG = 0x0990, 0x1E
REG = 0x098C, 0xAB55 //(2) HG_GAMMA_TABLE_B_6
REG = 0x0990, 0x2D
REG = 0x098C, 0xAB56 //(2) HG_GAMMA_TABLE_B_7
REG = 0x0990, 0x3F
REG = 0x098C, 0xAB57 //(2) HG_GAMMA_TABLE_B_8
REG = 0x0990, 0x53
REG = 0x098C, 0xAB58 //(2) HG_GAMMA_TABLE_B_9
REG = 0x0990, 0x6B
REG = 0x098C, 0xAB59 //(2) HG_GAMMA_TABLE_B_10
REG = 0x0990, 0x87
REG = 0x098C, 0xAB5A //(2) HG_GAMMA_TABLE_B_11
REG = 0x0990, 0xA0
REG = 0x098C, 0xAB5B //(2) HG_GAMMA_TABLE_B_12
REG = 0x0990, 0xB5
REG = 0x098C, 0xAB5C //(2) HG_GAMMA_TABLE_B_13
REG = 0x0990, 0xC7
REG = 0x098C, 0xAB5D //(2) HG_GAMMA_TABLE_B_14
REG = 0x0990, 0xD6
REG = 0x098C, 0xAB5E //(2) HG_GAMMA_TABLE_B_15
REG = 0x0990, 0xE2
REG = 0x098C, 0xAB5F //(2) HG_GAMMA_TABLE_B_16
REG = 0x0990, 0xED
REG = 0x098C, 0xAB60 //(2) HG_GAMMA_TABLE_B_17
REG = 0x0990, 0xF6
REG = 0x098C, 0xAB61 //(2) HG_GAMMA_TABLE_B_18
REG = 0x0990, 0xFF
[Auto White Balance]
REG = 0x098C, 0x2306 //AWB_CCM_L_0
REG = 0x0990, 0x019B
REG = 0x098C, 0x2308 //AWB_CCM_L_1
REG = 0x0990, 0xFF4D
REG = 0x098C, 0x230A //AWB_CCM_L_2
REG = 0x0990, 0x001C
REG = 0x098C, 0x230C //AWB_CCM_L_3
REG = 0x0990, 0xFF00
REG = 0x098C, 0x230E //AWB_CCM_L_4
REG = 0x0990, 0x02FE
REG = 0x098C, 0x2310 //AWB_CCM_L_5
REG = 0x0990, 0xFF14
REG = 0x098C, 0x2312 //AWB_CCM_L_6
REG = 0x0990, 0xFF24
REG = 0x098C, 0x2314 //AWB_CCM_L_7
REG = 0x0990, 0xFD7F
REG = 0x098C, 0x2316 //AWB_CCM_L_8
REG = 0x0990, 0x03E9
REG = 0x098C, 0x2318 //AWB_CCM_L_9
REG = 0x0990, 0x002A
REG = 0x098C, 0x231A //AWB_CCM_L_10
REG = 0x0990, 0x003A
REG = 0x098C, 0x231C //AWB_CCM_RL_0
REG = 0x0990, 0x0020
REG = 0x098C, 0x231E //AWB_CCM_RL_1
REG = 0x0990, 0x0065
REG = 0x098C, 0x2320 //AWB_CCM_RL_2
REG = 0x0990, 0xFFB1
REG = 0x098C, 0x2322 //AWB_CCM_RL_3
REG = 0x0990, 0x0063
REG = 0x098C, 0x2324 //AWB_CCM_RL_4
REG = 0x0990, 0xFE8C
REG = 0x098C, 0x2326 //AWB_CCM_RL_5
REG = 0x0990, 0x006A
REG = 0x098C, 0x2328 //AWB_CCM_RL_6
REG = 0x0990, 0x0077
REG = 0x098C, 0x232A //AWB_CCM_RL_7
REG = 0x0990, 0x0161
REG = 0x098C, 0x232C //AWB_CCM_RL_8
REG = 0x0990, 0xFE76
REG = 0x098C, 0x232E //AWB_CCM_RL_9
REG = 0x0990, 0x0009
REG = 0x098C, 0x2330 //AWB_CCM_RL_10
REG = 0x0990, 0xFFEC
//VAR8=3, 0x4A, 0x70 //(1) AWB_GAIN_MIN
//VAR8=3, 0x4B, 0x90 //(1) AWB_GAIN_MAX
//VAR8=3, 0x4C, 0x70 //(1) AWB_GAINMIN_B
//VAR8=3, 0x4D, 0x90 //(1) AWB_GAINMAX_B
REG = 0x098C, 0xA35D //(1) AWB_STEADY_BGAIN_OUT_MIN
REG = 0x0990, 0x73
REG = 0x098C, 0xA35E //(1) AWB_STEADY_BGAIN_OUT_MAX
REG = 0x0990, 0x8D
[Lens Correction]
REG=0x3658, 0x7D8F //P_RD_P0Q0
REG=0x365A, 0x314D //P_RD_P0Q1
REG=0x365C, 0x7912 //P_RD_P0Q2
REG=0x365E, 0xA10F //P_RD_P0Q3
REG=0x3660, 0x6874 //P_RD_P0Q4
REG=0x3680, 0x1F0B //P_RD_P1Q0
REG=0x3682, 0xD48C //P_RD_P1Q1
REG=0x3684, 0x0E72 //P_RD_P1Q2
REG=0x3686, 0x6B51 //P_RD_P1Q3
REG=0x3688, 0x91F1 //P_RD_P1Q4
REG=0x36A8, 0x1293 //P_RD_P2Q0
REG=0x36AA, 0x04F0 //P_RD_P2Q1
REG=0x36AC, 0x40D6 //P_RD_P2Q2
REG=0x36AE, 0x1931 //P_RD_P2Q3
REG=0x36B0, 0xFCD7 //P_RD_P2Q4
REG=0x36D0, 0x34D1 //P_RD_P3Q0
REG=0x36D2, 0x5C92 //P_RD_P3Q1
REG=0x36D4, 0xEDF5 //P_RD_P3Q2
REG=0x36D6, 0x56B4 //P_RD_P3Q3
REG=0x36D8, 0x47F9 //P_RD_P3Q4
REG=0x36F8, 0x4175 //P_RD_P4Q0
REG=0x36FA, 0xC7F4 //P_RD_P4Q1
REG=0x36FC, 0xE738 //P_RD_P4Q2
REG=0x36FE, 0x8C98 //P_RD_P4Q3
REG=0x3700, 0x4D5C //P_RD_P4Q4
REG=0x364E, 0x7D0F //P_GR_P0Q0
REG=0x3650, 0x31CC //P_GR_P0Q1
REG=0x3652, 0x47D2 //P_GR_P0Q2
REG=0x3654, 0xC58F //P_GR_P0Q3
REG=0x3656, 0x2374 //P_GR_P0Q4
REG=0x3676, 0x232A //P_GR_P1Q0
REG=0x3678, 0x6186 //P_GR_P1Q1
REG=0x367A, 0x1852 //P_GR_P1Q2
REG=0x367C, 0x1F30 //P_GR_P1Q3
REG=0x367E, 0x9D14 //P_GR_P1Q4
REG=0x369E, 0x6A52 //P_GR_P2Q0
REG=0x36A0, 0x3450 //P_GR_P2Q1
REG=0x36A2, 0x3A96 //P_GR_P2Q2
REG=0x36A4, 0x93B4 //P_GR_P2Q3
REG=0x36A6, 0xF5B8 //P_GR_P2Q4
REG=0x36C6, 0x3D11 //P_GR_P3Q0
REG=0x36C8, 0x2832 //P_GR_P3Q1
REG=0x36CA, 0xA816 //P_GR_P3Q2
REG=0x36CC, 0x2BD4 //P_GR_P3Q3
REG=0x36CE, 0x7479 //P_GR_P3Q4
REG=0x36EE, 0x2175 //P_GR_P4Q0
REG=0x36F0, 0xC714 //P_GR_P4Q1
REG=0x36F2, 0xC339 //P_GR_P4Q2
REG=0x36F4, 0x47B6 //P_GR_P4Q3
REG=0x36F6, 0x0BBD //P_GR_P4Q4
REG=0x3662, 0x7CAF //P_BL_P0Q0
REG=0x3664, 0x6BEC //P_BL_P0Q1
REG=0x3666, 0x4CD2 //P_BL_P0Q2
REG=0x3668, 0xE80F //P_BL_P0Q3
REG=0x366A, 0x7B53 //P_BL_P0Q4
REG=0x368A, 0x2B8B //P_BL_P1Q0
REG=0x368C, 0x2C0B //P_BL_P1Q1
REG=0x368E, 0x0EF2 //P_BL_P1Q2
REG=0x3690, 0x77F0 //P_BL_P1Q3
REG=0x3692, 0xA1D4 //P_BL_P1Q4
REG=0x36B2, 0x53B2 //P_BL_P2Q0
REG=0x36B4, 0x5670 //P_BL_P2Q1
REG=0x36B6, 0x1D76 //P_BL_P2Q2
REG=0x36B8, 0xAD10 //P_BL_P2Q3
REG=0x36BA, 0x8179 //P_BL_P2Q4
REG=0x36DA, 0x6611 //P_BL_P3Q0
REG=0x36DC, 0x09D3 //P_BL_P3Q1
REG=0x36DE, 0xB976 //P_BL_P3Q2
REG=0x36E0, 0x7F14 //P_BL_P3Q3
REG=0x36E2, 0x7AD9 //P_BL_P3Q4
REG=0x3702, 0x16D5 //P_BL_P4Q0
REG=0x3704, 0x8CD5 //P_BL_P4Q1
REG=0x3706, 0xD2F9 //P_BL_P4Q2
REG=0x3708, 0x9316 //P_BL_P4Q3
REG=0x370A, 0x1BDD //P_BL_P4Q4
REG=0x366C, 0x7BEF //P_GB_P0Q0
REG=0x366E, 0x300C //P_GB_P0Q1
REG=0x3670, 0x4FF2 //P_GB_P0Q2
REG=0x3672, 0xA2AF //P_GB_P0Q3
REG=0x3674, 0x1EF4 //P_GB_P0Q4
REG=0x3694, 0x570B //P_GB_P1Q0
REG=0x3696, 0xA4A7 //P_GB_P1Q1
REG=0x3698, 0x1392 //P_GB_P1Q2
REG=0x369A, 0x4430 //P_GB_P1Q3
REG=0x369C, 0x82D4 //P_GB_P1Q4
REG=0x36BC, 0x5F12 //P_GB_P2Q0
REG=0x36BE, 0x40D0 //P_GB_P2Q1
REG=0x36C0, 0x2ED6 //P_GB_P2Q2
REG=0x36C2, 0x95B4 //P_GB_P2Q3
REG=0x36C4, 0xEA18 //P_GB_P2Q4
REG=0x36E4, 0x3191 //P_GB_P3Q0
REG=0x36E6, 0x3632 //P_GB_P3Q1
REG=0x36E8, 0xA476 //P_GB_P3Q2
REG=0x36EA, 0xE411 //P_GB_P3Q3
REG=0x36EC, 0x7339 //P_GB_P3Q4
REG=0x370C, 0x2655 //P_GB_P4Q0
REG=0x370E, 0xE994 //P_GB_P4Q1
REG=0x3710, 0xA5D9 //P_GB_P4Q2
REG=0x3712, 0x4777 //P_GB_P4Q3
REG=0x3714, 0x7B9C //P_GB_P4Q4
REG=0x3644, 0x0158 //POLY_ORIGIN_C
REG=0x3642, 0x00E4 //POLY_ORIGIN_R
BITFIELD=0x3210, 0x0008, 1 //PGA_ENABLE
[Image Size : VGA]
REG = 0x098C, 0x2703 //MODE_OUTPUT_WIDTH_A
REG = 0x0990, 0x0280
REG = 0x098C, 0x2705 //MODE_OUTPUT_HEIGHT_A
REG = 0x0990, 0x01E0
LOAD=Refresh
[Image Size : QVGA]
REG = 0x098C, 0x2703 //MODE_OUTPUT_WIDTH_A
REG = 0x0990, 0x0140
REG = 0x098C, 0x2705 //MODE_OUTPUT_HEIGHT_A
REG = 0x0990, 0x00F0
LOAD=Refresh
[Image Size : CIF]
REG = 0x098C, 0x2703 //MODE_OUTPUT_WIDTH_A
REG = 0x0990, 0x0160
REG = 0x098C, 0x2705 //MODE_OUTPUT_HEIGHT_A
REG = 0x0990, 0x0120
LOAD=Refresh
[Image Size : QCIF]
REG = 0x098C, 0x2703 //MODE_OUTPUT_WIDTH_A
REG = 0x0990, 0x00B0
REG = 0x098C, 0x2705 //MODE_OUTPUT_HEIGHT_A
REG = 0x0990, 0x0090
LOAD=Refresh
[Effect : Off]
REG = 0x098C, 0x2759 //MODE_SPEC_EFFECTS_A
REG = 0x0990, 0x6440
REG = 0x098C, 0x275B //MODE_SPEC_EFFECTS_B
REG = 0x0990, 0x6440
LOAD=Refresh
[Effect : Mono]
REG = 0x098C, 0x2759 //MODE_SPEC_EFFECTS_A
REG = 0x0990, 0x6441
REG = 0x098C, 0x275B //MODE_SPEC_EFFECTS_B
REG = 0x0990, 0x6441
LOAD=Refresh
[Effect : Sepia]
REG=0x326C, 0x0100 //APERTURE_PARAMETERS
REG = 0x098C, 0xAB3C //HG_GAMMA_TABLE_A_0
REG = 0x0990, 0x00
REG = 0x098C, 0xAB3D //HG_GAMMA_TABLE_A_1
REG = 0x0990, 0x05
REG = 0x098C, 0xAB3E //HG_GAMMA_TABLE_A_2
REG = 0x0990, 0x11
REG = 0x098C, 0xAB3F //HG_GAMMA_TABLE_A_3
REG = 0x0990, 0x33
REG = 0x098C, 0xAB40 //HG_GAMMA_TABLE_A_4
REG = 0x0990, 0x5D
REG = 0x098C, 0xAB41 //HG_GAMMA_TABLE_A_5
REG = 0x0990, 0x78
REG = 0x098C, 0xAB42 //HG_GAMMA_TABLE_A_6
REG = 0x0990, 0x8D
REG = 0x098C, 0xAB43 //HG_GAMMA_TABLE_A_7
REG = 0x0990, 0x9E
REG = 0x098C, 0xAB44 //HG_GAMMA_TABLE_A_8
REG = 0x0990, 0xAD
REG = 0x098C, 0xAB45 //HG_GAMMA_TABLE_A_9
REG = 0x0990, 0xB9
REG = 0x098C, 0xAB46 //HG_GAMMA_TABLE_A_10
REG = 0x0990, 0xC4
REG = 0x098C, 0xAB47 //HG_GAMMA_TABLE_A_11
REG = 0x0990, 0xCE
REG = 0x098C, 0xAB48 //HG_GAMMA_TABLE_A_12
REG = 0x0990, 0xD6
REG = 0x098C, 0xAB49 //HG_GAMMA_TABLE_A_13
REG = 0x0990, 0xDF
REG = 0x098C, 0xAB4A //HG_GAMMA_TABLE_A_14
REG = 0x0990, 0xE6
REG = 0x098C, 0xAB4B //HG_GAMMA_TABLE_A_15
REG = 0x0990, 0xED
REG = 0x098C, 0xAB4C //HG_GAMMA_TABLE_A_16
REG = 0x0990, 0xF3
REG = 0x098C, 0xAB4D //HG_GAMMA_TABLE_A_17
REG = 0x0990, 0xF9
REG = 0x098C, 0xAB4E //HG_GAMMA_TABLE_A_18
REG = 0x0990, 0xFF
REG = 0x098C, 0x2759 //MODE_SPEC_EFFECTS_A
REG = 0x0990, 0x6442
REG = 0x098C, 0x275B //MODE_SPEC_EFFECTS_B
REG = 0x0990, 0x6442
REG = 0x098C, 0x2763 //MODE_COMMONMODESETTINGS_FX_SEPIA_SETTINGS
REG = 0x0990, 0xB01C
LOAD=Refresh
[Manual WB -> Auto WB]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0F
[Manual White Balance : P1]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x00
[Manual White Balance : P2]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x0B
[Manual White Balance : P3]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x16
[Manual White Balance : P4]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x21
[Manual White Balance : P5]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x2C
[Manual White Balance : P6]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x37
[Manual White Balance : P7]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x42
[Manual White Balance : P8]
REG = 0x098C, 0xA102 //SEQ_MODE
REG = 0x0990, 0x0B
REG = 0x098C, 0xA353 //AWB_CCM_POSITION
REG = 0x0990, 0x4D
[Sharpness : 0]
REG=0x326C, 0x1600 //APERTURE_PARAMETERS
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