diff --git a/build/libraries/camera/ARM7/MT9V113-MTM10-3.ini b/build/libraries/camera/ARM7/MT9V113-MTM10-3.ini
index 8d8b85a..472f7af 100644
--- a/build/libraries/camera/ARM7/MT9V113-MTM10-3.ini
+++ b/build/libraries/camera/ARM7/MT9V113-MTM10-3.ini
@@ -180,7 +180,7 @@ BITFIELD= 0X14, 2, 0         // Power-down PLL
 REG = 0x0010, 0x0021        //PLL Dividers = 0x21
 REG = 0x0012, 0x0000        //PLL P Dividers = 0x0
 REG = 0x0014, 0x244B        //PLL control: TEST_BYPASS on = 0x244B
-DELAY = 1               // Allow PLL to lock
+DELAY = 5               // Allow PLL to lock
 REG = 0x0014, 0x304B        //PLL control: PLL_ENABLE on = 0x304B
 POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20   // Verify PLL lock
 BITFIELD= 0x14, 1, 0         //PLL_BYPASS_OFF
@@ -358,7 +358,7 @@ BITFIELD= 0X14, 2, 0         // Power-down PLL
 REG = 0x0010, 0x0335        //PLL Dividers = 0x335
 REG = 0x0012, 0x0000        //PLL P Dividers = 0x0
 REG = 0x0014, 0x244B        //PLL control: TEST_BYPASS on = 0x244B
-DELAY = 1               // Allow PLL to lock
+DELAY = 5               // Allow PLL to lock
 REG = 0x0014, 0x304B        //PLL control: PLL_ENABLE on = 0x304B
 POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20   // Verify PLL lock
 BITFIELD= 0x14, 1, 0         //PLL_BYPASS_OFF
@@ -643,7 +643,7 @@ BITFIELD= 0X14, 2, 0         // Power-down PLL
 REG = 0x0010, 0x0010        //PLL Dividers = 0x10
 REG = 0x0012, 0x0000        //PLL P Dividers = 0x0
 REG = 0x0014, 0x244B        //PLL control: TEST_BYPASS on = 0x244B
-DELAY = 1               // Allow PLL to lock
+DELAY = 5               // Allow PLL to lock
 REG = 0x0014, 0x304B        //PLL control: PLL_ENABLE on = 0x304B
 POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20   // Verify PLL lock
 BITFIELD= 0x14, 1, 0         //PLL_BYPASS_OFF
@@ -820,7 +820,7 @@ BITFIELD= 0X14, 2, 0         // Power-down PLL
 REG = 0x0010, 0x0110        //PLL Dividers = 0x110
 REG = 0x0012, 0x0000        //PLL P Dividers = 0x0
 REG = 0x0014, 0x244B        //PLL control: TEST_BYPASS on = 0x244B
-DELAY = 1               // Allow PLL to lock
+DELAY = 5               // Allow PLL to lock
 REG = 0x0014, 0x304B        //PLL control: PLL_ENABLE on = 0x304B
 POLL_REG=0x0014, 0x8000, ==0, DELAY=50, TIMEOUT=20   // Verify PLL lock
 BITFIELD= 0x14, 1, 0         //PLL_BYPASS_OFF