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割り込み禁止を短く押さえた副作用?でコマンドが立て続けに来たときに発行された際に後ろのコマンドが実行されないことがあった。
(TWLアプリがリセットを掛けたときの一連) これを修正 git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@71 013db118-44a6-b54f-8bf7-843cb86687b1
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@ -19,7 +19,7 @@
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#include "..\user_define.h"
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// #define _renge_test_
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#define _renge_test_
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//******************************************************************************
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bit renge_flg_interval;
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@ -140,7 +140,7 @@ err renge_task_immed_add( task_status* new_task ){
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if( tasks_immed[ i ] == new_task )
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{
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// 重複登録はしない
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// NOP();
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NOP();
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return( ERR_ERR );
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}
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}
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@ -7,7 +7,8 @@
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#define TASK_IMMED_RUN_LIST_MAX 8
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extern task_status_immed do_command( );
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extern task_status_immed do_command0( );
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extern task_status_immed do_command2( );
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extern task_status_immed ntr_pmic_comm();
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extern task_status_immed acc_read();
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extern task_status_immed acc_write();
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@ -118,42 +118,50 @@ void tsk_misc_stat( )
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COMMANDレジスタへの書き込み
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0なら呼ばれません。ケア不要
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======================================================== */
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task_status_immed do_command( )
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task_status_immed do_command0( )
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{
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// command0 本体電源など
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if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ )
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if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BIT_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) != 0x00 )
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{
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system_status.pwr_state = OFF_TRIG;
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}
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else
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{
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if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ )
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if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ )
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{
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PM_reset_ast( );
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RESET2_ast;
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FCRAM_RST_ast;
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wait_ms( 5 );
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system_status.pwr_state = OFF_TRIG;
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}
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else
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{
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if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ )
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{
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PM_reset_ast( );
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RESET2_ast;
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FCRAM_RST_ast;
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}
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if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_REQ )
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{
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FCRAM_RST_ast;
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wait_ms( 5 );
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}
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else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_REQ )
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{
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RESET2_ast;
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wait_ms( 5 );
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}
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wait_ms( 5 );
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FCRAM_RST_neg;
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RESET2_neg;
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PM_reset_neg( );
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}
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PM_reset_neg( );
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RESET2_neg;
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FCRAM_RST_neg;
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}
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// command2 ‰t<E280B0>»Œn
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vreg_ctr[VREG_C_COMMAND0] = 0;
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return ( ERR_FINISED );
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}
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/* ========================================================
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command2 液晶系
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0なら呼ばれません。ケア不要
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======================================================== */
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task_status_immed do_command2( )
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{
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// こちらからの完了割り込みを待ってくれることを前提にしています。
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if(( vreg_ctr[VREG_C_COMMAND2] & REG_BIT_CMD_LCD_ON ) != 0 )
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{
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@ -170,7 +178,6 @@ task_status_immed do_command( )
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PM_BL_set( vreg_ctr[VREG_C_COMMAND2] & REG_BITS_CMD_BL );
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}
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vreg_ctr[VREG_C_COMMAND0] = 0;
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vreg_ctr[VREG_C_COMMAND2] = 0;
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return ( ERR_FINISED );
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}
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@ -86,6 +86,8 @@ void tsk_sys( )
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system_status.pwr_state = OFF_TRIG;
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return;
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}
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// IRQ0_active;
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#else
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vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR;
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system_status.poweron_reason = PWSW;
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@ -200,14 +202,15 @@ void tsk_sys( )
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#ifdef _PMIC_TWL_
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PM_TEG_LCD_dis( 1 );
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#endif
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PM_sys_pow_off( );
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// IRQ0_deactive;
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// pullup_off(); ↓
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{
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PU5 = 0b00000011; // PM_CHG,PM_CHGERR
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PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC
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}
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PM_sys_pow_off( );
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KRM = ( KR_SW_POW ); // Mask ではなく、Modeなのだそうだ。紛らわしい
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// intp20系は後ほど
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MK0 = ~( INT_MSK0_EXTDC );
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@ -309,7 +312,7 @@ static void chk_emergencyExit(){
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iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, 0 );
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vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & 0b10011111 );
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vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ;
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renge_task_immed_add( do_command );
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renge_task_immed_add( do_command0 );
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}
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}
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#endif
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@ -101,29 +101,35 @@ void vreg_ctr_write( u8 adrs, u8 data )
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break;
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case ( VREG_C_COMMAND0 ):
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case ( VREG_C_COMMAND2 ):
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vreg_ctr[adrs] = data;
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vreg_ctr[adrs] |= data;
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if( data != 0 )
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{
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renge_task_immed_add( do_command );
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renge_task_immed_add( do_command0 );
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}
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break;
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case ( VREG_C_COMMAND2 ):
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vreg_ctr[adrs] |= data;
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if( data != 0 )
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{
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renge_task_immed_add( do_command2 );
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}
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break;
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case ( VREG_C_COMMAND1 ):
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vreg_ctr[adrs] = data;
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if( data != 0 )
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{
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// TWLに割り込みを入れる
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/// 実際に割り込みを入れるのはSoC
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vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; //pwsw_det
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; //reset_req
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vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT_SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; //pwsw_det
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; //reset_req
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //off_req
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //off_req
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; //batt_low
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; //batt_empty
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; //batt_low
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; //batt_empty
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00; //vol_changed
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vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00; //vol_changed
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}
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break;
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