割り込み禁止を短く押さえた副作用?でコマンドが立て続けに来たときに発行された際に後ろのコマンドが実行されないことがあった。

(TWLアプリがリセットを掛けたときの一連)
これを修正

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@71 013db118-44a6-b54f-8bf7-843cb86687b1
This commit is contained in:
fujita_ryohei 2009-12-25 07:12:26 +00:00
parent a8f5504152
commit a5671d2f4e
5 changed files with 52 additions and 35 deletions

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@ -19,7 +19,7 @@
#include "..\user_define.h"
// #define _renge_test_
#define _renge_test_
//******************************************************************************
bit renge_flg_interval;
@ -140,7 +140,7 @@ err renge_task_immed_add( task_status* new_task ){
if( tasks_immed[ i ] == new_task )
{
// 重複登録はしない
// NOP();
NOP();
return( ERR_ERR );
}
}

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@ -7,7 +7,8 @@
#define TASK_IMMED_RUN_LIST_MAX 8
extern task_status_immed do_command( );
extern task_status_immed do_command0( );
extern task_status_immed do_command2( );
extern task_status_immed ntr_pmic_comm();
extern task_status_immed acc_read();
extern task_status_immed acc_write();

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@ -118,42 +118,50 @@ void tsk_misc_stat( )
COMMANDレジスタへの書き込み
  0
======================================================== */
task_status_immed do_command( )
task_status_immed do_command0( )
{
// command0 本体電源など
if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ )
if( ( vreg_ctr[VREG_C_COMMAND0] & ( REG_BIT_OFF_REQ | REG_BIT_RESET1_REQ | REG_BIT_FCRAM_RESET_REQ | REG_BIT_RESET2_REQ )) != 0x00 )
{
system_status.pwr_state = OFF_TRIG;
}
else
{
if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ )
if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_OFF_REQ )
{
PM_reset_ast( );
RESET2_ast;
FCRAM_RST_ast;
wait_ms( 5 );
system_status.pwr_state = OFF_TRIG;
}
else
{
if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET1_REQ )
{
PM_reset_ast( );
RESET2_ast;
FCRAM_RST_ast;
}
if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_FCRAM_RESET_REQ )
{
FCRAM_RST_ast;
wait_ms( 5 );
}
else if( vreg_ctr[VREG_C_COMMAND0] & REG_BIT_RESET2_REQ )
{
RESET2_ast;
wait_ms( 5 );
}
wait_ms( 5 );
FCRAM_RST_neg;
RESET2_neg;
PM_reset_neg( );
}
PM_reset_neg( );
RESET2_neg;
FCRAM_RST_neg;
}
// command2 ‰t<E280B0>»Œn
vreg_ctr[VREG_C_COMMAND0] = 0;
return ( ERR_FINISED );
}
/* ========================================================
command2
  0
======================================================== */
task_status_immed do_command2( )
{
// こちらからの完了割り込みを待ってくれることを前提にしています。
if(( vreg_ctr[VREG_C_COMMAND2] & REG_BIT_CMD_LCD_ON ) != 0 )
{
@ -170,7 +178,6 @@ task_status_immed do_command( )
PM_BL_set( vreg_ctr[VREG_C_COMMAND2] & REG_BITS_CMD_BL );
}
vreg_ctr[VREG_C_COMMAND0] = 0;
vreg_ctr[VREG_C_COMMAND2] = 0;
return ( ERR_FINISED );
}

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@ -86,6 +86,8 @@ void tsk_sys( )
system_status.pwr_state = OFF_TRIG;
return;
}
// IRQ0_active;
#else
vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR;
system_status.poweron_reason = PWSW;
@ -200,14 +202,15 @@ void tsk_sys( )
#ifdef _PMIC_TWL_
PM_TEG_LCD_dis( 1 );
#endif
PM_sys_pow_off( );
// IRQ0_deactive;
// pullup_off(); ↓
{
PU5 = 0b00000011; // PM_CHG,PM_CHGERR
PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC
}
PM_sys_pow_off( );
KRM = ( KR_SW_POW ); // Mask ではなく、Modeなのだそうだ。紛らわしい
// intp20系は後ほど
MK0 = ~( INT_MSK0_EXTDC );
@ -309,7 +312,7 @@ static void chk_emergencyExit(){
iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL, 0 );
vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS] & 0b10011111 );
vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ;
renge_task_immed_add( do_command );
renge_task_immed_add( do_command0 );
}
}
#endif

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@ -101,29 +101,35 @@ void vreg_ctr_write( u8 adrs, u8 data )
break;
case ( VREG_C_COMMAND0 ):
case ( VREG_C_COMMAND2 ):
vreg_ctr[adrs] = data;
vreg_ctr[adrs] |= data;
if( data != 0 )
{
renge_task_immed_add( do_command );
renge_task_immed_add( do_command0 );
}
break;
case ( VREG_C_COMMAND2 ):
vreg_ctr[adrs] |= data;
if( data != 0 )
{
renge_task_immed_add( do_command2 );
}
break;
case ( VREG_C_COMMAND1 ):
vreg_ctr[adrs] = data;
if( data != 0 )
{
// TWLに割り込みを入れる
/// 実際に割り込みを入れるのはSoC
vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; //pwsw_det
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; //reset_req
vreg_twl[REG_TWL_INT_ADRS_IRQ] = ( ( data & REG_BIT_SEND_TWL_PWSW_DET ) != 0 ) ? REG_BIT_TWL_IRQ_PWSW_DET : 0x00; //pwsw_det
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_RESET_DET ) != 0 ) ? REG_BIT_TWL_IRQ_RESET : 0x00; //reset_req
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //off_req
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_OFF_DET ) != 0 ) ? REG_BIT_TWL_IRQ_OFF : 0x00; //off_req
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; //batt_low
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; //batt_empty
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_LOW ) != 0 ) ? REG_BIT_TWL_IRQ_BT_LOW : 0x00; //batt_low
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_BATT_EMPTY ) != 0 ) ? REG_BIT_TWL_IRQ_BT_EMPTY : 0x00; //batt_empty
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( vreg_ctr[VREG_C_COMMAND1] & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00; //vol_changed
vreg_twl[REG_TWL_INT_ADRS_IRQ] |= ( ( data & REG_BIT_SEND_TWL_VOL_CLICK ) != 0 ) ? REG_BIT_TWL_IRQ_VOL_CHANGE : 0x00; //vol_changed
}
break;