update ex-dma test. fix MIi_StopExDma.

git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@42 4ee2a332-4b2b-5046-8439-1ba90f034370

build/libraries/mi/common/mi_exDma.c

@@ -14,13 +14,13 @@
   $NoKeywords: $
  *---------------------------------------------------------------------------*/
 
-#include <twl.h>
+#include <twl/mi.h>
 
 static BOOL isArbitrated = FALSE;
 
 static u32 intervalTable[] =
 {
-    8, 8, 8, 8,
+    1, 1, 1, 1,
 };
 
 //================================================================================
@@ -632,6 +632,22 @@ void MIi_WaitExDma( u32 dmaNo )
   Returns:      None
  *---------------------------------------------------------------------------*/
 void MIi_StopExDma( u32 dmaNo )
+{
+    MIi_StopExDmaAsync( dmaNo );
+    MIi_WaitExDma( dmaNo );
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         MIi_StopDmaAsync
+
+  Description:  stop extended DMA
+                async version
+
+  Arguments:    dmaNo : DMA channel No.
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void MIi_StopExDmaAsync( u32 dmaNo )
 {
     OSIntrMode enabled = OS_DisableInterrupts();
 

build/libraries/mi/common/mi_init.c

@@ -23,7 +23,7 @@
   $NoKeywords: $
  *---------------------------------------------------------------------------*/
 
-#include <twl.h>
+#include <twl/mi.h>
 
 /*---------------------------------------------------------------------------*
   Name:         MI_Init
@@ -47,6 +47,5 @@ void MI_Init(void)
     //---- add for TWL
 
     //---- DMA arbitration
-    //     this value depends on that the cache line read from the main memory is 20 cycles.
+    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_ROUND_ROBIN, MI_EXDMAGBL_YLD_CYCLE_DEFAULT );
-    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_ROUND_ROBIN, MI_EXDMAGBL_YLD_CYCLE_32 );
 }

build/tests/mi/Makefile

@@ -20,7 +20,9 @@ include	$(TWLSDK_ROOT)/build/buildtools/commondefs
 
 #----------------------------------------------------------------------------
 
-SUBDIRS =	exDma-1
+SUBDIRS =	\
+			exDma-1 \
+			_ARM7_exDma-1 \
 
 
 #----------------------------------------------------------------------------

build/tests/mi/_ARM7_exDma-1/Makefile

@@ -0,0 +1,44 @@
+#! make -f
+#----------------------------------------------------------------------------
+# Project:  TwlSDK - OS - demos - _ARM7-exDma-1
+# File:     Makefile
+#
+# Copyright 2007 Nintendo.  All rights reserved.
+#
+# These coded instructions, statements, and computer programs contain
+# proprietary information of Nintendo of America Inc. and/or Nintendo
+# Company Ltd., and are protected by Federal copyright law.  They may
+# not be disclosed to third parties or copied or duplicated in any form,
+# in whole or in part, without the prior written consent of Nintendo.
+#
+# $Log: $
+# $NoKeywords: $
+#----------------------------------------------------------------------------
+
+SUBDIRS		=
+
+
+#----------------------------------------------------------------------------
+
+#TWL_CODEGEN   =       THUMB
+TWL_PROC      =       ARM7
+
+TARGET_BIN	=	main.axf
+
+SRCS		=	main.c
+
+#SRCDIR		=	# using default
+#LCFILE		=	# using default
+
+include	$(TWLSDK_ROOT)/build/buildtools/commondefs
+
+
+#----------------------------------------------------------------------------
+
+do-build:		$(TARGETS)
+
+
+include	$(TWLSDK_ROOT)/build/buildtools/modulerules
+
+
+#===== End of Makefile =====

build/tests/mi/_ARM7_exDma-1/src/main.c

@@ -0,0 +1,484 @@
+/*---------------------------------------------------------------------------*
+  Project:  TwlSDK - MI - demos - exDma-1
+  File:     main.c
+
+  Copyright 2003-2006 Nintendo.  All rights reserved.
+
+  These coded instructions, statements, and computer programs contain
+  proprietary information of Nintendo of America Inc. and/or Nintendo
+  Company Ltd., and are protected by Federal copyright law.  They may
+  not be disclosed to third parties or copied or duplicated in any form,
+  in whole or in part, without the prior written consent of Nintendo.
+
+  $Log: $
+  $NoKeywords: $
+ *---------------------------------------------------------------------------*/
+#include <twl.h>
+
+
+#define ONE_BUF_SIZE  0x2004
+
+typedef struct
+{
+    u32 prePad __attribute__ ((aligned (32)));
+    u16 src[4][ONE_BUF_SIZE/2]  __attribute__ ((aligned (32)));
+    u16 dest[4][ONE_BUF_SIZE/2] __attribute__ ((aligned (32)));
+    u32 PostPad __attribute__ ((aligned (32)));
+}
+t_TestBuf;
+
+typedef struct
+{
+    u16 (*src)[ONE_BUF_SIZE/2];
+    u16 (*dest)[ONE_BUF_SIZE/2];
+    char *copyStr;
+    char *fillStr;
+}
+t_CommonArg;
+
+
+t_TestBuf testBuf __attribute__ ((aligned (32)));
+
+t_CommonArg copyfillArg[] =
+{
+    { testBuf.src,                   testBuf.dest,                   "DmaCopy success.\n", "DmaFill success on WRAM.\n", },
+};
+
+t_CommonArg stopArg[] =
+{
+    { testBuf.src,                   testBuf.dest,                   "Stopping DmaCopy success.\n", "Stopping DmaFill success on WRAM.\n", },
+};
+
+t_CommonArg copyfillAsyncArg[] =
+{
+    { testBuf.src,                   testBuf.dest,                   "DmaCopyAsync success.\n", "DmaFillAsync success on WRAM.\n", },
+};
+
+u32 exDmaIntrCount[MI_EXDMA_CH_NUM];
+
+void InitExDmaIntr(void);
+void ClearIntrCount(void);
+void PrintIntrCount(void);
+void ExDma4Intr(void);
+void ExDma5Intr(void);
+void ExDma6Intr(void);
+void ExDma7Intr(void);
+
+static BOOL CheckDmaCopy( u32 dmaNo, void *src, void *dest, const char *str )
+{
+    BOOL ercd = TRUE;
+    u8 *s = src;
+    u8 *d = dest;
+    int i;
+
+    for (i=0; i<ONE_BUF_SIZE; i++)
+    {
+        if ( s[i] != d[i] )
+        {
+            OS_TPrintf( "error: DmaCopy failed address = 0x%x count = 0x%x dmaNo = %d.\n", &d[i], i/2, dmaNo );
+            OS_TPrintf( "       src = 0x%02x dest = 0x%02x.\n", s[i], d[i] );
+            ercd = FALSE;
+            break;
+        }
+    }
+    if (str)
+    {
+        OS_TPrintf( str );
+    }
+
+    return ercd;
+}
+
+static BOOL CheckDmaFill( u32 dmaNo, void *dest, u32 data, char *str )
+{
+    BOOL ercd = TRUE;
+    u32 *d = dest;
+    int i;
+
+    for (i=0; i<ONE_BUF_SIZE/4; i++)
+    {
+        if ( data != d[i] )
+        {
+            OS_TPrintf( "error: DmaFill failed address = 0x%x count = 0x%x dmaNo = %d.\n", &d[i], i/2, dmaNo );
+            OS_TPrintf( "       data = 0x%08x dest = 0x%08x.\n", data, d[i] );
+            ercd = FALSE;
+            break;
+        }
+    }
+    if (str)
+    {
+        OS_TPrintf( str );
+    }
+
+    return ercd;
+}
+
+
+static BOOL CheckDmaCopyAndFill( t_CommonArg *arg, u32 data )
+{
+    u16 (*src)[ONE_BUF_SIZE/2] = arg->src;
+    u16 (*dest)[ONE_BUF_SIZE/2] = arg->dest;
+    char *copyStr = arg->copyStr;
+    char *fillStr = arg->fillStr;
+    BOOL c_ercd = TRUE, f_ercd = TRUE;
+    u32 i, ii;
+
+    for (i=0; i<4; i++)
+    {
+        for (ii=0; ii<ONE_BUF_SIZE/2; ii++)
+        {
+            src[i][ii] = (u16)(ii+i-data);
+        }
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *s = src[i];
+        u16 *d = dest[i];
+        char *str = NULL;
+
+        MIi_ExDmaCopy( ch, s, d, ONE_BUF_SIZE );
+        if ( i == 3 )
+        {
+            str = copyStr;
+        }
+        c_ercd |= CheckDmaCopy( ch, s, d, str );
+    }
+
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *d = dest[i];
+        char *str = NULL;
+
+        MIi_ExDmaFill( ch, d, data+i, ONE_BUF_SIZE );
+        if ( i == 3 )
+        {
+            str = fillStr;
+        }
+        f_ercd |= CheckDmaFill( ch, d, data+i, str );
+    }
+
+    return c_ercd | f_ercd;
+}
+
+static BOOL CheckDmaCopyAndFillAsync( t_CommonArg *arg, u32 data )
+{
+    u16 (*src)[ONE_BUF_SIZE/2] = arg->src;
+    u16 (*dest)[ONE_BUF_SIZE/2] = arg->dest;
+    char *copyStr = arg->copyStr;
+    char *fillStr = arg->fillStr;
+    BOOL c_ercd = TRUE, f_ercd = TRUE;
+    u32 i, ii;
+
+    for (i=0; i<4; i++)
+    {
+        for (ii=0; ii<ONE_BUF_SIZE/2; ii++)
+        {
+            src[i][ii] = (u16)(ii+i-data);
+        }
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *s = src[i];
+        u16 *d = dest[i];
+
+        MIi_ExDmaCopyAsync( ch, s, d, ONE_BUF_SIZE );
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        if ( MIi_IsExDmaBusy( ch ) == FALSE )
+        {
+            OS_TPrintf( "warning: DmaCopyAsync isn't busy dmaNo = %d.\n", ch );
+        }
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        MIi_WaitExDma( ch );
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *s = src[i];
+        u16 *d = dest[i];
+        char *str = NULL;
+
+        if ( i == 3 )
+        {
+            str = copyStr;
+        }
+        c_ercd |= CheckDmaCopy( ch, s, d, str );
+    }
+
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *d = dest[i];
+
+        MIi_ExDmaFillAsync( ch, d, data+i, ONE_BUF_SIZE );
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        if ( MIi_IsExDmaBusy( ch ) == FALSE )
+        {
+            OS_TPrintf( "warning: DmaFillAsync isn't busy dmaNo = %d.\n", ch );
+        }
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        MIi_WaitExDma( ch );
+    }
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *d = dest[i];
+        char *str = NULL;
+
+        if ( i == 3 )
+        {
+            str = fillStr;
+        }
+        f_ercd |= CheckDmaFill( ch, d, data+i, str );
+    }
+
+    return c_ercd | f_ercd;
+}
+
+static BOOL CheckDmaStop( t_CommonArg *arg )
+{
+    u16 (*src)[ONE_BUF_SIZE/2] = arg->src;
+    u16 (*dest)[ONE_BUF_SIZE/2] = arg->dest;
+    char *copyStr = arg->copyStr;
+    char *fillStr = arg->fillStr;
+    BOOL c_ercd = TRUE, f_ercd = TRUE;
+    u32 i;
+
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *s = src[i];
+        u16 *d = dest[i];
+
+        MIi_ExDmaCopyAsync( ch, s, d, ONE_BUF_SIZE );
+        if ( MIi_IsExDmaBusy( ch ) == FALSE )
+        {
+            OS_TPrintf( "warning: DmaCopyAsync isn't busy dmaNo = %d.\n", ch );
+        }
+        MIi_StopExDma( ch );
+
+        if ( MIi_IsExDmaBusy( ch ) == TRUE )
+        {
+            OS_TPrintf( "error: Stopping DmaCopy failed dmaNo = %d.\n", ch );
+            c_ercd = FALSE;
+//            break;
+        }
+    }
+    if ( c_ercd == TRUE )
+    {
+        OS_TPrintf( copyStr );
+    }
+
+    for (i=0; i<4; i++)
+    {
+        u32 ch = i + MI_EXDMA_CH_MIN;
+        u16 *d = dest[i];
+
+        MIi_ExDmaFillAsync( ch, d, i, ONE_BUF_SIZE );
+        if ( MIi_IsExDmaBusy( ch ) == FALSE )
+        {
+            OS_TPrintf( "warning: DmaFillAsync isn't busy dmaNo = %d.\n", ch );
+        }
+        MIi_StopExDma( ch );
+
+        if ( MIi_IsExDmaBusy( ch ) == TRUE )
+        {
+            OS_TPrintf( "error: Stopping DmaFill failed dmaNo = %d.\n", ch );
+            f_ercd = FALSE;
+//            break;
+        }
+    }
+    if ( f_ercd == TRUE )
+    {
+        OS_TPrintf( fillStr );
+    }
+
+    return c_ercd | f_ercd;
+}
+
+static void TestDmaFuncs( void )
+{
+    u32 i;
+
+    ClearIntrCount();
+
+    // sync copy and fill test
+    OS_TPrintf( "\nChecking DmaCopy and DmaFill ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaCopyAndFill( &copyfillArg[i], i );
+    }
+
+    // async copy and fill test
+    OS_TPrintf( "\nChecking DmaCopyAsync and DmaFillAsync ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaCopyAndFillAsync( &copyfillAsyncArg[i], i );
+    }
+
+    // stop test
+    OS_TPrintf( "\nChecking DmaStop ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaStop( &stopArg[i] );
+    }
+
+    PrintIntrCount();
+}
+
+//================================================================================
+/*---------------------------------------------------------------------------*
+  Name:         TwlMain
+
+  Description:  main
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void TwlMain()
+{
+    OS_Init();
+
+    InitExDmaIntr();
+
+    OS_TPrintf("\nARM7 starts.\n");
+
+    // priority dma test
+    OS_TPrintf( "\nTurn into Priority Mode.\n" );
+
+    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_PRIORITY, MI_EXDMAGBL_YLD_CYCLE_DEFAULT );
+
+    TestDmaFuncs();
+
+    // round robin dma test
+    OS_TPrintf( "\nTurn into Round Robin Mode.\n" );
+
+    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_ROUND_ROBIN, MI_EXDMAGBL_YLD_CYCLE_DEFAULT );
+
+    TestDmaFuncs();
+
+    OS_TPrintf("\nARM7 ends.\n");
+    OS_Terminate();
+}
+
+
+/*---------------------------------------------------------------------------*
+  Name:         InitExDmaIntr
+
+  Description:  initialize extended dma interrupt handler
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void InitExDmaIntr(void)
+{
+    (void)OS_SetIrqFunction( OS_IE_DMA4, ExDma4Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA5, ExDma5Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA6, ExDma6Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA7, ExDma7Intr );
+    (void)OS_EnableIrqMask( OS_IE_DMA4 | OS_IE_DMA5 | OS_IE_DMA6 | OS_IE_DMA7 );
+    (void)OS_EnableIrq();
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         ClearIntrCount
+
+  Description:  clear interrupt counter
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void ClearIntrCount(void)
+{
+    int i;
+
+    OS_ResetRequestIrqMask( OS_IE_DMA4 | OS_IE_DMA5 | OS_IE_DMA6 | OS_IE_DMA7 );
+
+    for (i=0; i<MI_EXDMA_CH_NUM; i++)
+    {
+        exDmaIntrCount[i] = 0;
+    }
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         PrintIntrCount
+
+  Description:  print interrupt counter
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void PrintIntrCount(void)
+{
+    OS_TPrintf( "\ninterrupt count: dma4 = %d, dma5 = %d, dma6 = %d, dma7 = %d.\n", 
+                exDmaIntrCount[0], exDmaIntrCount[1], exDmaIntrCount[2], exDmaIntrCount[3]);
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         ExDmaIntr
+
+  Description:  extended dma interrupt handler
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void ExDma4Intr(void)
+{
+    u32 ofs = 4 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA4 );
+}
+
+void ExDma5Intr(void)
+{
+    u32 ofs = 5 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA5 );
+}
+
+void ExDma6Intr(void)
+{
+    u32 ofs = 6 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA6 );
+}
+
+void ExDma7Intr(void)
+{
+    u32 ofs = 7 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA7 );
+}
+
+/*====== End of main.c ======*/

build/tests/mi/exDma-1/src/main.c

@@ -41,19 +41,29 @@ t_TestBuf testBuf __attribute__ ((aligned (32)));
 
 t_CommonArg copyfillArg[] =
 {
-    { testBuf.src,                   testBuf.dest,                   "DmaCopy success.\n", "DmaFill success on WRAM.\n", },
+    { testBuf.src,                   testBuf.dest,                   "DmaCopy success.\n", "DmaFill success on MAIN_MEM.\n", },
 };
 
 t_CommonArg stopArg[] =
 {
-    { testBuf.src,                   testBuf.dest,                   "Stopping DmaCopy success.\n", "Stopping DmaFill success on WRAM.\n", },
+    { testBuf.src,                   testBuf.dest,                   "Stopping DmaCopy success.\n", "Stopping DmaFill success on MAIN_MEM.\n", },
 };
 
 t_CommonArg copyfillAsyncArg[] =
 {
-    { testBuf.src,                   testBuf.dest,                   "DmaCopyAsync success.\n", "DmaFillAsync success on WRAM.\n", },
+    { testBuf.src,                   testBuf.dest,                   "DmaCopyAsync success.\n", "DmaFillAsync success on MAIN_MEM.\n", },
 };
 
+u32 exDmaIntrCount[MI_EXDMA_CH_NUM];
+
+void InitExDmaIntr(void);
+void ClearIntrCount(void);
+void PrintIntrCount(void);
+void ExDma4Intr(void);
+void ExDma5Intr(void);
+void ExDma6Intr(void);
+void ExDma7Intr(void);
+
 static BOOL CheckDmaCopy( u32 dmaNo, void *src, void *dest, const char *str )
 {
     BOOL ercd = TRUE;
@@ -136,10 +146,6 @@ static BOOL CheckDmaCopyAndFill( t_CommonArg *arg, u32 data )
         }
         c_ercd |= CheckDmaCopy( ch, s, d, str );
     }
-    if ( c_ercd == TRUE )
-    {
-        OS_TPrintf( copyStr );
-    }
 
     for (i=0; i<4; i++)
     {
@@ -156,10 +162,6 @@ static BOOL CheckDmaCopyAndFill( t_CommonArg *arg, u32 data )
         }
         f_ercd |= CheckDmaFill( ch, d, data+i, str );
     }
-    if ( f_ercd == TRUE )
-    {
-        OS_TPrintf( fillStr );
-    }
 
     return c_ercd | f_ercd;
 }
@@ -215,10 +217,6 @@ static BOOL CheckDmaCopyAndFillAsync( t_CommonArg *arg, u32 data )
         }
         c_ercd |= CheckDmaCopy( ch, s, d, str );
     }
-    if ( c_ercd == TRUE )
-    {
-        OS_TPrintf( copyStr );
-    }
 
     DC_FlushAll();
     for (i=0; i<4; i++)
@@ -253,10 +251,6 @@ static BOOL CheckDmaCopyAndFillAsync( t_CommonArg *arg, u32 data )
         }
         f_ercd |= CheckDmaFill( ch, d, data+i, str );
     }
-    if ( f_ercd == TRUE )
-    {
-        OS_TPrintf( fillStr );
-    }
 
     return c_ercd | f_ercd;
 }
@@ -322,6 +316,35 @@ static BOOL CheckDmaStop( t_CommonArg *arg )
     return c_ercd | f_ercd;
 }
 
+static void TestDmaFuncs( void )
+{
+    u32 i;
+
+    ClearIntrCount();
+
+    // sync copy and fill test
+    OS_TPrintf( "\nChecking DmaCopy and DmaFill ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaCopyAndFill( &copyfillArg[i], i );
+    }
+
+    // async copy and fill test
+    OS_TPrintf( "\nChecking DmaCopyAsync and DmaFillAsync ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaCopyAndFillAsync( &copyfillAsyncArg[i], i );
+    }
+
+    // stop test
+    OS_TPrintf( "\nChecking DmaStop ....\n" );
+    for (i=0; i<1; i++)
+    {
+        (void)CheckDmaStop( &stopArg[i] );
+    }
+
+    PrintIntrCount();
+}
 
 
 //================================================================================
@@ -336,35 +359,135 @@ static BOOL CheckDmaStop( t_CommonArg *arg )
  *---------------------------------------------------------------------------*/
 void TwlMain()
 {
-    u32 i;
-
     OS_Init();
 
-//    (void)OS_EnableIrq();
+    InitExDmaIntr();
 
-    OS_TPrintf("ARM9 starts.\n");
+    OS_TPrintf("\nARM9 starts.\n");
 
-    OS_TPrintf( "\nChecking DmaCopy and DmaFill ....\n" );
+//    OS_DisableProtectionUnit();
-    for (i=0; i<1; i++)
-    {
-        (void)CheckDmaCopyAndFill( &copyfillArg[i], i );
-    }
 
-    OS_TPrintf( "\nChecking DmaCopyAsync and DmaFillAsync ....\n" );
+    // priority dma test
-    for (i=0; i<1; i++)
+    OS_TPrintf( "\nTurn into Priority Mode.\n" );
-    {
-        (void)CheckDmaCopyAndFillAsync( &copyfillAsyncArg[i], i );
-    }
 
-    OS_TPrintf( "\nChecking DmaStop ....\n" );
+    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_PRIORITY, MI_EXDMAGBL_YLD_CYCLE_DEFAULT );
-    for (i=0; i<1; i++)
-    {
-        (void)CheckDmaStop( &stopArg[i] );
-    }
 
-    OS_TPrintf("ARM9 ends.\n");
+    TestDmaFuncs();
+
+    // round robin dma test
+    OS_TPrintf( "\nTurn into Round Robin Mode.\n" );
+
+    MIi_SetExDmaArbiter( MI_EXDMAGBL_ARB_ROUND_ROBIN, MI_EXDMAGBL_YLD_CYCLE_DEFAULT );
+
+    TestDmaFuncs();
+
+    OS_TPrintf("\nARM9 ends.\n");
     OS_Terminate();
 }
 
 
+/*---------------------------------------------------------------------------*
+  Name:         InitExDmaIntr
+
+  Description:  initialize extended dma interrupt handler
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void InitExDmaIntr(void)
+{
+    (void)OS_SetIrqFunction( OS_IE_DMA4, ExDma4Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA5, ExDma5Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA6, ExDma6Intr );
+    (void)OS_SetIrqFunction( OS_IE_DMA7, ExDma7Intr );
+    (void)OS_EnableIrqMask( OS_IE_DMA4 | OS_IE_DMA5 | OS_IE_DMA6 | OS_IE_DMA7 );
+    (void)OS_EnableIrq();
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         ClearIntrCount
+
+  Description:  clear interrupt counter
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void ClearIntrCount(void)
+{
+    int i;
+
+    OS_ResetRequestIrqMask( OS_IE_DMA4 | OS_IE_DMA5 | OS_IE_DMA6 | OS_IE_DMA7 );
+
+    for (i=0; i<MI_EXDMA_CH_NUM; i++)
+    {
+        exDmaIntrCount[i] = 0;
+    }
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         PrintIntrCount
+
+  Description:  print interrupt counter
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void PrintIntrCount(void)
+{
+    OS_TPrintf( "\ninterrupt count: dma4 = %d, dma5 = %d, dma6 = %d, dma7 = %d.\n", 
+                exDmaIntrCount[0], exDmaIntrCount[1], exDmaIntrCount[2], exDmaIntrCount[3]);
+}
+
+/*---------------------------------------------------------------------------*
+  Name:         ExDmaIntr
+
+  Description:  extended dma interrupt handler
+
+  Arguments:    None
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void ExDma4Intr(void)
+{
+    u32 ofs = 4 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA4 );
+}
+
+void ExDma5Intr(void)
+{
+    u32 ofs = 5 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA5 );
+}
+
+void ExDma6Intr(void)
+{
+    u32 ofs = 6 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA6 );
+}
+
+void ExDma7Intr(void)
+{
+    u32 ofs = 7 - MI_EXDMA_CH_MIN;
+
+    exDmaIntrCount[ofs]++;
+
+    //---- check interrupt flag
+    OS_SetIrqCheckFlag( OS_IE_DMA7 );
+}
+
 /*====== End of main.c ======*/

include/nitro/os/common/interrupt.h

@@ -66,6 +66,8 @@ void    OSi_EnterTimerCallback(u32 timerNo, void (*callback) (void *), void *arg
 #define OS_IE_CARD_B_DATA   (1UL << REG_OS_IE_MC_B_SHIFT) // card B data transfer finish
 #define OS_IE_CARD_B_IREQ   (1UL << REG_OS_IE_MI_B_SHIFT) // card B IREQ
 #define OS_IE_CARD_B_DET    (1UL << REG_OS_IE_MC_B_DET_SHIFT) // card B detect
+#define OS_IE_JTAG_TX       (1UL << REG_OS_IE_J_TX_MASK)// JTAG comm send
+#define OS_IE_JTAG_RX       (1UL << REG_OS_IE_J_RX_MASK)// JTAG comm receive
 #define OS_IE_DMA4          (1UL << REG_OS_IE_D4_SHIFT) // DMA4
 #define OS_IE_DMA5          (1UL << REG_OS_IE_D5_SHIFT) // DMA5
 #define OS_IE_DMA6          (1UL << REG_OS_IE_D6_SHIFT) // DMA6

include/twl/mi/exDma.h

@@ -28,18 +28,18 @@ extern "C" {
 //---- timing
 typedef enum
 {
-    MI_EXDMA_TIMING_IMM        = (0x10UL << REG_MI_DMA4CNT_TIMING_SHIFT),  // start immediately
+    MI_EXDMA_TIMING_IMM         = (0x10UL << REG_MI_DMA4CNT_TIMING_SHIFT),  // start immediately
-    MI_EXDMA_TIMING_TM0        = (0x0UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 0
+    MI_EXDMA_TIMING_TM0         = (0x0UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 0
-    MI_EXDMA_TIMING_TM1        = (0x1UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 1
+    MI_EXDMA_TIMING_TM1         = (0x1UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 1
-    MI_EXDMA_TIMING_TM2        = (0x2UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 2
+    MI_EXDMA_TIMING_TM2         = (0x2UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 2
-    MI_EXDMA_TIMING_TM3        = (0x3UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 3
+    MI_EXDMA_TIMING_TM3         = (0x3UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // timer 3
-    MI_EXDMA_TIMING_V_BLANK    = (0x4UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // VBlank
+    MI_EXDMA_TIMING_V_BLANK     = (0x4UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // VBlank
-    MI_EXDMA_TIMING_GCD        = (0x7UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // card
+    MI_EXDMA_TIMING_GCD         = (0x7UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // card
-    MI_EXDMA_TIMING_SD         = (0x8UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // SD
+    MI_EXDMA_TIMING_SD          = (0x8UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // SD
-    MI_EXDMA_TIMING_CAMERA     = (0x9UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // camera
+    MI_EXDMA_TIMING_CAMERA      = (0x9UL << REG_MI_DMA4CNT_TIMING_SHIFT),   // camera
-    MI_EXDMA_TIMING_AES_IN     = (0xAUL << REG_MI_DMA4CNT_TIMING_SHIFT),   // AES input
+    MI_EXDMA_TIMING_AES_IN      = (0xAUL << REG_MI_DMA4CNT_TIMING_SHIFT),   // AES input
-    MI_EXDMA_TIMING_AES_OUT    = (0xBUL << REG_MI_DMA4CNT_TIMING_SHIFT),   // AES output
+    MI_EXDMA_TIMING_AES_OUT     = (0xBUL << REG_MI_DMA4CNT_TIMING_SHIFT),   // AES output
-    MI_EXDMA_TIMING_MIC        = (0xCUL << REG_MI_DMA4CNT_TIMING_SHIFT)    // MIC
+    MI_EXDMA_TIMING_MIC         = (0xCUL << REG_MI_DMA4CNT_TIMING_SHIFT)    // MIC
 }
 MIExDmaTiming;
 
@@ -78,22 +78,29 @@ MIExDmaPrescaler;
 //---- yield cycle
 typedef enum
 {
-    MI_EXDMAGBL_YLD_CYCLE_0      = (0x0UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_0         = (0x0UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_1      = (0x1UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_1         = (0x1UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_2      = (0x2UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_2         = (0x2UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_4      = (0x3UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_4         = (0x3UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_8      = (0x4UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_8         = (0x4UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_16     = (0x5UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_16        = (0x5UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_32     = (0x6UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_32        = (0x6UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_64     = (0x7UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_64        = (0x7UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_128    = (0x8UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_128       = (0x8UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_256    = (0x9UL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_256       = (0x9UL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_512    = (0xAUL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_512       = (0xAUL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_1K     = (0xBUL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_1K        = (0xBUL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_2K     = (0xCUL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_2K        = (0xCUL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_4K     = (0xDUL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_4K        = (0xDUL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_8K     = (0xEUL << REG_MI_DMAGBL_YLD_SHIFT),
+    MI_EXDMAGBL_YLD_CYCLE_8K        = (0xEUL << REG_MI_DMAGBL_YLD_SHIFT),
-    MI_EXDMAGBL_YLD_CYCLE_16K    = (0xFUL << REG_MI_DMAGBL_YLD_SHIFT)
+    MI_EXDMAGBL_YLD_CYCLE_16K       = (0xFUL << REG_MI_DMAGBL_YLD_SHIFT),
+
+#ifdef SDK_ARM9
+    // the cache line read from the main memory is 20 cycles and the DSP access is added.
+    MI_EXDMAGBL_YLD_CYCLE_DEFAULT   = MI_EXDMAGBL_YLD_CYCLE_32
+#else // SDK_ARM7
+    MI_EXDMAGBL_YLD_CYCLE_DEFAULT   = MI_EXDMAGBL_YLD_CYCLE_16
+#endif // SDK_ARM7
 }
 MIExDmaYieldCycles;
 
@@ -216,6 +223,18 @@ void    MIi_WaitExDma( u32 dmaNo );
  *---------------------------------------------------------------------------*/
 void    MIi_StopExDma( u32 dmaNo );
 
+/*---------------------------------------------------------------------------*
+  Name:         MIi_StopDmaAsync
+
+  Description:  stop extended DMA
+                async version
+
+  Arguments:    dmaNo : DMA channel No.
+
+  Returns:      None
+ *---------------------------------------------------------------------------*/
+void MIi_StopExDmaAsync( u32 dmaNo );
+
 //================================================================================
 //            memory operation using DMA
 //================================================================================