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ヘッドフォンドライバオフ時のデポップ処理パラメータ変更

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@310 4ee2a332-4b2b-5046-8439-1ba90f034370
This commit is contained in:
kamikawa 2007-10-25 02:07:29 +00:00
parent 00534a2bdc
commit e5c5313bd1
2 changed files with 5 additions and 5 deletions
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6
build/libraries/cdc/ARM7/src/cdc_api.c
View File

@ -181,7 +181,7 @@ void CDC_InitSound( void )
*/
CDC_SetupDAC( CDC_HP_DRV_PWON_TM_DEFAULT,
CDC_HP_DRV_RAMPUP_TM_0MS,
CDC_HP_DRV_RAMPUP_TM_DEFAULT,
CDC_HPSP_DRV_RAMPDWN_TM_DEFAULT );
@ -204,7 +204,7 @@ void CDC_InitSound( void )
void CDC_InitMic( void )
{
// setup Mic Bias
CDC_WriteSpiRegisterEx( 1, REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_2_5V );
CDC_WriteSpiRegisterEx( 1, REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_AVDD );
#if 1 // このコードは本来、cdcInitSound呼び出しルーチンが記述すべきコード。
// Enable I2S
@ -303,7 +303,7 @@ void CDC_GoDsMode( void )
// マイクバイアスを設定しておく必要がある。
// DSモードに入ってからはこの設定を行う手段がない。
CDC_WriteSpiRegisterEx( 1, REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_2_5V );
CDC_WriteSpiRegisterEx( 1, REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_AVDD );
// PGAインピーダンス 設定も同様（18.8k 設定でDSと同等のゲインが得られる）
CDC_WriteSpiRegisterEx( 1, REG_CDC1_MIC_PGA_P_ADDR, 1 << CDC1_MIC_PGA_P_I_SHIFT);

4
include/twl/cdc/ARM7/cdc_reg.h
View File

@ -649,14 +649,14 @@ CDCBackCompatibleMode;
#define CDC_HP_DRV_PWON_TM_800MS ( 9<<CDC1_HP_DRV_TM_PWON_SHIFT)
#define CDC_HP_DRV_PWON_TM_2S (10<<CDC1_HP_DRV_TM_PWON_SHIFT)
#define CDC_HP_DRV_PWON_TM_4S (11<<CDC1_HP_DRV_TM_PWON_SHIFT)
#define CDC_HP_DRV_PWON_TM_DEFAULT CDC_HP_DRV_PWON_TM_200MS
#define CDC_HP_DRV_PWON_TM_DEFAULT CDC_HP_DRV_PWON_TM_0US
// ramp-up step time
#define CDC_HP_DRV_RAMPUP_TM_0MS ( 0<<CDC1_HP_DRV_TM_RAMPUP_SHIFT)
#define CDC_HP_DRV_RAMPUP_TM_1MS ( 1<<CDC1_HP_DRV_TM_RAMPUP_SHIFT)
#define CDC_HP_DRV_RAMPUP_TM_2MS ( 2<<CDC1_HP_DRV_TM_RAMPUP_SHIFT)
#define CDC_HP_DRV_RAMPUP_TM_4MS ( 3<<CDC1_HP_DRV_TM_RAMPUP_SHIFT)
#define CDC_HP_DRV_RAMPUP_TM_DEFAULT CDC_HP_DRV_RAMPUP_TM_4MS
#define CDC_HP_DRV_RAMPUP_TM_DEFAULT CDC_HP_DRV_RAMPUP_TM_0MS
//---- CDC1_HPSP_RAMPDWN (reg34)
#define CDC1_HPSP_RAMPDWN_TM_SHIFT 0