mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
755 lines
23 KiB
NASM
755 lines
23 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c
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; In-file : i2c_twl.c
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; Asm-file : inter_asm\i2c_twl.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 06FH, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, i2c_twl.c
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$DGS MOD_NAM, i2c_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _int_iic_twl, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H
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$DGS BEG_FUN, ??bf_int_iic_twl, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 052H, 01CH, 01BH
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$DGS AUT_VAR, _temp, 05H, 0FFFFH, 0CH, 01H, 00H, 00H
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$DGS AUT_VAR, _tot, 02H, 0FFFFH, 0DH, 01H, 00H, 00H
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$DGS BEG_BLK, ??bb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 011H, 00H, 01DH
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$DGS BEG_BLK, ??bb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 011H, 00H, 01FH
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$DGS BEG_BLK, ??bb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 011H, 00H, 023H
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$DGS END_BLK, ??eb02_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS BEG_BLK, ??bb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 011H, 00H, 02BH
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$DGS END_BLK, ??eb03_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS END_BLK, ??eb01_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS END_BLK, ??eb00_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS BEG_BLK, ??bb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01EH, 00H, 02FH
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$DGS AUT_VAR, _my_iics, 01H, 0FFFFH, 0CH, 01H, 01H, 00H
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$DGS AUX_STR, 00H, 01FH, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BEG_BLK, ??bb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 022H, 00H, 033H
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$DGS END_BLK, ??eb05_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 025H
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$DGS BEG_BLK, ??bb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 027H, 00H, 035H
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$DGS BEG_BLK, ??bb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02CH, 00H, 037H
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$DGS BEG_BLK, ??bb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02CH, 00H, 039H
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$DGS BEG_BLK, ??bb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02CH, 00H, 03DH
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$DGS END_BLK, ??eb09_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02CH
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$DGS BEG_BLK, ??bb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02CH, 00H, 045H
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$DGS END_BLK, ??eb0A_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02CH
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$DGS END_BLK, ??eb08_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02CH
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$DGS END_BLK, ??eb07_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 02CH
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$DGS BEG_BLK, ??bb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02FH, 00H, 049H
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$DGS END_BLK, ??eb0B_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 032H
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$DGS BEG_BLK, ??bb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 035H, 00H, 04BH
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$DGS BEG_BLK, ??bb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 035H, 00H, 04DH
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$DGS BEG_BLK, ??bb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 035H, 00H, 051H
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$DGS END_BLK, ??eb0E_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 035H
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$DGS BEG_BLK, ??bb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 035H, 00H, 05BH
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$DGS END_BLK, ??eb0F_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 035H
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$DGS END_BLK, ??eb0D_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 035H
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$DGS END_BLK, ??eb0C_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 035H
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$DGS END_BLK, ??eb06_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03AH
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$DGS BEG_BLK, ??bb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03CH, 00H, 00H
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$DGS END_BLK, ??eb10_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 046H
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$DGS END_BLK, ??eb04_int_iic_twl, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 047H
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$DGS END_FUN, ??ef_int_iic_twl, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 048H
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$DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 069H, 00H, 00H
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$DGS BEG_FUN, ??bf_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 09FH, 00H, 069H
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$DGS END_FUN, ??ef_IIC_twl_Init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 024H
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$DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 06FH, 00H, 00H
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$DGS BEG_FUN, ??bf_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0C8H, 00H, 06FH
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$DGS END_FUN, ??ef_IIC_twl_Stop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 04H
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$DGS GLV_SYM, _vreg_adrs, U, U, 0CH, 026H, 00H, 00H
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$DGS GLV_SYM, _pre_dat, U, U, 0CH, 026H, 00H, 00H
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$DGS GLV_SYM, _tot, U, U, 0DH, 026H, 00H, 00H
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$DGS GLV_SYM, _@SEGAX, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _@SEGDE, U, U, 00H, 02H, 00H, 00H
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$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
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EXTRN _@SEGAX
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EXTRN _@SEGDE
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EXTRN _@RTARG0
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EXTRN _adrs_table_twl_ext2int
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EXTRN _vreg_twl_read
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EXTRN _vreg_twl_write
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PUBLIC _vreg_adrs
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PUBLIC _pre_dat
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PUBLIC _tot
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PUBLIC _int_iic_twl
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PUBLIC _IIC_twl_Init
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PUBLIC _IIC_twl_Stop
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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DB 025H ; 37
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DB 038H ; 56
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DB 04DH ; 77
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DB 05FH ; 95
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DB 06EH ; 110
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DB 077H ; 119
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DB 07AH ; 122
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DB 077H ; 119
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DB 06EH ; 110
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DB 05FH ; 95
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DB 04DH ; 77
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DB 038H ; 56
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DB 025H ; 37
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DB 012H ; 18
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DB 04H ; 4
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DB 0FAH ; 250
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0F7H ; 247
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DB 0FBH ; 251
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DB 0FEH ; 254
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DB 00H ; 0
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 02H ; 2
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DB 01H ; 1
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DB (1)
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@@R_INIT CSEG UNIT64KP
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@@INIT DSEG BASEP
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@@DATA DSEG BASEP
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_vreg_adrs: DS (1)
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_pre_dat: DS (1)
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_tot: DS (2)
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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@@CNSTL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : #pragma sfr /* <20><><EFBFBD><EFBFBD><EFBFBD>@<40>\<5C><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>g<EFBFBD>p */
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; line 2 :
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; line 3 :
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; line 4 :
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; line 5 : /*==============================================================
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; ==============*/
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; line 6 : #include "incs.h"
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; line 7 : #include "i2c_twl_defs.h"
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; line 8 :
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; line 9 :
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; line 10 : extern u8 vreg_twl[];
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; line 11 :
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; line 12 : #ifdef _MCU_BSR_
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; line 13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_
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; line 14 :
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; line 15 : // <20><><EFBFBD>[<5B>L<EFBFBD><4C><EFBFBD>O<EFBFBD><4F><EFBFBD>f<EFBFBD><66><EFBFBD><EFBFBD>I2C<32><43><EFBFBD>t
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; line 16 : #define ACKD ACKD0
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; line 17 : #define ACKE ACKE0
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; line 18 : #define COI COI0
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; line 19 : #define IICAEN IICA0EN
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; line 20 : #define IICRSV IICRSV0
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; line 21 : #define IICA IICA0
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; line 22 : #define IICAIF IICAIF0
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; line 23 : #define IICAMK IICAMK0
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; line 24 : #define IICAPR0 IICAPR00
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; line 25 : #define IICAPR1 IICAPR10
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; line 26 : #define IICCTL0 IICCTL00
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; line 27 : #define IICE IICE0
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; line 28 : #define IICF IICF0
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; line 29 : #define IICS IICS0
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; line 30 : #define IICWH IICWH0
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; line 31 : #define IICWL IICWL0
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; line 32 : #define LREL LREL0
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; line 33 : #define SPD SPD0
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; line 34 : #define SPIE SPIE0
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; line 35 : #define STCEN STCEN0
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; line 36 : #define STD STD0
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; line 37 : #define SVA SVA0
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; line 38 : #define WREL WREL0
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; line 39 : #define WTIM WTIM0
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; line 40 : #define SMC SMC0
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; line 41 :
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; line 42 : #endif
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; line 43 :
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; line 44 : #ifndef _MCU_BSR_
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; line 45 :
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; line 46 : // ke3<65>̎<EFBFBD><CC8E>̓_<CD83>~<7E>[<5B><EFBFBD>
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; line 47 : void IIC_twl_Stop( void )
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; line 48 : {
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; line 49 : }
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; line 50 : void IIC_twl_Init( void )
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; line 51 : {
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; line 52 : }
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; line 53 : #else
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; line 54 :
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; line 55 :
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; line 56 : /*==============================================================
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; ==============*/
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; line 57 : u8 vreg_adrs;
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; line 58 : u8 pre_dat;
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; line 59 :
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; line 60 :
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; line 61 : u16 tot;
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; line 62 :
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; line 63 :
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; line 64 : // <20><><EFBFBD>I<EFBFBD>@<40><><EFBFBD>̓}<7D>N<EFBFBD><4E><EFBFBD>Ȃ̂ŁAreturn<72>̓<EFBFBD><CD83>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>[<5B>v<EFBFBD>ɖ߂<C996><DF82>܂<EFBFBD><DC82>B
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; line 65 : #define wait_next { \
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; line 66 : tot = 0; \
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; line 67 : while( IICAIF != 1 ){ \
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; line 68 : if( SPD ){ \
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; line 69 : LREL = 1; \
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; line 70 : return; \
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; line 71 : } \
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; line 72 : tot++; \
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; line 73 : if( tot == 0 ){ \
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; line 74 : LREL = 1; \
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; line 75 : return; \
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; line 76 : } \
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; line 77 : } \
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; line 78 : }
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; line 79 :
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; line 80 :
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; line 81 : __interrupt void int_iic_twl( )
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; line 82 : {
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@@BASE CSEG BASE
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_int_iic_twl:
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$DGL 1,21
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push ax ;[INF] 1, 1
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push bc ;[INF] 1, 1
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push de ;[INF] 1, 1
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push hl ;[INF] 1, 1
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mov c,#0CH ;[INF] 2, 1
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dec c ;[INF] 1, 1
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dec c ;[INF] 1, 1
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movw ax,_@SEGAX[c] ;[INF] 3, 1
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push ax ;[INF] 1, 1
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bnz $$-6 ;[INF] 2, 4
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mov a,ES ;[INF] 2, 1
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mov x,a ;[INF] 1, 1
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mov a,CS ;[INF] 2, 1
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push ax ;[INF] 1, 1
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subw sp,#06H ;[INF] 2, 1
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movw hl,sp ;[INF] 3, 1
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??bf_int_iic_twl:
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; line 83 : u8 temp;
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; line 84 : u16 tot;
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; line 85 :
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; line 86 : // WDT_Restart();
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; line 87 : // <20>t<EFBFBD><74><EFBFBD>O<EFBFBD>P<EFBFBD><50><EFBFBD><EFBFBD> <20>X<EFBFBD><58><EFBFBD>[<5B>u<EFBFBD>A<EFBFBD>h<EFBFBD><68><EFBFBD>X,R/W
|
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; line 88 : /* COI != 1 <20>Ȃ<EFBFBD><C882>A<EFBFBD><41><EFBFBD>荞<EFBFBD>݂͂<DD82><CD82><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
; line 89 : if( COI != 1 ){ // <20><><EFBFBD>Ăяo<D18F><6F><EFBFBD>H
|
||
; line 90 : LREL = 1; // <20>Ăꂽ<CE82>̂͑<CC82><CD91><EFBFBD>ID
|
||
; line 91 : return;
|
||
; line 92 : }else{
|
||
; line 93 : ACKE0 = 1; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ack<63><6B><EFBFBD>Ԃ<EFBFBD><D482>悤<EFBFBD>ɂ<EFBFBD><C982><EFBFBD>
|
||
; line 94 : WREL = 1; // <20>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ď<EFBFBD><C48E>̃o<CC83>C<EFBFBD>g<EFBFBD><67><EFBFBD>҂<EFBFBD>
|
||
; line 95 : }
|
||
; line 96 : */
|
||
; line 97 : WREL = 1; // <20>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ď<EFBFBD><C48E>̃o<CC83>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD>
|
||
; <20><>
|
||
$DGL 0,16
|
||
set1 !IICCTL00.5 ;[INF] 4, 2
|
||
; line 98 : wait_next; // <20>P<EFBFBD>o<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>M<EFBFBD><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>҂<EFBFBD>
|
||
$DGL 0,17
|
||
??bb00_int_iic_twl:
|
||
clrw ax ;[INF] 1, 1
|
||
movw [hl+2],ax ; tot ;[INF] 2, 1
|
||
?L0003:
|
||
bt IF1L.3,$?L0004 ;[INF] 4, 5
|
||
??bb01_int_iic_twl:
|
||
bf IICS0.0,$?L0005 ;[INF] 4, 5
|
||
??bb02_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br !?L0010 ;[INF] 3, 3
|
||
??eb02_int_iic_twl:
|
||
?L0005:
|
||
incw [hl+2] ; tot ;[INF] 3, 2
|
||
clrw ax ;[INF] 1, 1
|
||
cmpw ax,[hl+2] ; tot ;[INF] 3, 1
|
||
bnz $?L0003 ;[INF] 2, 4
|
||
??bb03_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br !?L0010 ;[INF] 3, 3
|
||
??eb03_int_iic_twl:
|
||
??eb01_int_iic_twl:
|
||
?L0004:
|
||
??eb00_int_iic_twl:
|
||
; line 99 :
|
||
; line 100 : // <20>Q<EFBFBD><51><EFBFBD><EFBFBD> R/W <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>A<EFBFBD>h<EFBFBD><68><EFBFBD>X
|
||
; line 101 : temp = IICA;
|
||
$DGL 0,20
|
||
mov a,IICA0 ;[INF] 2, 1
|
||
mov [hl+5],a ; temp ;[INF] 2, 1
|
||
; line 102 : IICAIF = 0;
|
||
$DGL 0,21
|
||
clr1 IF1L.3 ;[INF] 3, 2
|
||
; line 103 : WREL = 1;
|
||
$DGL 0,22
|
||
set1 !IICCTL00.5 ;[INF] 4, 2
|
||
; line 104 :
|
||
; line 105 : vreg_adrs = adrs_table_twl_ext2int( temp );
|
||
$DGL 0,24
|
||
mov a,[hl+5] ; temp ;[INF] 2, 1
|
||
shrw ax,8 ;[INF] 2, 1
|
||
call !_adrs_table_twl_ext2int ;[INF] 3, 3
|
||
mov a,c ;[INF] 1, 1
|
||
mov !_vreg_adrs,a ;[INF] 3, 1
|
||
; line 106 :
|
||
; line 107 : // <20>R<EFBFBD><52><EFBFBD><EFBFBD>
|
||
; line 108 : // <20>X<EFBFBD>^<5E>[<5B>g<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD>M<EFBFBD><4D><EFBFBD><EFBFBD><EFBFBD>t<EFBFBD><74><EFBFBD>O<EFBFBD>҂<EFBFBD>
|
||
; line 109 :
|
||
; line 110 : while( 1 )
|
||
?L0009:
|
||
; line 111 : {
|
||
??bb04_int_iic_twl:
|
||
; line 112 : u8 my_iics = IICS;
|
||
$DGL 0,31
|
||
mov a,IICS0 ;[INF] 2, 1
|
||
mov [hl+1],a ; my_iics ;[INF] 2, 1
|
||
; line 113 :
|
||
; line 114 : if( my_iics & 0x01 ) // SPD
|
||
$DGL 0,33
|
||
and a,#01H ; 1 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0011 ;[INF] 2, 4
|
||
; line 115 : { // <20><><EFBFBD><EFBFBD><EFBFBD>I<EFBFBD><49>
|
||
??bb05_int_iic_twl:
|
||
; line 116 : LREL = 1;
|
||
$DGL 0,35
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
; line 117 : return;
|
||
$DGL 0,36
|
||
br !?L0010 ;[INF] 3, 3
|
||
??eb05_int_iic_twl:
|
||
; line 118 : }
|
||
?L0011:
|
||
; line 119 : else if( my_iics & 0x02 ) // ( STD && !SPD )
|
||
$DGL 0,38
|
||
mov a,[hl+1] ; my_iics ;[INF] 2, 1
|
||
and a,#02H ; 2 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0013 ;[INF] 2, 4
|
||
; line 120 : {
|
||
??bb06_int_iic_twl:
|
||
; line 121 : // <20><><EFBFBD>M // (<28>X<EFBFBD>^<5E>[<5B>g<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o)
|
||
; line 122 : pre_dat = vreg_twl_read( vreg_adrs ); // mcu<63><75>
|
||
; <20><><EFBFBD>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD><58><EFBFBD>n<EFBFBD><6E><EFBFBD>B<EFBFBD><42><EFBFBD>o<EFBFBD>C<EFBFBD>g<EFBFBD>ڂ̏<DA82><CC8F><EFBFBD> IICB<43>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ނƃE<C683>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD>
|
||
$DGL 0,41
|
||
mov x,!_vreg_adrs ;[INF] 3, 1
|
||
clrb a ;[INF] 1, 1
|
||
call !_vreg_twl_read ;[INF] 3, 3
|
||
mov a,c ;[INF] 1, 1
|
||
mov !_pre_dat,a ;[INF] 3, 1
|
||
; line 123 :
|
||
; line 124 : // <20><><EFBFBD>ǂ<EFBFBD>R<EFBFBD>ŌĂ<C482><CE82><EFBFBD><EFBFBD>̂<EFBFBD><CC82>҂<EFBFBD>
|
||
; line 125 : wait_next;
|
||
$DGL 0,44
|
||
??bb07_int_iic_twl:
|
||
clrw ax ;[INF] 1, 1
|
||
movw [hl+2],ax ; tot ;[INF] 2, 1
|
||
?L0015:
|
||
bt IF1L.3,$?L0016 ;[INF] 4, 5
|
||
??bb08_int_iic_twl:
|
||
bf IICS0.0,$?L0017 ;[INF] 4, 5
|
||
??bb09_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb09_int_iic_twl:
|
||
?L0017:
|
||
incw [hl+2] ; tot ;[INF] 3, 2
|
||
clrw ax ;[INF] 1, 1
|
||
cmpw ax,[hl+2] ; tot ;[INF] 3, 1
|
||
bnz $?L0015 ;[INF] 2, 4
|
||
??bb0A_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb0A_int_iic_twl:
|
||
; line 126 : IICAIF = 0;
|
||
$DGL 0,45
|
||
??eb08_int_iic_twl:
|
||
?L0016:
|
||
??eb07_int_iic_twl:
|
||
clr1 IF1L.3 ;[INF] 3, 2
|
||
; line 127 : if( COI != 1 )
|
||
$DGL 0,46
|
||
bt IICS0.4,$?L0021 ;[INF] 4, 5
|
||
; line 128 : { // <20><><EFBFBD>Ăяo<D18F><6F><EFBFBD>H
|
||
??bb0B_int_iic_twl:
|
||
; line 129 : LREL = 1; // <20>Ăꂽ<CE82>̂͑<CC82><CD91><EFBFBD>ID<49>i<EFBFBD><69><EFBFBD><EFBFBD><EFBFBD>H<EFBFBD>j
|
||
$DGL 0,48
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
; line 130 : return;
|
||
$DGL 0,49
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb0B_int_iic_twl:
|
||
; line 131 : }
|
||
?L0021:
|
||
; line 132 : IICA = pre_dat; // <20>f<EFBFBD>[<5B>^<5E>𑗂<EFBFBD><F0919782>B<EFBFBD>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>B
|
||
$DGL 0,51
|
||
mov a,!_pre_dat ;[INF] 3, 1
|
||
mov IICA0,a ;[INF] 2, 1
|
||
; line 133 :
|
||
; line 134 : wait_next;
|
||
$DGL 0,53
|
||
??bb0C_int_iic_twl:
|
||
clrw ax ;[INF] 1, 1
|
||
movw [hl+2],ax ; tot ;[INF] 2, 1
|
||
?L0023:
|
||
bt IF1L.3,$?L0024 ;[INF] 4, 5
|
||
??bb0D_int_iic_twl:
|
||
bf IICS0.0,$?L0025 ;[INF] 4, 5
|
||
??bb0E_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb0E_int_iic_twl:
|
||
?L0025:
|
||
incw [hl+2] ; tot ;[INF] 3, 2
|
||
clrw ax ;[INF] 1, 1
|
||
cmpw ax,[hl+2] ; tot ;[INF] 3, 1
|
||
bnz $?L0023 ;[INF] 2, 4
|
||
??bb0F_int_iic_twl:
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb0F_int_iic_twl:
|
||
; line 135 : // <20>S<EFBFBD><53><EFBFBD>ځB(<28><><EFBFBD>M<EFBFBD>f<EFBFBD>[<5B>^<5E><><EFBFBD>́AACK/NACK<43><4B>)<29>@<40>ǂ<EFBFBD><C782><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD><DC82>B
|
||
??eb0D_int_iic_twl:
|
||
?L0024:
|
||
??eb0C_int_iic_twl:
|
||
; line 136 : IICAIF = 0; // <20><><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
$DGL 0,55
|
||
clr1 IF1L.3 ;[INF] 3, 2
|
||
; line 137 : LREL = 1;
|
||
$DGL 0,56
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
; line 138 : return;
|
||
$DGL 0,57
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb06_int_iic_twl:
|
||
; line 139 : }
|
||
?L0013:
|
||
; line 140 : else if( IICAIF && (( my_iics & 0x03 ) == 0 )) // !STD
|
||
; && !SPD )
|
||
$DGL 0,59
|
||
bf IF1L.3,$?L0029 ;[INF] 4, 5
|
||
mov a,[hl+1] ; my_iics ;[INF] 2, 1
|
||
and a,#03H ; 3 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0029 ;[INF] 2, 4
|
||
; line 141 : {
|
||
??bb10_int_iic_twl:
|
||
; line 142 : // <20><><EFBFBD>M //
|
||
; line 143 : IICAIF = 0;
|
||
$DGL 0,62
|
||
clr1 IF1L.3 ;[INF] 3, 2
|
||
; line 144 : temp = IICA;
|
||
$DGL 0,63
|
||
mov a,IICA0 ;[INF] 2, 1
|
||
mov [hl+5],a ; temp ;[INF] 2, 1
|
||
; line 145 : WREL = 1;
|
||
$DGL 0,64
|
||
set1 !IICCTL00.5 ;[INF] 4, 2
|
||
; line 146 :
|
||
; line 147 : // <20>ʏ<EFBFBD><CA8F>A<EFBFBD>N<EFBFBD>Z<EFBFBD>X(<28><><EFBFBD>C<EFBFBD>g) //
|
||
; line 148 : LREL = 1; // <20>X<EFBFBD>^<5E>[<5B>g<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>҂<EFBFBD><D282><EFBFBD>(
|
||
; <20>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݖ<EFBFBD><DD96>Ή<EFBFBD><CE89>̂<EFBFBD><CC82><EFBFBD>)
|
||
$DGL 0,67
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
; line 149 : vreg_twl_write( vreg_adrs, temp );
|
||
$DGL 0,68
|
||
mov a,[hl+5] ; temp ;[INF] 2, 1
|
||
shrw ax,8 ;[INF] 2, 1
|
||
push ax ;[INF] 1, 1
|
||
mov x,!_vreg_adrs ;[INF] 3, 1
|
||
call !_vreg_twl_write ;[INF] 3, 3
|
||
pop ax ;[INF] 1, 1
|
||
; line 150 : return; // <20><><EFBFBD>M<EFBFBD><4D><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD> //
|
||
$DGL 0,69
|
||
br $?L0010 ;[INF] 2, 3
|
||
??eb10_int_iic_twl:
|
||
; line 151 : }
|
||
?L0029:
|
||
??eb04_int_iic_twl:
|
||
; line 152 : }
|
||
$DGL 0,71
|
||
br !?L0009 ;[INF] 3, 3
|
||
?L0010:
|
||
; line 153 : }
|
||
$DGL 0,72
|
||
??ef_int_iic_twl:
|
||
addw sp,#06H ;[INF] 2, 1
|
||
pop ax ;[INF] 1, 1
|
||
mov CS,a ;[INF] 2, 1
|
||
mov a,x ;[INF] 1, 1
|
||
mov ES,a ;[INF] 2, 1
|
||
movw de,#_@SEGAX ;[INF] 3, 1
|
||
mov c,#06H ;[INF] 2, 1
|
||
pop ax ;[INF] 1, 1
|
||
movw [de],ax ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $$-5 ;[INF] 2, 4
|
||
pop hl ;[INF] 1, 1
|
||
pop de ;[INF] 1, 1
|
||
pop bc ;[INF] 1, 1
|
||
pop ax ;[INF] 1, 1
|
||
reti ;[INF] 2, 6
|
||
??ee_int_iic_twl:
|
||
; line 154 :
|
||
; line 155 :
|
||
; line 156 :
|
||
; line 157 : /*****************************************************/
|
||
; line 158 : void IIC_twl_Init( void )
|
||
; line 159 : {
|
||
|
||
ROM_CODE CSEG BASE
|
||
_IIC_twl_Init:
|
||
$DGL 1,99
|
||
??bf_IIC_twl_Init:
|
||
; line 160 :
|
||
; line 161 : IICAEN = 1;
|
||
$DGL 0,3
|
||
set1 !PER0.4 ;[INF] 4, 2
|
||
; line 162 :
|
||
; line 163 : IICE = 0; /* IICA disable */
|
||
$DGL 0,5
|
||
clr1 !IICCTL00.7 ;[INF] 4, 2
|
||
; line 164 :
|
||
; line 165 : IICAMK = 1; /* INTIICA disable */
|
||
$DGL 0,7
|
||
set1 MK1L.3 ;[INF] 3, 2
|
||
; line 166 : IICAIF = 0; /* clear INTIICA interrupt flag
|
||
; */
|
||
$DGL 0,8
|
||
clr1 IF1L.3 ;[INF] 3, 2
|
||
; line 167 :
|
||
; line 168 : IICAPR0 = 0; /* set INTIICA high priority */
|
||
$DGL 0,10
|
||
clr1 PR01L.3 ;[INF] 3, 2
|
||
; line 169 : IICAPR1 = 0; /* set INTIICA high priority */
|
||
$DGL 0,11
|
||
clr1 PR11L.3 ;[INF] 3, 2
|
||
; line 170 : P20 &= ~0x3;
|
||
$DGL 0,12
|
||
mov a,!P20 ;[INF] 3, 1
|
||
and a,#0FCH ; 252 ;[INF] 2, 1
|
||
mov !P20,a ;[INF] 3, 1
|
||
; line 171 :
|
||
; line 172 : SVA = IIC_T_SLAVEADDRESS;
|
||
$DGL 0,14
|
||
mov !SVA0,#04AH ; 74 ;[INF] 4, 1
|
||
; line 173 : IICF = 0x01;
|
||
$DGL 0,15
|
||
oneb !IICF0 ;[INF] 3, 1
|
||
; line 174 :
|
||
; line 175 : STCEN = 1; // <20><><EFBFBD>X<EFBFBD>^<5E>[<5B>g<EFBFBD>̋<EFBFBD><CC8B><EFBFBD>
|
||
$DGL 0,17
|
||
set1 IICF0.1 ;[INF] 3, 2
|
||
; line 176 : IICRSV = 1; // <20>ʐM<CA90>\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>:<3A>X<EFBFBD><58><EFBFBD>[<5B>u<EFBFBD><75>
|
||
; <20>O<EFBFBD><4F><EFBFBD><EFBFBD>
|
||
$DGL 0,18
|
||
set1 IICF0.0 ;[INF] 3, 2
|
||
; line 177 :
|
||
; line 178 : SPIE = 0; // <20>X<EFBFBD>g<EFBFBD>b<EFBFBD>v<EFBFBD>R<EFBFBD><52><EFBFBD>f<EFBFBD>B<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>ł̊<C582><CC8A><EFBFBD>
|
||
; <20><><EFBFBD>݂<EFBFBD><DD82>֎~
|
||
$DGL 0,20
|
||
clr1 !IICCTL00.4 ;[INF] 4, 2
|
||
; line 179 : WTIM = 1; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ACK<43><4B><EFBFBD>Ԃ<EFBFBD><D482><EFBFBD><EFBFBD><EFBFBD>clk<6C><6B>L<EFBFBD>Ɍ<EFBFBD>
|
||
; <20>肷<EFBFBD><E882B7>
|
||
$DGL 0,21
|
||
set1 !IICCTL00.3 ;[INF] 4, 2
|
||
; line 180 : ACKE = 1; // <20>_<EFBFBD><5F>CPU<50>͖<EFBFBD><CD96><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ď<EFBFBD><C48E>̒ʐM<CA90><4D><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>߂邩<DF82><E982A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD>ő<EFBFBD><C591><EFBFBD>clk<6C><6B><EFBFBD>J<EFBFBD><4A><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
$DGL 0,22
|
||
set1 !IICCTL00.2 ;[INF] 4, 2
|
||
; line 181 :
|
||
; line 182 : IICWH = 5;
|
||
$DGL 0,24
|
||
mov !IICWH0,#05H ; 5 ;[INF] 4, 1
|
||
; line 183 : IICWL = 10; // L<><4C><EFBFBD>Ԃ̒<D482><CC92><EFBFBD><EFBFBD>i<EFBFBD>H<EFBFBD>j
|
||
$DGL 0,25
|
||
mov !IICWL0,#0AH ; 10 ;[INF] 4, 1
|
||
; line 184 :
|
||
; line 185 : SMC = 1;
|
||
$DGL 0,27
|
||
set1 !IICCTL10.3 ;[INF] 4, 2
|
||
; line 186 :
|
||
; line 187 : IICAMK = 0; // <20><><EFBFBD>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD>
|
||
$DGL 0,29
|
||
clr1 MK1L.3 ;[INF] 3, 2
|
||
; line 188 :
|
||
; line 189 : IICE = 1;
|
||
$DGL 0,31
|
||
set1 !IICCTL00.7 ;[INF] 4, 2
|
||
; line 190 :
|
||
; line 191 : PM20 &= ~0x3; /* set clock pin for IICA */
|
||
$DGL 0,33
|
||
mov a,!PM20 ;[INF] 3, 1
|
||
and a,#0FCH ; 252 ;[INF] 2, 1
|
||
mov !PM20,a ;[INF] 3, 1
|
||
; line 192 :
|
||
; line 193 : LREL = 1;
|
||
$DGL 0,35
|
||
set1 !IICCTL00.6 ;[INF] 4, 2
|
||
; line 194 : }
|
||
$DGL 0,36
|
||
??ef_IIC_twl_Init:
|
||
ret ;[INF] 1, 6
|
||
??ee_IIC_twl_Init:
|
||
; line 195 :
|
||
; line 196 :
|
||
; line 197 :
|
||
; line 198 : //**************************************************************
|
||
; **************
|
||
; line 199 : void IIC_twl_Stop( void )
|
||
; line 200 : {
|
||
_IIC_twl_Stop:
|
||
$DGL 1,105
|
||
??bf_IIC_twl_Stop:
|
||
; line 201 : IICE = 0; /* IICA disable */
|
||
$DGL 0,2
|
||
clr1 !IICCTL00.7 ;[INF] 4, 2
|
||
; line 202 : IICAEN = 0;
|
||
$DGL 0,3
|
||
clr1 !PER0.4 ;[INF] 4, 2
|
||
; line 203 : }
|
||
$DGL 0,4
|
||
??ef_IIC_twl_Stop:
|
||
ret ;[INF] 1, 6
|
||
??ee_IIC_twl_Stop:
|
||
|
||
@@CODEL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c
|
||
;
|
||
; $FUNC int_iic_twl(82)
|
||
; void=(void)
|
||
; CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes
|
||
;
|
||
; $CALL adrs_table_twl_ext2int(105)
|
||
; bc=(int:ax)
|
||
;
|
||
; $CALL vreg_twl_read(122)
|
||
; bc=(int:ax)
|
||
;
|
||
; $CALL vreg_twl_write(149)
|
||
; void=(int:ax, int:[sp+4])
|
||
;
|
||
; $FUNC IIC_twl_Init(159)
|
||
; void=(void)
|
||
; CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC IIC_twl_Stop(200)
|
||
; void=(void)
|
||
; CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|