; 78K0R C Compiler V2.10 Assembler Source        Date:13 Jun 2010 Time:19:31:24

; Command   : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
;             renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
;             V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no i2c_twl.c
; In-file   : i2c_twl.c
; Asm-file  : inter_asm\i2c_twl.asm
; Para-file : 

$PROCESSOR(9F0104)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF	03FH, 0210H, 00H, 00H, 00H, 00H, 00H

$DGS	FIL_NAM, .file,		06FH,	0FFFEH,	03FH,	067H,	01H,	00H
$DGS	AUX_FIL, i2c_twl.c
$DGS	MOD_NAM, i2c_twl,	00H,	0FFFEH,	00H,	077H,	00H,	00H
$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNSTL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@RLINIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INITL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATAL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, ROM_CODE,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CODEL,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@BASE,	U,	U,	00H,	078H,	00H,	00H
$DGS	STA_SYM, _lpf_coeff,	U,	U,	05002H,	03H,	01H,	03H
$DGS	AUX_STR, 00H,		00H,	02FH,	02FH,	00H,	00H,	00H,	00H
$DGS	GLV_SYM, _int_iic_twl,	U,	U,	0E001H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	063H,	00H,	00H
$DGS	BEG_FUN, ??bf_int_iic_twl,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 052H,		01CH,	01BH
$DGS	AUT_VAR, _temp,		05H,	0FFFFH,	0CH,	01H,	00H,	00H
$DGS	AUT_VAR, _tot,		02H,	0FFFFH,	0DH,	01H,	00H,	00H
$DGS	BEG_BLK, ??bb00_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 011H,		00H,	01DH
$DGS	BEG_BLK, ??bb01_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 011H,		00H,	01FH
$DGS	BEG_BLK, ??bb02_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 011H,		00H,	023H
$DGS	END_BLK, ??eb02_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	BEG_BLK, ??bb03_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 011H,		00H,	02BH
$DGS	END_BLK, ??eb03_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	END_BLK, ??eb01_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	END_BLK, ??eb00_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 011H
$DGS	BEG_BLK, ??bb04_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 01EH,		00H,	02FH
$DGS	AUT_VAR, _my_iics,	01H,	0FFFFH,	0CH,	01H,	01H,	00H
$DGS	AUX_STR, 00H,		01FH,	01H,	00H,	00H,	00H,	00H,	00H
$DGS	BEG_BLK, ??bb05_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 022H,		00H,	033H
$DGS	END_BLK, ??eb05_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 025H
$DGS	BEG_BLK, ??bb06_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 027H,		00H,	035H
$DGS	BEG_BLK, ??bb07_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02CH,		00H,	037H
$DGS	BEG_BLK, ??bb08_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02CH,		00H,	039H
$DGS	BEG_BLK, ??bb09_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02CH,		00H,	03DH
$DGS	END_BLK, ??eb09_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02CH
$DGS	BEG_BLK, ??bb0A_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02CH,		00H,	045H
$DGS	END_BLK, ??eb0A_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02CH
$DGS	END_BLK, ??eb08_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02CH
$DGS	END_BLK, ??eb07_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 02CH
$DGS	BEG_BLK, ??bb0B_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 02FH,		00H,	049H
$DGS	END_BLK, ??eb0B_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 032H
$DGS	BEG_BLK, ??bb0C_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 035H,		00H,	04BH
$DGS	BEG_BLK, ??bb0D_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 035H,		00H,	04DH
$DGS	BEG_BLK, ??bb0E_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 035H,		00H,	051H
$DGS	END_BLK, ??eb0E_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 035H
$DGS	BEG_BLK, ??bb0F_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 035H,		00H,	05BH
$DGS	END_BLK, ??eb0F_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 035H
$DGS	END_BLK, ??eb0D_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 035H
$DGS	END_BLK, ??eb0C_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 035H
$DGS	END_BLK, ??eb06_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 03AH
$DGS	BEG_BLK, ??bb10_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 03CH,		00H,	00H
$DGS	END_BLK, ??eb10_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 046H
$DGS	END_BLK, ??eb04_int_iic_twl,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 047H
$DGS	END_FUN, ??ef_int_iic_twl,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 048H
$DGS	GLV_SYM, _IIC_twl_Init,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	069H,	00H,	00H
$DGS	BEG_FUN, ??bf_IIC_twl_Init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 09FH,		00H,	069H
$DGS	END_FUN, ??ef_IIC_twl_Init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 024H
$DGS	GLV_SYM, _IIC_twl_Stop,	U,	U,	01H,	026H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	06FH,	00H,	00H
$DGS	BEG_FUN, ??bf_IIC_twl_Stop,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 0C8H,		00H,	06FH
$DGS	END_FUN, ??ef_IIC_twl_Stop,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 04H
$DGS	GLV_SYM, _vreg_adrs,	U,	U,	0CH,	026H,	00H,	00H
$DGS	GLV_SYM, _pre_dat,	U,	U,	0CH,	026H,	00H,	00H
$DGS	GLV_SYM, _tot,		U,	U,	0DH,	026H,	00H,	00H
$DGS	GLV_SYM, _@SEGAX,	U,	U,	00H,	02H,	00H,	00H
$DGS	GLV_SYM, _adrs_table_twl_ext2int,	U,	U,	0CH,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _vreg_twl_read,	U,	U,	0CH,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _vreg_twl_write,	U,	U,	01H,	02H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	00H,	00H,	00H
$DGS	GLV_SYM, _@SEGDE,	U,	U,	00H,	02H,	00H,	00H
$DGS	GLV_SYM, _@RTARG0,	U,	U,	00H,	02H,	00H,	00H

	EXTRN	_@SEGAX
	EXTRN	_@SEGDE
	EXTRN	_@RTARG0
	EXTRN	_adrs_table_twl_ext2int
	EXTRN	_vreg_twl_read
	EXTRN	_vreg_twl_write
	PUBLIC	_vreg_adrs
	PUBLIC	_pre_dat
	PUBLIC	_tot
	PUBLIC	_int_iic_twl
	PUBLIC	_IIC_twl_Init
	PUBLIC	_IIC_twl_Stop

@@BITS	BSEG

@@CNST	CSEG	MIRRORP
_lpf_coeff:	DB	01H	; 1
	DB	02H	; 2
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	00H	; 0
	DB	0FEH	; 254
	DB	0FBH	; 251
	DB	0F7H	; 247
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0FAH	; 250
	DB	04H	; 4
	DB	012H	; 18
	DB	025H	; 37
	DB	038H	; 56
	DB	04DH	; 77
	DB	05FH	; 95
	DB	06EH	; 110
	DB	077H	; 119
	DB	07AH	; 122
	DB	077H	; 119
	DB	06EH	; 110
	DB	05FH	; 95
	DB	04DH	; 77
	DB	038H	; 56
	DB	025H	; 37
	DB	012H	; 18
	DB	04H	; 4
	DB	0FAH	; 250
	DB	0F3H	; 243
	DB	0F0H	; 240
	DB	0F0H	; 240
	DB	0F3H	; 243
	DB	0F7H	; 247
	DB	0FBH	; 251
	DB	0FEH	; 254
	DB	00H	; 0
	DB	02H	; 2
	DB	03H	; 3
	DB	03H	; 3
	DB	02H	; 2
	DB	02H	; 2
	DB	01H	; 1
	DB	(1)

@@R_INIT	CSEG	UNIT64KP

@@INIT	DSEG	BASEP

@@DATA	DSEG	BASEP
_vreg_adrs:	DS	(1)
_pre_dat:	DS	(1)
_tot:	DS	(2)

@@R_INIS	CSEG	UNIT64KP

@@INIS	DSEG	SADDRP

@@DATS	DSEG	SADDRP

@@CNSTL	CSEG	PAGE64KP

@@RLINIT	CSEG	UNIT64KP

@@INITL	DSEG	UNIT64KP

@@DATAL	DSEG	UNIT64KP

@@CALT	CSEG	CALLT0

; line     1 : #pragma sfr                     /* 特殊機能レジスタ使用 */
; line     2 : 
; line     3 : 
; line     4 : 
; line     5 : /*==============================================================
;              ==============*/
; line     6 : #include "incs.h"
; line     7 : #include "i2c_twl_defs.h"
; line     8 : 
; line     9 : 
; line    10 : extern u8 vreg_twl[];
; line    11 : 
; line    12 : #ifdef _MCU_BSR_
; line    13 : //#ifdef _MODEL_TS0_ || _MODEL_WM0_
; line    14 : 
; line    15 : // ワーキングモデルはI2Cが逆
; line    16 : #define ACKD       ACKD0
; line    17 : #define ACKE       ACKE0
; line    18 : #define COI        COI0
; line    19 : #define IICAEN     IICA0EN
; line    20 : #define IICRSV     IICRSV0
; line    21 : #define IICA       IICA0
; line    22 : #define IICAIF     IICAIF0
; line    23 : #define IICAMK     IICAMK0
; line    24 : #define IICAPR0    IICAPR00
; line    25 : #define IICAPR1    IICAPR10
; line    26 : #define IICCTL0    IICCTL00
; line    27 : #define IICE       IICE0
; line    28 : #define IICF       IICF0
; line    29 : #define IICS       IICS0
; line    30 : #define IICWH      IICWH0
; line    31 : #define IICWL      IICWL0
; line    32 : #define LREL       LREL0
; line    33 : #define SPD        SPD0
; line    34 : #define SPIE       SPIE0
; line    35 : #define STCEN      STCEN0
; line    36 : #define STD        STD0
; line    37 : #define SVA        SVA0
; line    38 : #define WREL       WREL0
; line    39 : #define WTIM       WTIM0
; line    40 : #define SMC        SMC0
; line    41 : 
; line    42 : #endif
; line    43 : 
; line    44 : #ifndef _MCU_BSR_
; line    45 : 
; line    46 : // ke3の時はダミー関数
; line    47 : void IIC_twl_Stop( void )
; line    48 : {
; line    49 : }
; line    50 : void IIC_twl_Init( void )
; line    51 : {
; line    52 : }
; line    53 : #else
; line    54 : 
; line    55 : 
; line    56 : /*==============================================================
;              ==============*/
; line    57 : u8      vreg_adrs;
; line    58 : u8      pre_dat;
; line    59 : 
; line    60 : 
; line    61 : u16     tot;
; line    62 : 
; line    63 : 
; line    64 : // 注！　↓はマクロなので、returnはメインループに戻ります。
; line    65 : #define wait_next {                                    \
; line    66 :     tot = 0;                                             \
; line    67 :   while( IICAIF != 1 ){                                \
; line    68 :     if( SPD ){                                         \
; line    69 :       LREL = 1;                                        \
; line    70 :       return;                                          \
; line    71 :     }                                                  \
; line    72 :     tot++;                                             \
; line    73 :     if( tot == 0 ){                                    \
; line    74 :       LREL = 1;                                        \
; line    75 :       return;                                          \
; line    76 :     }                                                  \
; line    77 :   }                                                    \
; line    78 : }
; line    79 : 
; line    80 : 
; line    81 : __interrupt void int_iic_twl(  )
; line    82 : {

@@BASE	CSEG	BASE
_int_iic_twl:
$DGL	1,21
	push	ax						;[INF] 1, 1
	push	bc						;[INF] 1, 1
	push	de						;[INF] 1, 1
	push	hl						;[INF] 1, 1
	mov	c,#0CH						;[INF] 2, 1
	dec	c						;[INF] 1, 1
	dec	c						;[INF] 1, 1
	movw	ax,_@SEGAX[c]					;[INF] 3, 1
	push	ax						;[INF] 1, 1
	bnz	$$-6						;[INF] 2, 4
	mov	a,ES						;[INF] 2, 1
	mov	x,a						;[INF] 1, 1
	mov	a,CS						;[INF] 2, 1
	push	ax						;[INF] 1, 1
	subw	sp,#06H						;[INF] 2, 1
	movw	hl,sp						;[INF] 3, 1
??bf_int_iic_twl:
; line    83 :     u8      temp;
; line    84 :     u16     tot;
; line    85 : 
; line    86 : //  WDT_Restart();
; line    87 :     // フラグ１回目    スレーブアドレス,R/W
; line    88 : /* COI != 1 なら、割り込みはいらない
; line    89 :   if( COI != 1 ){               // 被呼び出し？
; line    90 :     LREL = 1;                   // 呼ばれたのは他のID
; line    91 :     return;
; line    92 :   }else{
; line    93 :     ACKE0 = 1;                // 自動でackを返すようにする
; line    94 :     WREL = 1;                 // ウェイト解除して次のバイトを待つ
; line    95 :   }
; line    96 :   */
; line    97 :     WREL = 1;                   // ウェイト解除して次のバイトを待
;              つ
$DGL	0,16
	set1	!IICCTL00.5					;[INF] 4, 2
; line    98 :     wait_next;                  // １バイト受信完了を待つ
$DGL	0,17
??bb00_int_iic_twl:
	clrw	ax						;[INF] 1, 1
	movw	[hl+2],ax	; tot 				;[INF] 2, 1
?L0003:
	bt	IF1L.3,$?L0004					;[INF] 4, 5
??bb01_int_iic_twl:
	bf	IICS0.0,$?L0005					;[INF] 4, 5
??bb02_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	!?L0010						;[INF] 3, 3
??eb02_int_iic_twl:
?L0005:
	incw	[hl+2]	; tot 					;[INF] 3, 2
	clrw	ax						;[INF] 1, 1
	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
	bnz	$?L0003						;[INF] 2, 4
??bb03_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	!?L0010						;[INF] 3, 3
??eb03_int_iic_twl:
??eb01_int_iic_twl:
?L0004:
??eb00_int_iic_twl:
; line    99 : 
; line   100 :     // ２回目           R/W レジスタアドレス
; line   101 :     temp = IICA;
$DGL	0,20
	mov	a,IICA0						;[INF] 2, 1
	mov	[hl+5],a	; temp 				;[INF] 2, 1
; line   102 :     IICAIF = 0;
$DGL	0,21
	clr1	IF1L.3						;[INF] 3, 2
; line   103 :     WREL = 1;
$DGL	0,22
	set1	!IICCTL00.5					;[INF] 4, 2
; line   104 : 
; line   105 :     vreg_adrs = adrs_table_twl_ext2int( temp );
$DGL	0,24
	mov	a,[hl+5]	; temp 				;[INF] 2, 1
	shrw	ax,8						;[INF] 2, 1
	call	!_adrs_table_twl_ext2int			;[INF] 3, 3
	mov	a,c						;[INF] 1, 1
	mov	!_vreg_adrs,a					;[INF] 3, 1
; line   106 : 
; line   107 :     // ３回目
; line   108 :     // スタートコンディションか、データ受信完了フラグ待ち
; line   109 : 
; line   110 :     while( 1 )
?L0009:
; line   111 :     {
??bb04_int_iic_twl:
; line   112 :         u8 my_iics = IICS;
$DGL	0,31
	mov	a,IICS0						;[INF] 2, 1
	mov	[hl+1],a	; my_iics 			;[INF] 2, 1
; line   113 : 
; line   114 :         if( my_iics & 0x01 )    // SPD
$DGL	0,33
	and	a,#01H	; 1 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0011						;[INF] 2, 4
; line   115 :         {                       // 強制終了
??bb05_int_iic_twl:
; line   116 :             LREL = 1;
$DGL	0,35
	set1	!IICCTL00.6					;[INF] 4, 2
; line   117 :             return;
$DGL	0,36
	br	!?L0010						;[INF] 3, 3
??eb05_int_iic_twl:
; line   118 :         }
?L0011:
; line   119 :         else if( my_iics & 0x02 )  // ( STD && !SPD )
$DGL	0,38
	mov	a,[hl+1]	; my_iics 			;[INF] 2, 1
	and	a,#02H	; 2 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bz	$?L0013						;[INF] 2, 4
; line   120 :         {
??bb06_int_iic_twl:
; line   121 :             // 送信 // (スタートコンディション検出)
; line   122 :             pre_dat = vreg_twl_read( vreg_adrs );       // mcu内
;              部アドレスを渡す。一バイト目の準備 IICBに書き込むとウェイト解除
$DGL	0,41
	mov	x,!_vreg_adrs					;[INF] 3, 1
	clrb	a						;[INF] 1, 1
	call	!_vreg_twl_read					;[INF] 3, 3
	mov	a,c						;[INF] 1, 1
	mov	!_pre_dat,a					;[INF] 3, 1
; line   123 : 
; line   124 :             // 自局をRで呼ばれるのを待つ
; line   125 :             wait_next;
$DGL	0,44
??bb07_int_iic_twl:
	clrw	ax						;[INF] 1, 1
	movw	[hl+2],ax	; tot 				;[INF] 2, 1
?L0015:
	bt	IF1L.3,$?L0016					;[INF] 4, 5
??bb08_int_iic_twl:
	bf	IICS0.0,$?L0017					;[INF] 4, 5
??bb09_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	$?L0010						;[INF] 2, 3
??eb09_int_iic_twl:
?L0017:
	incw	[hl+2]	; tot 					;[INF] 3, 2
	clrw	ax						;[INF] 1, 1
	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
	bnz	$?L0015						;[INF] 2, 4
??bb0A_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	$?L0010						;[INF] 2, 3
??eb0A_int_iic_twl:
; line   126 :             IICAIF = 0;
$DGL	0,45
??eb08_int_iic_twl:
?L0016:
??eb07_int_iic_twl:
	clr1	IF1L.3						;[INF] 3, 2
; line   127 :             if( COI != 1 )
$DGL	0,46
	bt	IICS0.4,$?L0021					;[INF] 4, 5
; line   128 :             {                   // 被呼び出し？
??bb0B_int_iic_twl:
; line   129 :                 LREL = 1;       // 呼ばれたのは他のID（あれ？）
$DGL	0,48
	set1	!IICCTL00.6					;[INF] 4, 2
; line   130 :                 return;
$DGL	0,49
	br	$?L0010						;[INF] 2, 3
??eb0B_int_iic_twl:
; line   131 :             }
?L0021:
; line   132 :             IICA = pre_dat;     // データを送る。ウェイトも解除さ
;              れる。
$DGL	0,51
	mov	a,!_pre_dat					;[INF] 3, 1
	mov	IICA0,a						;[INF] 2, 1
; line   133 : 
; line   134 :             wait_next;
$DGL	0,53
??bb0C_int_iic_twl:
	clrw	ax						;[INF] 1, 1
	movw	[hl+2],ax	; tot 				;[INF] 2, 1
?L0023:
	bt	IF1L.3,$?L0024					;[INF] 4, 5
??bb0D_int_iic_twl:
	bf	IICS0.0,$?L0025					;[INF] 4, 5
??bb0E_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	$?L0010						;[INF] 2, 3
??eb0E_int_iic_twl:
?L0025:
	incw	[hl+2]	; tot 					;[INF] 3, 2
	clrw	ax						;[INF] 1, 1
	cmpw	ax,[hl+2]	; tot 				;[INF] 3, 1
	bnz	$?L0023						;[INF] 2, 4
??bb0F_int_iic_twl:
	set1	!IICCTL00.6					;[INF] 4, 2
	br	$?L0010						;[INF] 2, 3
??eb0F_int_iic_twl:
; line   135 :             // ４回目。(送信データ後の、ACK/NACK後)　どうしても発
;              生してしまう。
??eb0D_int_iic_twl:
?L0024:
??eb0C_int_iic_twl:
; line   136 :             IICAIF = 0;         // おしまい
$DGL	0,55
	clr1	IF1L.3						;[INF] 3, 2
; line   137 :             LREL = 1;
$DGL	0,56
	set1	!IICCTL00.6					;[INF] 4, 2
; line   138 :             return;
$DGL	0,57
	br	$?L0010						;[INF] 2, 3
??eb06_int_iic_twl:
; line   139 :         }
?L0013:
; line   140 :         else if( IICAIF && (( my_iics & 0x03 ) == 0 ))   // !STD
;               && !SPD )
$DGL	0,59
	bf	IF1L.3,$?L0029					;[INF] 4, 5
	mov	a,[hl+1]	; my_iics 			;[INF] 2, 1
	and	a,#03H	; 3 					;[INF] 2, 1
	cmp0	a						;[INF] 1, 1
	bnz	$?L0029						;[INF] 2, 4
; line   141 :         {
??bb10_int_iic_twl:
; line   142 :             // 受信 //
; line   143 :             IICAIF = 0;
$DGL	0,62
	clr1	IF1L.3						;[INF] 3, 2
; line   144 :             temp = IICA;
$DGL	0,63
	mov	a,IICA0						;[INF] 2, 1
	mov	[hl+5],a	; temp 				;[INF] 2, 1
; line   145 :             WREL = 1;
$DGL	0,64
	set1	!IICCTL00.5					;[INF] 4, 2
; line   146 : 
; line   147 :             // 通常アクセス(ライト) //
; line   148 :             LREL = 1;           // スタートコンディション待ちへ(
;              連続書き込み未対応のため)
$DGL	0,67
	set1	!IICCTL00.6					;[INF] 4, 2
; line   149 :             vreg_twl_write( vreg_adrs, temp );
$DGL	0,68
	mov	a,[hl+5]	; temp 				;[INF] 2, 1
	shrw	ax,8						;[INF] 2, 1
	push	ax						;[INF] 1, 1
	mov	x,!_vreg_adrs					;[INF] 3, 1
	call	!_vreg_twl_write				;[INF] 3, 3
	pop	ax						;[INF] 1, 1
; line   150 :             return;             // 受信おしまい //
$DGL	0,69
	br	$?L0010						;[INF] 2, 3
??eb10_int_iic_twl:
; line   151 :         }
?L0029:
??eb04_int_iic_twl:
; line   152 :     }
$DGL	0,71
	br	!?L0009						;[INF] 3, 3
?L0010:
; line   153 : }
$DGL	0,72
??ef_int_iic_twl:
	addw	sp,#06H						;[INF] 2, 1
	pop	ax						;[INF] 1, 1
	mov	CS,a						;[INF] 2, 1
	mov	a,x						;[INF] 1, 1
	mov	ES,a						;[INF] 2, 1
	movw	de,#_@SEGAX					;[INF] 3, 1
	mov	c,#06H						;[INF] 2, 1
	pop	ax						;[INF] 1, 1
	movw	[de],ax						;[INF] 1, 1
	incw	de						;[INF] 1, 1
	incw	de						;[INF] 1, 1
	dec	c						;[INF] 1, 1
	bnz	$$-5						;[INF] 2, 4
	pop	hl						;[INF] 1, 1
	pop	de						;[INF] 1, 1
	pop	bc						;[INF] 1, 1
	pop	ax						;[INF] 1, 1
	reti							;[INF] 2, 6
??ee_int_iic_twl:
; line   154 : 
; line   155 : 
; line   156 : 
; line   157 : /*****************************************************/
; line   158 : void IIC_twl_Init( void )
; line   159 : {

ROM_CODE	CSEG	BASE
_IIC_twl_Init:
$DGL	1,99
??bf_IIC_twl_Init:
; line   160 : 
; line   161 :     IICAEN = 1;
$DGL	0,3
	set1	!PER0.4						;[INF] 4, 2
; line   162 : 
; line   163 :     IICE = 0;                   /* IICA disable */
$DGL	0,5
	clr1	!IICCTL00.7					;[INF] 4, 2
; line   164 : 
; line   165 :     IICAMK = 1;                 /* INTIICA disable */
$DGL	0,7
	set1	MK1L.3						;[INF] 3, 2
; line   166 :     IICAIF = 0;                 /* clear INTIICA interrupt flag 
;              */
$DGL	0,8
	clr1	IF1L.3						;[INF] 3, 2
; line   167 : 
; line   168 :     IICAPR0 = 0;                /* set INTIICA high priority */
$DGL	0,10
	clr1	PR01L.3						;[INF] 3, 2
; line   169 :     IICAPR1 = 0;                /* set INTIICA high priority */
$DGL	0,11
	clr1	PR11L.3						;[INF] 3, 2
; line   170 :     P20 &= ~0x3;
$DGL	0,12
	mov	a,!P20						;[INF] 3, 1
	and	a,#0FCH	; 252 					;[INF] 2, 1
	mov	!P20,a						;[INF] 3, 1
; line   171 : 
; line   172 :     SVA = IIC_T_SLAVEADDRESS;
$DGL	0,14
	mov	!SVA0,#04AH	; 74 				;[INF] 4, 1
; line   173 :     IICF = 0x01;
$DGL	0,15
	oneb	!IICF0						;[INF] 3, 1
; line   174 : 
; line   175 :     STCEN = 1;                  // リスタートの許可
$DGL	0,17
	set1	IICF0.1						;[INF] 3, 2
; line   176 :     IICRSV = 1;                 // 通信予約をさせない:スレーブに
;              徹する
$DGL	0,18
	set1	IICF0.0						;[INF] 3, 2
; line   177 : 
; line   178 :     SPIE = 0;                   // ストップコンディションでの割り
;              込みを禁止
$DGL	0,20
	clr1	!IICCTL00.4					;[INF] 4, 2
; line   179 :     WTIM = 1;                   // 自動でACKを返した後clkをLに固
;              定する
$DGL	0,21
	set1	!IICCTL00.3					;[INF] 4, 2
; line   180 :     ACKE = 1;                   //  ダメCPUは無視して次の通信をは
;              じめるかもしれないんで早くclkを開放しないといけない
$DGL	0,22
	set1	!IICCTL00.2					;[INF] 4, 2
; line   181 : 
; line   182 :     IICWH = 5;
$DGL	0,24
	mov	!IICWH0,#05H	; 5 				;[INF] 4, 1
; line   183 :     IICWL = 10;                 // L期間の長さ（？）
$DGL	0,25
	mov	!IICWL0,#0AH	; 10 				;[INF] 4, 1
; line   184 : 
; line   185 :     SMC = 1;
$DGL	0,27
	set1	!IICCTL10.3					;[INF] 4, 2
; line   186 : 
; line   187 :     IICAMK = 0;                 // 割り込みを許可
$DGL	0,29
	clr1	MK1L.3						;[INF] 3, 2
; line   188 : 
; line   189 :     IICE = 1;
$DGL	0,31
	set1	!IICCTL00.7					;[INF] 4, 2
; line   190 : 
; line   191 :     PM20 &= ~0x3;               /* set clock pin for IICA */
$DGL	0,33
	mov	a,!PM20						;[INF] 3, 1
	and	a,#0FCH	; 252 					;[INF] 2, 1
	mov	!PM20,a						;[INF] 3, 1
; line   192 : 
; line   193 :     LREL = 1;
$DGL	0,35
	set1	!IICCTL00.6					;[INF] 4, 2
; line   194 : }
$DGL	0,36
??ef_IIC_twl_Init:
	ret							;[INF] 1, 6
??ee_IIC_twl_Init:
; line   195 : 
; line   196 : 
; line   197 : 
; line   198 : //**************************************************************
;              **************
; line   199 : void IIC_twl_Stop( void )
; line   200 : {
_IIC_twl_Stop:
$DGL	1,105
??bf_IIC_twl_Stop:
; line   201 :     IICE = 0;                   /* IICA disable */
$DGL	0,2
	clr1	!IICCTL00.7					;[INF] 4, 2
; line   202 :     IICAEN = 0;
$DGL	0,3
	clr1	!PER0.4						;[INF] 4, 2
; line   203 : }
$DGL	0,4
??ef_IIC_twl_Stop:
	ret							;[INF] 1, 6
??ee_IIC_twl_Stop:

@@CODEL	CSEG
	END


; *** Code Information ***
;
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\i2c_twl.c
;
; $FUNC int_iic_twl(82)
;	void=(void)
;	CODE SIZE= 279 bytes, CLOCK_SIZE= 232 clocks, STACK_SIZE= 34 bytes
;
; $CALL adrs_table_twl_ext2int(105)
;	bc=(int:ax)
;
; $CALL vreg_twl_read(122)
;	bc=(int:ax)
;
; $CALL vreg_twl_write(149)
;	void=(int:ax, int:[sp+4])
;
; $FUNC IIC_twl_Init(159)
;	void=(void)
;	CODE SIZE= 85 bytes, CLOCK_SIZE= 46 clocks, STACK_SIZE= 0 bytes
;
; $FUNC IIC_twl_Stop(200)
;	void=(void)
;	CODE SIZE= 9 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 0 bytes

; Target chip : uPD79F0104
; Device file : E1.00b