mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@6 013db118-44a6-b54f-8bf7-843cb86687b1
176 lines
4.2 KiB
C
176 lines
4.2 KiB
C
#ifndef __vreg_ctr__
|
||
#define __vreg_ctr__
|
||
|
||
|
||
#define REG_BITS_RTC_BLACKOUT 0b00000001
|
||
#define REG_BIT_MCU_FIRMBROKEN 0b10000000
|
||
|
||
#define REG_BIT_IRQ0_MCUSTATUS 0b01000000
|
||
|
||
|
||
// VREG_C_IRQ0
|
||
#define REG_BIT_VR_SNDVOL_CHANGE ( 1 << 7 )
|
||
#define REG_BIT_VR_3D_CHANGE ( 1 << 6 )
|
||
#define REG_BIT_SW_3D_CLICK ( 1 << 5 )
|
||
#define REG_BIT_SW_WIFI_CLICK ( 1 << 4 )
|
||
#define REG_BIT_SW_POW_HOLD ( 1 << 3 )
|
||
#define REG_BIT_SW_POW_CLICK ( 1 << 2 )
|
||
#define REG_BIT_SW_HOME_HOLD ( 1 << 1 )
|
||
#define REG_BIT_SW_HOME_CLICK ( 1 << 0 )
|
||
|
||
// VREG_C_IRQ1
|
||
#define REG_BIT_TWL_OFF_REQ ( 1 << 7 )
|
||
#define REG_BIT_TWL_RESET_REQ ( 1 << 6 )
|
||
#define REG_BIT_WDT_DET ( 1 << 5 )
|
||
#define REG_BIT_ACC_DAT_RDY ( 1 << 4 )
|
||
#define REG_BIT_ACC_ACK ( 1 << 3 )
|
||
#define REG_BIT_RTC_ALARM ( 1 << 2 )
|
||
#define REG_BIT_BT_REMAIN ( 1 << 1 )
|
||
#define REG_BIT_STAT_CHANGE ( 1 << 0 )
|
||
|
||
// VREG_C_STATUS,
|
||
#define REG_BIT_BATT_CHARGE_ERR ( 1 << 5 )
|
||
#define REG_BIT_BATT_CHARGE ( 1 << 4 )
|
||
#define REG_BIT_POW_SUPPLY ( 1 << 3 )
|
||
#define REG_BIT_EXT_OPT_LOCK ( 1 << 2 )
|
||
#define REG_BIT_SHELL_CLOSE ( 1 << 1 )
|
||
#define REG_BIT_BL ( 1 << 0 )
|
||
|
||
|
||
// VREG_C_COMMAND0
|
||
#define REG_BIT_FCRAM_RESET_REQ ( 1 << 3 )
|
||
#define REG_BIT_RESET2_REQ ( 1 << 2 )
|
||
#define REG_BIT_RESET1_REQ ( 1 << 1 )
|
||
#define REG_BIT_OFF_REQ ( 1 << 0 )
|
||
|
||
// VREG_C_COMMAND1
|
||
#define REG_BIT_SEND_TWL_BATT_EMPTY ( 1 << 4 )
|
||
#define REG_BIT_SEND_TWL_BATT_LOW ( 1 << 3 )
|
||
#define REG_BIT_SEND_TWL_OFF_REQ ( 1 << 2 )
|
||
#define REG_BIT_SEND_TWL_RESET_REQ ( 1 << 1 )
|
||
#define REG_BIT_SEND_TWL_PWSW_DET ( 1 << 0 )
|
||
|
||
|
||
// VREG_C_WIFI_LED
|
||
#define REG_BIT_WIFI_BLINK_ENA ( 1 << 1 )
|
||
#define REG_BIT_WIFI_ON ( 1 << 0 )
|
||
|
||
|
||
/*
|
||
ƒeƒ“ƒvƒŒ
|
||
#define REG_BIT_ ( 1 << 7 )
|
||
#define REG_BIT_ ( 1 << 6 )
|
||
#define REG_BIT_ ( 1 << 5 )
|
||
#define REG_BIT_ ( 1 << 4 )
|
||
#define REG_BIT_ ( 1 << 3 )
|
||
#define REG_BIT_ ( 1 << 2 )
|
||
#define REG_BIT_ ( 1 << 1 )
|
||
#define REG_BIT_ ( 1 << 0 )
|
||
*/
|
||
|
||
|
||
|
||
/*============================================================================*/
|
||
extern u8 vreg_ctr[];
|
||
|
||
/*============================================================================*/
|
||
enum VREG_C{ // –¢’è‹`ƒAƒhƒŒƒX‚Ö<E2809A>‘‚«<E2809A>ž‚ñ‚¾<E2809A>Û‚Ì“®<E2809C>ì‚Í•s’è
|
||
VREG_C_IRQ0,
|
||
VREG_C_IRQ1,
|
||
|
||
VREG_C_STATUS,
|
||
|
||
VREG_C_IRQ_MASK0,
|
||
VREG_C_IRQ_MASK1,
|
||
VREG_C_RESERVED0,
|
||
|
||
VREG_C_BT_REMAIN,
|
||
VREG_C_SND_VOL,
|
||
VREG_C_3D_DEPTH,
|
||
|
||
VREG_C_COMMAND0,
|
||
VREG_C_COMMAND1,
|
||
|
||
VREG_C_LED_BRIGHT,
|
||
VREG_C_LED_POW_ILUMI,
|
||
|
||
VREG_C_WIFI_LED,
|
||
|
||
VREG_C_CAM_LED,
|
||
|
||
VREG_C_MCU_VER_MAJOR,
|
||
VREG_C_MCU_VER_MINOR,
|
||
VREG_C_MCU_STATUS,
|
||
|
||
//VREG_C_PM_INFO,
|
||
//VREG_C_BT_INFO,
|
||
VREG_C_VCOM_T,
|
||
VREG_C_VCOM_B,
|
||
// VREG_C_VCS_T,
|
||
// VREG_C_VCS_B,
|
||
VREG_C_RESERVED3,
|
||
VREG_C_RESERVED4,
|
||
|
||
VREG_C_BT_TEMP,
|
||
|
||
VREG_C_RESERVED1,
|
||
|
||
VREG_C_RTC_SEC,
|
||
VREG_C_RTC_MIN,
|
||
VREG_C_RTC_HOUR,
|
||
VREG_C_RTC_YOBI,
|
||
VREG_C_RTC_DAY,
|
||
VREG_C_RTC_MONTH,
|
||
VREG_C_RTC_YEAR,
|
||
VREG_C_RESERVED2,
|
||
VREG_C_RTC_ALARM_MIN,
|
||
VREG_C_RTC_ALARM_HOUR,
|
||
VREG_C_RTC_ALARM_DAY,
|
||
VREG_C_RTC_ALARM_MONTH,
|
||
VREG_C_RTC_ALARM_YEAR,
|
||
VREG_C_RTC_COMP,
|
||
|
||
VREG_C_ACC_CONFIG_HOSU,
|
||
VREG_C_ACC_CONFIG,
|
||
VREG_C_ACC_R_ADRS,
|
||
// VREG_C_ACC_R_BUF,
|
||
VREG_C_ACC_W_ADRS,
|
||
VREG_C_ACC_W_BUF,
|
||
|
||
VREG_C_ACC_HOSU_L,
|
||
VREG_C_ACC_HOSU_M,
|
||
VREG_C_ACC_HOSU_H,
|
||
|
||
VREG_C_ACC_XL,
|
||
VREG_C_ACC_XH,
|
||
VREG_C_ACC_YL,
|
||
VREG_C_ACC_YH,
|
||
VREG_C_ACC_ZL,
|
||
VREG_C_ACC_ZH,
|
||
|
||
VREG_C_DIAG,
|
||
|
||
VREG_C_FREE0,
|
||
VREG_C_FREE1,
|
||
VREG_C_FREE2,
|
||
VREG_C_FREE3,
|
||
VREG_C_DBG0,
|
||
VREG_C_DBG1,
|
||
VREG_C_DBG2,
|
||
VREG_C_DBG3,
|
||
|
||
VREG_C_ENDMARK_
|
||
};
|
||
|
||
|
||
/*============================================================================*/
|
||
void vreg_ctr_init();
|
||
void vreg_ctr_write( u8 adrs, u8 data );
|
||
u8 vreg_ctr_read( u8 phy_adrs );
|
||
void vreg_ctr_after_read( u8 adrs );
|
||
|
||
void vreg_c_iic_release();
|
||
|
||
|
||
#endif
|