mirror of
https://github.com/rvtr/ctr_firmware.git
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441ab5b993
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@188 b871894f-2f95-9b40-918c-086798483c85
282 lines
9.5 KiB
C
282 lines
9.5 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrBrom - library - init
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File: crt0_app.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/os.h>
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#define STUPi_HW_DTCM |Image$$DTCM$$Base|
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void _start(void);
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/*---------------------------------------------------------------------------*
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Name: _start
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Description: Start up
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Arguments: None
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Returns: None.
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*---------------------------------------------------------------------------*/
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asm void _start( void )
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PRESERVE8
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INASM_EXTERN( STUPi_HW_DTCM )
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INASM_EXTERN( BromSpMain )
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INASM_EXTERN( main )
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//---- initialize stack pointer
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// SVC mode
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mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr sp, =HW_BROM_SVC_STACK_END
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// IRQ mode
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mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr r0, =HW_BROM_IRQ_STACK_END
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mov sp, r0
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// System mode
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mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
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msr cpsr_fsxc, r0
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ldr r0, =HW_BROM_SYS_STACK_END
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mov sp, r0
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//---- initialize cp15
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bl i_stupInitCP15
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//---- clear wram
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// DTCM (16KB)
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mov r0, #0
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ldr r1, =STUPi_HW_DTCM
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mov r2, #HW_DTCM_SIZE
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bl i_stupCpuClear32
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// 64B
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mov r0, #0
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ldr r1, =HW_PRV_WRAM_SYSRV
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ldr r2, =HW_EXCP_VENEER_BUF
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sub r2, r2, r1
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bl i_stupCpuClear32
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ldr r1, =HW_EXCP_VENEER_BUF_END
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ldr r2, =HW_PRV_WRAM_SYSRV_END
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sub r2, r2, r1
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bl i_stupCpuClear32
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//---- lnitialize sections
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bl stupInitSections
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//---- start (to 16bit code)
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ldr r1, =BromSpMain
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adr lr, terminate
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bx r1
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terminate
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b terminate
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}
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//-----------------------------------------------------------------------
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// <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>R<EFBFBD>v<EFBFBD><76><EFBFBD>Z<EFBFBD>b<EFBFBD>T <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//-----------------------------------------------------------------------
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asm void i_stupInitCP15(void)
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{
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// <20>v<EFBFBD><76><EFBFBD>e<EFBFBD>N<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>j<EFBFBD>b<EFBFBD>g/<2F>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>/TCM <20>f<EFBFBD>B<EFBFBD>Z<EFBFBD>[<5B>u<EFBFBD><75>
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \
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| HW_C1_LD_INTERWORK_DISABLE \
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| HW_C1_PROTECT_UNIT_ENABLE
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#ifdef SDK_MG20EMU
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bic r1, r1, #HW_C1_ITCM_ENABLE
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#endif // SDK_MG20EMU
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bic r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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// <20>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // <20><><EFBFBD>߃L<DF83><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>
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mcr p15, 0, r0, c7, c6, 0 // <20>f<EFBFBD>[<5B>^<5E>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56>
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// <20><><EFBFBD>C<EFBFBD>g<EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@ <20>G<EFBFBD><47><EFBFBD>v<EFBFBD>e<EFBFBD>B<EFBFBD>҂<EFBFBD>
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mcr p15, 0, r0, c7, c10, 4
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/*
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; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA
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; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW
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; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW
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; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW
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; Region 3: PRV_WRAM_SYSRV:Base = 0x08000000, Size = 4KB, I:Cach Buf / D:Cach Buf, I:RO / D:RW
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; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW
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; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW
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; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO
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; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW
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*/
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#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE)
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#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0
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#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7))
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#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28))
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#define NA 0
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#define RW 1
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#define RO 5
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//
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//
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//---- <20><><EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB )
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SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB )
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//---- I/O<><4F><EFBFBD>W<EFBFBD>X<EFBFBD>^ & VRAM & AXI-WRAM
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SET_PROTECTION_A( c1, HW_IOREG, 256MB )
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SET_PROTECTION_B( c1, HW_IOREG, 256MB )
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//---- PRV_WRAM
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SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB )
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SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB )
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//---- PRV_WRAM_SYSRV
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#ifndef SDK_MG20EMU
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SET_PROTECTION_A( c3, HW_PRV_WRAM_SYSRV, 4KB )
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SET_PROTECTION_B( c3, HW_PRV_WRAM_SYSRV, 4KB )
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#else // SDK_MG20EMU
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SET_PROTECTION_A( c3, HW_MG20IOP_REG, 1MB )
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SET_PROTECTION_B( c3, HW_MG20IOP_REG, 1MB )
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#endif // SDK_MG20EMU
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//---- <20>f<EFBFBD>[<5B>^ TCM
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ldr r0, =STUPi_HW_DTCM
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orr r0, r0, #HW_C6_PR_16KB
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orr r0, r0, #HW_C6_PR_ENABLE
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SET_PROTECTION_B( c4, HW_DTCM, 16KB )
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//---- <20><><EFBFBD><EFBFBD> TCM
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// <20>f<EFBFBD>[<5B>^ TCM <20><><EFBFBD><EFBFBD><EFBFBD>D<EFBFBD>悪<EFBFBD><E682AA><EFBFBD><EFBFBD>
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SET_PROTECTION_A( c5, HW_ITCM, 32KB )
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SET_PROTECTION_B( c5, HW_ITCM, 32KB )
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//---- BIOS
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SET_PROTECTION_A( c6, HW_BIOS, 64KB )
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SET_PROTECTION_B( c6, HW_BIOS, 64KB )
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//---- SHARED CPU <20>ԒʐM<CA90><4D><EFBFBD>[<5B>N<EFBFBD>̈<EFBFBD>
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SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB )
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SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB )
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//
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// <20><><EFBFBD>߂s<DF82>b<EFBFBD>l <20>ݒ<EFBFBD>
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//
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mov r0, #HW_C9_TCMR_128MB
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mcr p15, 0, r0, c9, c1, 1
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//
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// <20>f<EFBFBD>[<5B>^<5E>s<EFBFBD>b<EFBFBD>l <20>ݒ<EFBFBD>
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//
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ldr r0, =STUPi_HW_DTCM
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orr r0, r0, #HW_C9_TCMR_16KB
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mcr p15, 0, r0, c9, c1, 0
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//
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// <20><><EFBFBD>߃L<DF83><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56> <20>C<EFBFBD>l<EFBFBD>[<5B>u<EFBFBD><75> (<28><><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ݒ<EFBFBD>)
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// 6: BIOS
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//
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mov r0, #REGION_BIT(0,0,0,0,0,0,1,0)
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mcr p15, 0, r0, c2, c0, 1
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//
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// <20>f<EFBFBD>[<5B>^<5E>L<EFBFBD><4C><EFBFBD>b<EFBFBD>V<EFBFBD><56> <20>C<EFBFBD>l<EFBFBD>[<5B>u<EFBFBD><75> (<28><><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ݒ<EFBFBD>)
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// 0: HW_MAIN_MEM
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// 2: PRV_WRAM
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// 6: BIOS
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//
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mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
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mcr p15, 0, r0, c2, c0, 0
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//
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// <20><><EFBFBD>C<EFBFBD>g<EFBFBD>o<EFBFBD>b<EFBFBD>t<EFBFBD>@ <20>C<EFBFBD>l<EFBFBD>[<5B>u<EFBFBD><75>(<28><><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ݒ<EFBFBD>)
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// 0: HW_MAIN_MEM
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// 2: PRV_WRAM
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// 6: BIOS
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//
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mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
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mcr p15, 0, r0, c3, c0, 0
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//
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// <20><><EFBFBD>߃A<DF83>N<EFBFBD>Z<EFBFBD>X<EFBFBD><58><EFBFBD><EFBFBD> (<28><><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ݒ<EFBFBD>)
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// MAIN_MEM : NA
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// IO_AXIRAM : NA
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// PRV_WRAM : NA
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// PRV_WRAM_SYSRV: RO
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// DTCM : NA
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// ITCM : RO
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// BIOS : RO
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// SHARED : NA
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//
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#ifndef SDK_MG20EMU
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ldr r0, =REGION_ACC(NA,NA,NA,RO,NA,RO,RO,NA)
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#else // SDK_MG20EMU
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ldr r0, =REGION_ACC(NA,NA,RO,NA,NA,RO,RO,NA)
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#endif // SDK_MG20EMU
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mcr p15, 0, r0, c5, c0, 3
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//
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// <20>f<EFBFBD>[<5B>^<5E>A<EFBFBD>N<EFBFBD>Z<EFBFBD>X<EFBFBD><58><EFBFBD>i<C281><69><EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD>ݒ<EFBFBD><DD92>j
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// MAIN_MEM : RW
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// IO_AXIRAM : RW
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// PRV_WRAM : RW
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// PRV_WRAM_SYSRV: RW
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// DTCM : RW
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// ITCM : RW
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// BIOS : RO
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// SHARED : RW
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//
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#ifdef BROM_ENABLE_BOOTROM_WRITE
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ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RW,RW)
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#else // BROM_ENABLE_BOOTROM_WRITE
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ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RO,RW)
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#endif // BROM_ENABLE_BOOTROM_WRITE
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mcr p15, 0, r0, c5, c0, 2
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//
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// <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>R<EFBFBD>v<EFBFBD><76><EFBFBD>Z<EFBFBD>b<EFBFBD>T <20>}<7D>X<EFBFBD>^<5E>[<5B>ݒ<EFBFBD>
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//
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mrc p15, 0, r0, c1, c0, 0
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ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \
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| HW_C1_PROTECT_UNIT_ENABLE
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orr r0, r0, r1
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#ifdef SDK_MG20EMU
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bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER
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#endif // SDK_MG20EMU
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mcr p15, 0, r0, c1, c0, 0
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bx lr
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LTORG
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EXPORT i_stupInitCP15_End
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i_stupInitCP15_End
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}
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#undef BROM_TARGET_BROM
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#include <./crt0_misc_sp.c>
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