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アプリケーションビルド対応。

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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@188 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2009-01-20 10:10:39 +00:00
parent 91a38a6dca
commit 441ab5b993
14 changed files with 984 additions and 214 deletions
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1
trunk/bootrom/build/Makefile
View File

@ -24,6 +24,7 @@ SUBDIRS = \
$(CTRFIRM_ROOT)/build/buildsetup \
libraries \
bootrom \
tests \
#----------------------------------------------------------------------------

4
trunk/bootrom/build/libraries/init/ARM11/Makefile
View File

@ -29,8 +29,8 @@ BROM_PROC = ARM11
SRCDIR = ../common .
SRCS = crt0.c crt0_secure.c crt0_scat.c crt0_excp.c # crt0_app.c
TARGET_OBJ = crt0.o crt0_secure.o crt0_scat.o crt0_excp.o # crt0_app.o
SRCS = crt0.c crt0_secure.c crt0_scat.c crt0_excp.c crt0_app.c
TARGET_OBJ = crt0.o crt0_secure.o crt0_scat.o crt0_excp.o crt0_app.o
#----------------------------------------------------------------------------

387
trunk/bootrom/build/libraries/init/ARM11/crt0_app.c
View File

@ -18,7 +18,8 @@
#include <brom/os.h>
//#include <brom/mi.h>
void _start(void);
void _start(void);
void stupInitMMUTable( void );
/*---------------------------------------------------------------------------*
Name: _start
@ -33,69 +34,41 @@ asm void _start( void )
{
PRESERVE8
b stupStartHandlerVeneer // don't change for NULL access compatibility
stupStartHandlerVeneer
b i_stupStartHandler
}
/*---------------------------------------------------------------------------*
Name: i_stupStartHandler
Description: start handler
Arguments: None
Returns: None.
*---------------------------------------------------------------------------*/
asm void i_stupStartHandler( void )
{
INASM_EXTERN( BromSpMain )
INASM_EXTERN( BromMain )
INASM_EXTERN( main )
#ifndef BROM_ENABLE_BOOTROM_WRITE
ldr r3, =REG_ROM_ADDR
ldrb r1, [r3]
bic r1, #REG_SCFG_ROM_WE_MASK
strb r1, [r3]
#endif // BROM_ENABLE_BOOTROM_WRITE
//---- set IME = 0
// ( use that LSB of HW_REG_BASE equal to 0 )
mov r12, #HW_REG_BASE
str r12, [r12, #REG_IME_OFFSET]
// init BROM prot
ldr r3, =REG_PROT_ADDR
ldr r1, =4*8 // 0x1204
strh r1, [r3]
//---- initialize stack pointer
// SVC mode
mov r0, #HW_PSR_SVC_MODE
msr cpsr_c, r0
ldr sp, =HW_PRV_WRAM_SVC_STACK_END
mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr sp, =HW_BROM_SVC_STACK_END
// IRQ mode
mov r0, #HW_PSR_IRQ_MODE
msr cpsr_c, r0
ldr r0, =HW_PRV_WRAM_IRQ_STACK_END
mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_IRQ_STACK_END
mov sp, r0
// System mode
ldr r1, =HW_IRQ_STACK_SIZE
sub r1, r0, r1
mov r0, #HW_PSR_SYS_MODE
msr cpsr_csfx, r0
sub sp, r1, #4 // 4byte for stack check code
mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_SYS_STACK_END
mov sp, r0
//---- disable cp15
bl stupDisableCP15
//---- initialize MMU
bl stupInitMMU
//---- enable cp15
bl stupEnableCP15
//---- lnitialize sections
bl stupInitSections
//---- start (to 16bit code)
ldr r1, =BromSpMain
ldr r1, =BromMain
adr lr, terminate
bx r1
@ -104,6 +77,316 @@ terminate
b terminate
}
#undef BROM_TARGET_BROM
#include <./crt0_misc_sp.c>
/*---------------------------------------------------------------------------*
Name: stupInitMMU
Description: Initialize MMU
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
asm void stupInitMMU( void )
{
stmfd sp!, {r4, lr} // stack requires 8byte alignment
// Invalidate ITLB DTLB
mov r0, #0
mcr p15, 0, r0, c8, c5, 0
mcr p15, 0, r0, c8, c6, 0
ldr r0, =HW_BROM_MMU_T1
mov r2, #HW_C2_V5_T1_BOUNBARY_16KB
// MMU L1 Table Base
ldr r1, =HW_C2_0_T1_BASE_MASK_MIN
mov r1, r1, ASR r2
and r1 ,r1, r0
orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
| HW_C2_WALK_ON_SHARED_MEM
mcr p15, 0, r1, c2, c0, 0
ldr r1, =HW_C2_1_T1_BASE_MASK
and r1 ,r1, r0
orr r1, r1, #(HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT) \
| HW_C2_WALK_ON_SHARED_MEM
mcr p15, 0, r1, c2, c0, 1
// MMU L1 Table Boundary
mcr p15, 0, r2, c2, c0, 2
// Domain Access Permission
#if 1 // miya
ldr r1, =0x00000001
#else
ldr r1, = HW_C3_DOMAIN_PACK( \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_CLIENT, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER, \
HW_C3_DM_AP_MANAGER \
)
#endif
mcr p15, 0, r1, c3, c0, 0
// VFP Access Permission
ldr r1, =HW_C1_VFP_AP_PACK( \
HW_C1_AP_PRIV, HW_C1_AP_PRIV )
mcr p15, 0, r1, c1, c0, 2
// Initialize MMU Table
bl __cpp(stupInitMMUTable)
ldmfd sp!, {r4, pc} // stack requires 8byte alignment
}
/*---------------------------------------------------------------------------*
Name: stupInitMMUTable
Description: Initialize MMU Table
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
void stupInitMMUTable( void )
{
u32* t1Base = (u32* )HW_BROM_MMU_T1;
u32* t2Base = (u32* )HW_BROM_MMU_T2;
u32* table;
u32 paddr = (u32 )NULL;
// Initialize as Access Prohibition
table = t1Base;
for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; )
{
*table++ = HW_MMU6_T1_SEC_PACK(
paddr,
HW_MMU6_APX_NA,
HW_MMU6_T1_RGT_STRONG_ORDER,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN,
0);
}
table = t2Base;
for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T2_END; )
{
*table++ = HW_MMU6_T2_SP_PACK(
paddr,
HW_MMU6_T2_APX_NA,
HW_MMU6_T2_LP_RGT_STRONG_ORDER,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
HW_MMU6_T2_SP_XN);
}
// Main Memory Region (128MB cached)
paddr = HW_MAIN_MEM;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
while ( paddr < HW_MAIN_MEM_END )
{
*table++ = HW_MMU6_T1_SUSEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN
);
paddr += HW_MMU6_T1_SEC_SIZE;
}
#ifndef SDK_MG20EMU
// MG20には拡張メインメモリは無い
while ( paddr < HW_MAIN_MEM_EX_END )
{
*table++ = HW_MMU6_T1_SUSEC_PACK(
paddr,
HW_MMU6_T1_APX_ALL,
HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN
);
paddr += HW_MMU6_T1_SEC_SIZE;
}
#else // SDK_MG20EMU
// for AXI-WRAM & DSP-WRAM Emulation
paddr = HW_MAIN_MEM_END - HW_MMU6_T1_SUSEC_SIZE;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
while ( paddr < HW_MAIN_MEM_END )
{
*table++ = HW_MMU6_T1_SEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN,
0);
paddr += HW_MMU6_T1_SEC_SIZE;
}
#endif // SDK_MG20EMU
// IO Registers Region (16MB)
paddr = HW_IOREG;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
while ( paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE )
{
*table++ = HW_MMU6_T1_SUSEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_SHARED_DEV,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN
);
paddr += HW_MMU6_T1_SEC_SIZE;
}
// MPCore Registers Region (1MB)
paddr = HW_MPCORE_REG;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
*table++ = HW_MMU6_T1_SEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_NSHARED_DEV,
HW_MMU6_T1_GLOBAL,
FALSE,
HW_MMU6_T1_XN,
0);
// VRAM Region (4MB cached)
paddr = HW_VRAM;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
while ( paddr < HW_VRAM_END )
{
*table++ = HW_MMU6_T1_SEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL,
HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN,
0);
paddr += HW_MMU6_T1_SEC_SIZE;
}
#ifdef SDK_NE1EMU
// NE1-TB DDR2 Registers Region (1MB)
paddr = HW_NE1DDR2_REG;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
*table++ = HW_MMU6_T1_SEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_NSHARED_DEV,
HW_MMU6_T1_GLOBAL,
FALSE,
HW_MMU6_T1_XN,
0);
#endif // SDK_NE1EMU
// AXI-WRAM & DSP-WRAM Region (1MB cached & uncached)
paddr = HW_DSP_WRAM;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
*table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 );
// T2 for Page
table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE];
while ( paddr < MATH_ROUNDDOWN(HW_BROM_MMU_TBL, HW_MMU6_T2_LP_SIZE) )
{
*table++ = HW_MMU6_T2_LP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1C_WB_WA,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
HW_MMU6_T2_LP_XN);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
}
while ( paddr < HW_BROM_MMU_TBL )
{
*table++ = HW_MMU6_T2_SP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_SP_RGT_L1C_WB_WA,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
HW_MMU6_T2_SP_XN);
paddr += HW_MMU6_T2_SP_SIZE;
}
// HW_BROM_MMU_TBL
while ( paddr < HW_BROM_MMU_TBL_END )
{
*table++ = HW_MMU6_T2_SP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_SP_RGT_SHARED_DEV,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
HW_MMU6_T2_SP_XN);
paddr += HW_MMU6_T2_SP_SIZE;
}
// HW_AXI_WRAM_SHARED
while ( paddr < HW_AXI_WRAM_SHARED_END )
{
*table++ = HW_MMU6_T2_SP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_SP_RGT_SHARED_DEV,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
FALSE); // for exception veneer
paddr += HW_MMU6_T2_SP_SIZE;
}
// Coarse page is 1KB boundary
t2Base += MATH_ROUNDUP((HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE)/HW_MMU6_T2_SP_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
// BROM Region (64KBx2 cached)
paddr = HW_BROM_IMG;
table = &t1Base[paddr/HW_MMU6_T1_SEC_SIZE];
*table = HW_MMU6_T1_COURSE_PACK( (u32)t2Base, 0 );
// T2 for Page
table = &t2Base[paddr%HW_MMU6_T1_SEC_SIZE/HW_MMU6_T2_LP_ALIAS_SIZE];
while ( paddr != HW_BROM_END )
{
*table++ = HW_MMU6_T2_LP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1C_WB_WA,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
FALSE);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
}
// Coarse page is 1KB boundary
t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2/HW_MMU6_T2_LP_ALIAS_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
}
#undef BROM_TARGET_BROM
#include <./crt0_misc.c>

111
trunk/bootrom/build/libraries/init/ARM11/crt0_misc.c
View File

@ -56,6 +56,117 @@ void i_stupInitDDR2( void )
#endif // SDK_NE1EMU
/*---------------------------------------------------------------------------*
Name: stupDisableCP15
Description: Disable Coprocessor 15
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
asm void stupDisableCP15( void )
{
// MMU/Caches/BranchPrediction disable
mrc p15, 0, r0, c1, c0, 0
ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
| HW_C1_FORCE_AP_BIT \
| HW_C1_TEX_CB_REMAP \
| HW_C1_EXCEPT_BIG_ENDIAN \
| HW_C1_BR_PREDICT_ENABLE \
| HW_C1_LD_INTERWORK_DISABLE \
| HW_C1_UNALIGN_ACCESS_ENABLE \
| HW_C1_ALIGN_FAULT_ENABLE \
| HW_C1_ROM_PROTECT_ENABLE \
| HW_C1_MMU_PROTECT_ENABLE \
| HW_C1_MMU_ENABLE
#ifndef SDK_MG20EMU
orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
#endif // SDK_MG20EMU
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_SMP_MODE \
| HW_C1_EXCLUSIVE_L1C_L2C \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \
| HW_C1_RETURN_STACK_ENABLE
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 1
// Invalidate Caches
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // Inst Cache
mcr p15, 0, r0, c7, c6, 0 // Data cache
// Wait for write buffer empty
mcr p15, 0, r0, c7, c10, 4
bx lr
}
/*---------------------------------------------------------------------------*
Name: stupEnableCP15
Description: Enable Coprocessor 15
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
asm void stupEnableCP15( void )
{
//
// Auxiliary Control
//
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_AMP_MODE \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \
| HW_C1_RETURN_STACK_ENABLE
orr r0, r0, r1
mcr p15, 0, r0, c1, c0, 1
//
// Master Control
//
mrc p15, 0, r0, c1, c0, 0
ldr r1, = 0 \
| HW_C1_EXCEPT_LITTLE_ENDIAN \
| HW_C1_UNALIGN_ACCESS_ENABLE \
| HW_C1_BR_PREDICT_ENABLE \
| HW_C1_MMU_V6 \
| HW_C1_IC_ENABLE \
| HW_C1_DC_ENABLE \
| HW_C1_MMU_ENABLE
#ifdef SDK_MG20EMU
orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
#endif // SDK_MG20EMU
orr r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
// Invalidate Caches
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // Inst Cache
mcr p15, 0, r0, c7, c6, 0 // Data cache
// Wait for write buffer empty
mcr p15, 0, r0, c7, c10, 4
bx lr
}
/*---------------------------------------------------------------------------*
Name: __user_initial_stackheap

113
trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
View File

@ -18,8 +18,6 @@
#include <brom/os.h>
#define STUPi_HW_DTCM |Image$$DTCM$$Base|
void stupInitMMUTable( void );
@ -101,117 +99,6 @@ terminate
b terminate
}
/*---------------------------------------------------------------------------*
Name: stupDisableCP15
Description: Disable Coprocessor 15
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
asm void stupDisableCP15( void )
{
// MMU/Caches/BranchPrediction disable
mrc p15, 0, r0, c1, c0, 0
ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
| HW_C1_FORCE_AP_BIT \
| HW_C1_TEX_CB_REMAP \
| HW_C1_EXCEPT_BIG_ENDIAN \
| HW_C1_BR_PREDICT_ENABLE \
| HW_C1_LD_INTERWORK_DISABLE \
| HW_C1_UNALIGN_ACCESS_ENABLE \
| HW_C1_ALIGN_FAULT_ENABLE \
| HW_C1_ROM_PROTECT_ENABLE \
| HW_C1_MMU_PROTECT_ENABLE \
| HW_C1_MMU_ENABLE
#ifndef SDK_MG20EMU
orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
#endif // SDK_MG20EMU
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_SMP_MODE \
| HW_C1_EXCLUSIVE_L1C_L2C \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \
| HW_C1_RETURN_STACK_ENABLE
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 1
// Invalidate Caches
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // Inst Cache
mcr p15, 0, r0, c7, c6, 0 // Data cache
// Wait for write buffer empty
mcr p15, 0, r0, c7, c10, 4
bx lr
}
/*---------------------------------------------------------------------------*
Name: stupEnableCP15
Description: Enable Coprocessor 15
Arguments: None
Returns: None
*---------------------------------------------------------------------------*/
asm void stupEnableCP15( void )
{
//
// Auxiliary Control
//
mrc p15, 0, r0, c1, c0, 1
ldr r1, =HW_C1_AMP_MODE \
| HW_C1_BR_FOLDING_ENABLE \
| HW_C1_SBR_PREDICT_ENABLE \
| HW_C1_DBR_PREDICT_ENABLE \
| HW_C1_RETURN_STACK_ENABLE
orr r0, r0, r1
mcr p15, 0, r0, c1, c0, 1
//
// Master Control
//
mrc p15, 0, r0, c1, c0, 0
ldr r1, = 0 \
| HW_C1_EXCEPT_LITTLE_ENDIAN \
| HW_C1_UNALIGN_ACCESS_ENABLE \
| HW_C1_BR_PREDICT_ENABLE \
| HW_C1_MMU_V6 \
| HW_C1_IC_ENABLE \
| HW_C1_DC_ENABLE \
| HW_C1_MMU_ENABLE
#ifdef SDK_MG20EMU
orr r1, r1, #HW_C1_EXCEPT_VEC_UPPER
#endif // SDK_MG20EMU
orr r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
// Invalidate Caches
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // Inst Cache
mcr p15, 0, r0, c7, c6, 0 // Data cache
// Wait for write buffer empty
mcr p15, 0, r0, c7, c10, 4
bx lr
}
/*---------------------------------------------------------------------------*
Name: stupInitMMU

4
trunk/bootrom/build/libraries/init/ARM9/Makefile
View File

@ -29,8 +29,8 @@ BROM_PROC = ARM9
SRCDIR = ../common .
SRCS = crt0.c crt0_secure_sp.c crt0_scat.c crt0_excp.c # crt0_app.c
TARGET_OBJ = crt0.o crt0_secure_sp.o crt0_scat.o crt0_excp.o # crt0_app.o
SRCS = crt0.c crt0_secure_sp.c crt0_scat.c crt0_excp.c crt0_app.c
TARGET_OBJ = crt0.o crt0_secure_sp.o crt0_scat.o crt0_excp.o crt0_app.o
#----------------------------------------------------------------------------

265
trunk/bootrom/build/libraries/init/ARM9/crt0_app.c
View File

@ -16,7 +16,8 @@
*---------------------------------------------------------------------------*/
#include <brom/code32.h>
#include <brom/os.h>
//#include <brom/mi.h>
#define STUPi_HW_DTCM |Image$$DTCM$$Base|
void _start(void);
@ -30,61 +31,51 @@ void _start(void);
Returns: None.
*---------------------------------------------------------------------------*/
asm void _start( void )
{
PRESERVE8
b stupStartHandlerVeneer // don't change for NULL access compatibility
stupStartHandlerVeneer
b i_stupStartHandler
}
/*---------------------------------------------------------------------------*
Name: i_stupStartHandler
Description: start handler
Arguments: None
Returns: None.
*---------------------------------------------------------------------------*/
asm void i_stupStartHandler( void )
{
INASM_EXTERN( STUPi_HW_DTCM )
INASM_EXTERN( BromSpMain )
INASM_EXTERN( main )
#ifndef BROM_ENABLE_BOOTROM_WRITE
ldr r3, =REG_ROM_ADDR
ldrb r1, [r3]
bic r1, #REG_SCFG_ROM_WE_MASK
strb r1, [r3]
#endif // BROM_ENABLE_BOOTROM_WRITE
// init BROM prot
ldr r3, =REG_PROT_ADDR
ldr r1, =4*8 // 0x1204
strh r1, [r3]
//---- initialize stack pointer
// SVC mode
mov r0, #HW_PSR_SVC_MODE
msr cpsr_c, r0
ldr sp, =HW_PRV_WRAM_SVC_STACK_END
mov r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr sp, =HW_BROM_SVC_STACK_END
// IRQ mode
mov r0, #HW_PSR_IRQ_MODE
msr cpsr_c, r0
ldr r0, =HW_PRV_WRAM_IRQ_STACK_END
mov r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_IRQ_STACK_END
mov sp, r0
// System mode
ldr r1, =HW_IRQ_STACK_SIZE
sub r1, r0, r1
mov r0, #HW_PSR_SYS_MODE
msr cpsr_csfx, r0
sub sp, r1, #4 // 4byte for stack check code
mov r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
msr cpsr_fsxc, r0
ldr r0, =HW_BROM_SYS_STACK_END
mov sp, r0
//---- initialize cp15
bl i_stupInitCP15
//---- clear wram
// DTCM (16KB)
mov r0, #0
ldr r1, =STUPi_HW_DTCM
mov r2, #HW_DTCM_SIZE
bl i_stupCpuClear32
// 64B
mov r0, #0
ldr r1, =HW_PRV_WRAM_SYSRV
ldr r2, =HW_EXCP_VENEER_BUF
sub r2, r2, r1
bl i_stupCpuClear32
ldr r1, =HW_EXCP_VENEER_BUF_END
ldr r2, =HW_PRV_WRAM_SYSRV_END
sub r2, r2, r1
bl i_stupCpuClear32
//---- lnitialize sections
bl stupInitSections
@ -99,6 +90,192 @@ terminate
b terminate
}
//-----------------------------------------------------------------------
// システム制御コプロセッサ 初期化
//-----------------------------------------------------------------------
asm void i_stupInitCP15(void)
{
// プロテクションユニット/キャッシュ/TCM ディセーブル
mrc p15, 0, r0, c1, c0, 0
ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
| HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \
| HW_C1_LD_INTERWORK_DISABLE \
| HW_C1_PROTECT_UNIT_ENABLE
#ifdef SDK_MG20EMU
bic r1, r1, #HW_C1_ITCM_ENABLE
#endif // SDK_MG20EMU
bic r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
// キャッシュ無効化
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // 命令キャッシュ
mcr p15, 0, r0, c7, c6, 0 // データキャッシュ
// ライトバッファ エンプティ待ち
mcr p15, 0, r0, c7, c10, 4
/*
; Region G: BACK_GROUND: Base = 0x0, Size = 4GB, I:NC NB / D:NC NB, I:NA / D:NA
; Region 0: MAIN_MEM: Base = 0x20000000, Size = 128MB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 1: IO_AXIRAM: Base = 0x10000000, Size = 256MB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 2: PRV_WRAM: Base = 0x08000000, Size = 1MB, I:Cach Buf / D:Cach Buf, I:NA / D:RW
; Region 3: PRV_WRAM_SYSRV:Base = 0x08000000, Size = 4KB, I:Cach Buf / D:Cach Buf, I:RO / D:RW
; Region 4: DTCM: Base = 0xfffe0000, Size = 16KB, I:NC NB / D:NC NB, I:NA / D:RW
; Region 5: ITCM: Base = 0x07ff8000, Size = 32KB, I:Cach Buf / D:NC NB, I:RO / D:RW
; Region 6: BIOS: Base = 0xffff0000, Size = 64KB, I:Cach NB / D:Cach NB, I:RO / D:RO
; Region 7: SHARED_WORK: Base = 0x17fff000, Size = 8KB, I:NC NB / D:NC NB, I:NA / D:RW
*/
#define SET_PROTECTION_A( id, adr, siz ) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE)
#define SET_PROTECTION_B( id, adr, siz ) mcr p15, 0, r0, c6, id, 0
#define REGION_BIT(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7))
#define REGION_ACC(a,b,c,d,e,f,g,h) (((a)<<0)|((b)<<4)|((c)<<8)|((d)<<12)|((e)<<16)|((f)<<20)|((g)<<24)|((h)<<28))
#define NA 0
#define RW 1
#define RO 5
//
// メモリリージョン初期化
//
//---- メインメモリ
SET_PROTECTION_A( c0, HW_MAIN_MEM, 128MB )
SET_PROTECTION_B( c0, HW_MAIN_MEM, 128MB )
//---- I/Oレジスタ & VRAM & AXI-WRAM
SET_PROTECTION_A( c1, HW_IOREG, 256MB )
SET_PROTECTION_B( c1, HW_IOREG, 256MB )
//---- PRV_WRAM
SET_PROTECTION_A( c2, HW_PRV_WRAM, 1MB )
SET_PROTECTION_B( c2, HW_PRV_WRAM, 1MB )
//---- PRV_WRAM_SYSRV
#ifndef SDK_MG20EMU
SET_PROTECTION_A( c3, HW_PRV_WRAM_SYSRV, 4KB )
SET_PROTECTION_B( c3, HW_PRV_WRAM_SYSRV, 4KB )
#else // SDK_MG20EMU
SET_PROTECTION_A( c3, HW_MG20IOP_REG, 1MB )
SET_PROTECTION_B( c3, HW_MG20IOP_REG, 1MB )
#endif // SDK_MG20EMU
//---- データ TCM
ldr r0, =STUPi_HW_DTCM
orr r0, r0, #HW_C6_PR_16KB
orr r0, r0, #HW_C6_PR_ENABLE
SET_PROTECTION_B( c4, HW_DTCM, 16KB )
//---- 命令 TCM
// データ TCM より優先が高い
SET_PROTECTION_A( c5, HW_ITCM, 32KB )
SET_PROTECTION_B( c5, HW_ITCM, 32KB )
//---- BIOS
SET_PROTECTION_A( c6, HW_BIOS, 64KB )
SET_PROTECTION_B( c6, HW_BIOS, 64KB )
//---- SHARED CPU 間通信ワーク領域
SET_PROTECTION_A( c7, HW_AXI_WRAM_SHARED, 8KB )
SET_PROTECTION_B( c7, HW_AXI_WRAM_SHARED, 8KB )
//
// 命令ＴＣＭ 設定
//
mov r0, #HW_C9_TCMR_128MB
mcr p15, 0, r0, c9, c1, 1
//
// データＴＣＭ 設定
//
ldr r0, =STUPi_HW_DTCM
orr r0, r0, #HW_C9_TCMR_16KB
mcr p15, 0, r0, c9, c1, 0
//
// 命令キャッシュ イネーブル (リージョン設定)
// 6: BIOS
//
mov r0, #REGION_BIT(0,0,0,0,0,0,1,0)
mcr p15, 0, r0, c2, c0, 1
//
// データキャッシュ イネーブル (リージョン設定)
// 0: HW_MAIN_MEM
// 2: PRV_WRAM
// 6: BIOS
//
mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
mcr p15, 0, r0, c2, c0, 0
//
// ライトバッファ イネーブル(リージョン設定)
// 0: HW_MAIN_MEM
// 2: PRV_WRAM
// 6: BIOS
//
mov r0, #REGION_BIT(1,0,1,0,0,0,1,0)
mcr p15, 0, r0, c3, c0, 0
//
// 命令アクセス許可 (リージョン設定)
// MAIN_MEM : NA
// IO_AXIRAM : NA
// PRV_WRAM : NA
// PRV_WRAM_SYSRV: RO
// DTCM : NA
// ITCM : RO
// BIOS : RO
// SHARED : NA
//
#ifndef SDK_MG20EMU
ldr r0, =REGION_ACC(NA,NA,NA,RO,NA,RO,RO,NA)
#else // SDK_MG20EMU
ldr r0, =REGION_ACC(NA,NA,RO,NA,NA,RO,RO,NA)
#endif // SDK_MG20EMU
mcr p15, 0, r0, c5, c0, 3
//
// データアクセス許可（リージョン設定）
// MAIN_MEM : RW
// IO_AXIRAM : RW
// PRV_WRAM : RW
// PRV_WRAM_SYSRV: RW
// DTCM : RW
// ITCM : RW
// BIOS : RO
// SHARED : RW
//
#ifdef BROM_ENABLE_BOOTROM_WRITE
ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RW,RW)
#else // BROM_ENABLE_BOOTROM_WRITE
ldr r0, =REGION_ACC(RW,RW,RW,RW,RW,RW,RO,RW)
#endif // BROM_ENABLE_BOOTROM_WRITE
mcr p15, 0, r0, c5, c0, 2
//
// システム制御コプロセッサ マスター設定
//
mrc p15, 0, r0, c1, c0, 0
ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \
| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
| HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \
| HW_C1_PROTECT_UNIT_ENABLE
orr r0, r0, r1
#ifdef SDK_MG20EMU
bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER
#endif // SDK_MG20EMU
mcr p15, 0, r0, c1, c0, 0
bx lr
LTORG
EXPORT i_stupInitCP15_End
i_stupInitCP15_End
}
#undef BROM_TARGET_BROM
#include <./crt0_misc_sp.c>

31
trunk/bootrom/build/tests/Makefile Normal file
View File

@ -0,0 +1,31 @@
#! make -f
#----------------------------------------------------------------------------
# Project: CtrBrom - bootrom
# File: Makefile
#
# Copyright 2009 Nintendo. All rights reserved.
#
# These coded instructions, statements, and computer programs contain
# proprietary information of Nintendo of America Inc. and/or Nintendo
# Company Ltd., and are protected by Federal copyright law. They may
# not be disclosed to third parties or copied or duplicated in any form,
# in whole or in part, without the prior written consent of Nintendo.
#
# $Date:: $
# $Rev$
# $Author$
#----------------------------------------------------------------------------
include $(CTRBROM_ROOT)/build/buildtools/commondefs
#----------------------------------------------------------------------------
SUBDIRS = \
thread \
#----------------------------------------------------------------------------
include $(CTRBROM_ROOT)/build/buildtools/modulerules
#===== End of Makefile =====

50
trunk/bootrom/build/tests/thread/ARM11/Makefile Normal file
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@ -0,0 +1,50 @@
#! make -f
#----------------------------------------------------------------------------
# Project: CtrBrom - bootrom - thread
# File: Makefile
#
# Copyright 2008 Nintendo. All rights reserved.
#
# These coded instructions, statements, and computer programs contain
# proprietary information of Nintendo of America Inc. and/or Nintendo
# Company Ltd., and are protected by Federal copyright law. They may
# not be disclosed to third parties or copied or duplicated in any form,
# in whole or in part, without the prior written consent of Nintendo.
#
# $Date:: $
# $Rev$
# $Author$
#----------------------------------------------------------------------------
#BROM_DEF_LINK_SCATLD = TRUE
BROM_TARGET = APP
SUBDIRS =
#----------------------------------------------------------------------------
TARGET_BIN = thread11.axf
SRCS = \
main.c \
#LCFILE = # using default
include $(CTRBROM_ROOT)/build/buildtools/commondefs
SRCDIR = . $(ROOT)/bootrom/build/bootrom/thread/ARM11 \
INSTALL_DIR = ..
INSTALL_TARGETS = $(BINDIR)/$(TARGET_BIN_BASENAME).axf
#----------------------------------------------------------------------------
do-build: $(TARGETS)
include $(CTRBROM_ROOT)/build/buildtools/modulerules
#===== End of Makefile =====

52
trunk/bootrom/build/tests/thread/ARM9/Makefile Normal file
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@ -0,0 +1,52 @@
#! make -f
#----------------------------------------------------------------------------
# Project: CtrBrom - bootrom - thread
# File: Makefile
#
# Copyright 2008 Nintendo. All rights reserved.
#
# These coded instructions, statements, and computer programs contain
# proprietary information of Nintendo of America Inc. and/or Nintendo
# Company Ltd., and are protected by Federal copyright law. They may
# not be disclosed to third parties or copied or duplicated in any form,
# in whole or in part, without the prior written consent of Nintendo.
#
# $Date:: $
# $Rev$
# $Author$
#----------------------------------------------------------------------------
#BROM_DEF_LINK_SCATLD = TRUE
BROM_TARGET = APP
BROM_PROC = ARM9
SUBDIRS =
#----------------------------------------------------------------------------
TARGET_BIN = thread9.axf
SRCS = \
main.c \
#LCFILE = # using default
include $(CTRBROM_ROOT)/build/buildtools/commondefs
SRCDIR = . $(ROOT)/bootrom/build/bootrom/thread/ARM9 \
INSTALL_DIR = ..
INSTALL_TARGETS = $(BINDIR)/$(TARGET_BIN_BASENAME).axf
#----------------------------------------------------------------------------
do-build: $(TARGETS)
include $(CTRBROM_ROOT)/build/buildtools/modulerules
#===== End of Makefile =====

33
trunk/bootrom/build/tests/thread/Makefile Normal file
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@ -0,0 +1,33 @@
#! make -f
#----------------------------------------------------------------------------
# Project: CtrBrom - build
# File: Makefile
#
# Copyright 2009 Nintendo. All rights reserved.
#
# These coded instructions, statements, and computer programs contain
# proprietary information of Nintendo of America Inc. and/or Nintendo
# Company Ltd., and are protected by Federal copyright law. They may
# not be disclosed to third parties or copied or duplicated in any form,
# in whole or in part, without the prior written consent of Nintendo.
#
# $Date:: $
# $Rev$
# $Author$
#----------------------------------------------------------------------------
include $(CTRBROM_ROOT)/build/buildtools/commondefs
#----------------------------------------------------------------------------
SUBDIRS = \
ARM11 \
ARM9 \
#----------------------------------------------------------------------------
include $(CTRBROM_ROOT)/build/buildtools/modulerules
#===== End of Makefile =====

61
trunk/bootrom/include/brom/specfiles/ARM11-APP.ldscript.template Normal file
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@ -0,0 +1,61 @@
/*---------------------------------------------------------------------------*
Project: TwlBrom - specfiles
File: ARM11-TEG-APP.ldscript.template
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-12-01#$
$Rev: 53 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
//
// Scatter Loading Description File Templete
//
#define SDK_ASM
#include <brom/hw/ARM11/mmap_brom.h>
#define HW_APP HW_MAIN_MEM
#define HW_APP_END (HW_APP + HW_APP_SIZE)
#define HW_APP_SIZE HW_MAIN_MEM_SIZE
LOAD_STATIC HW_APP HW_APP_SIZE
{
STUP_ENTRY +0
{
*crt0_app.*o (.emb_text, +FIRST)
#ifdef BROM_DEF_LINK_SCATLD
*crt0scat.*o (.emb_text)
__main.o (+RO)
* (Region$$Table)
* (ZISection$$$Table)
#endif // BROM_DEF_LINK_SCATLD
}
RO +0
{
* (+RO)
}
RW +0
{
* (+RW)
}
ZI +0
{
* (+ZI)
}
BUF_OVER_BARRIER HW_APP_END EMPTY 0
{
}
}

84
trunk/bootrom/include/brom/specfiles/ARM9-APP.ldscript.template Normal file
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@ -0,0 +1,84 @@
/*---------------------------------------------------------------------------*
Project: TwlBrom - specfiles
File: ARM9-TEG-APP.ldscript.template
Copyright 2008 Nintendo. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Date:: 2008-12-01#$
$Rev: 53 $
$Author: nakasima $
*---------------------------------------------------------------------------*/
//
// Scatter Loading Description File Templete
//
#define SDK_ASM
#include <brom/memorymap.h>
#define HW_APP HW_PRV_WRAM_SYSRV_END
#define HW_APP_END (HW_APP + HW_APP_SIZE)
#define HW_APP_SIZE (HW_PRV_WRAM_SIZE - HW_PRV_WRAM_SYSRV_SIZE)
LOAD_STATIC HW_APP HW_APP_SIZE
{
STUP_ENTRY +0
{
*crt0_app.*o (.emb_text, +FIRST)
#ifdef BROM_DEF_LINK_SCATLD
*crt0scat.*o (.emb_text)
__main.o (+RO)
* (Region$$Table)
* (ZISection$$$Table)
#endif // BROM_DEF_LINK_SCATLD
}
RO +0
{
* (+RO)
}
RW +0
{
* (+RW)
}
ZI +0
{
* (+ZI)
}
BUF_OVER_BARRIER HW_APP_END EMPTY 0
{
}
#ifndef BROM_DEF_LINK_SCATLD
DTCM HW_DTCM EMPTY 0
{
}
#else // BROM_DEF_LINK_SCATLD
ITCM (HW_ITCM + 0x100) (HW_ITCM_SIZE - 0x100)
{
* (.itcm)
* (.itcm.bss)
}
DTCM HW_DTCM HW_DTCM_SIZE
{
* (.dtcm)
* (.dtcm.bss)
}
#endif // BROM_DEF_LINK_SCATLD
}

2
trunk/include/ctr/hw/ARM11/mmap_axi_wram.h
View File

@ -68,8 +68,8 @@ extern "C" {
#define HW_CARD_LOCK_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_CARD_LOCK_BUF)
#ifdef SDK_ARM11
#define HW_START_VECTOR1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_START_VECTOR1)
#define HW_INTR_CHECK0_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0)
#define HW_INTR_CHECK1_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK1)
#define HW_INTR_CHECK0_BUF (HW_AXI_WRAM_SYSRV + HW_AXI_WRAM_SYSRV_OFS_INTR_CHECK0)
#endif // SDK_ARM11