mirror of
https://github.com/rvtr/ctr_firmware.git
synced 2025-10-31 07:51:08 -04:00
aff8998612
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@235 b871894f-2f95-9b40-918c-086798483c85
132 lines
4.9 KiB
C
132 lines
4.9 KiB
C
/*---------------------------------------------------------------------------*
|
|
Project: CtrFirm - include - ctr - HW - ARM9
|
|
File: mmap_global.h
|
|
|
|
Copyright 2008 Nintendo. All rights reserved.
|
|
|
|
These coded instructions, statements, and computer programs contain
|
|
proprietary information of Nintendo of America Inc. and/or Nintendo
|
|
Company Ltd., and are protected by Federal copyright law. They may
|
|
not be disclosed to third parties or copied or duplicated in any form,
|
|
in whole or in part, without the prior written consent of Nintendo.
|
|
|
|
$Date:: $
|
|
$Rev$
|
|
$Author$
|
|
*---------------------------------------------------------------------------*/
|
|
#ifndef CTR_HW_ARM9_MMAP_GLOBAL_H_
|
|
#define CTR_HW_ARM9_MMAP_GLOBAL_H_
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
GLOBAL MEMORY MAP
|
|
*---------------------------------------------------------------------------*/
|
|
|
|
//----------------------------- ITCM
|
|
#define HW_ITCM 0x07ff8000
|
|
#define HW_ITCM_SIZE 0x8000 // 32KB
|
|
#define HW_ITCM_END (HW_ITCM + HW_ITCM_SIZE)
|
|
|
|
//----------------------------- DTCM
|
|
#define HW_DTCM 0xfff00000
|
|
#define HW_DTCM_END (HW_DTCM + HW_DTCM_SIZE)
|
|
#define HW_DTCM_SIZE 0x4000 // 16KB
|
|
|
|
//----------------------------- MAIN
|
|
#define HW_MAIN_MEM 0x20000000
|
|
#define HW_MAIN_MEM_EX HW_MAIN_MEM_END
|
|
#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE)
|
|
#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE)
|
|
#define HW_MAIN_MEM_SIZE 0x04000000 // 64MB
|
|
#define HW_MAIN_MEM_EX_SIZE 0x08000000 // 128MB
|
|
|
|
#ifndef SDK_MG20EMU
|
|
//----------------------------- AXI-WRAM
|
|
#define HW_AXI_WRAM 0x1ff80000
|
|
#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE)
|
|
#define HW_AXI_WRAM_SIZE 0x80000 // 512KB
|
|
|
|
//----------------------------- DSP-WRAM (only DMAC2)
|
|
#define HW_DSP_WRAM 0x1ff00000
|
|
#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE)
|
|
#define HW_DSP_WRAM_SIZE 0x80000 // 512KB
|
|
|
|
//----------------------------- VRAM
|
|
#define HW_VRAM 0x18000000
|
|
#define HW_VRAM_END (HW_VRAM + HW_VRAM_SIZE)
|
|
#define HW_VRAM_SIZE 0x400000 // 4MB
|
|
|
|
#else // SDK_MG20EMU
|
|
//----------------------------- AXI-WRAM
|
|
#define HW_AXI_WRAM 0x00100000
|
|
#define HW_AXI_WRAM_END (HW_AXI_WRAM + HW_AXI_WRAM_SIZE)
|
|
#define HW_AXI_WRAM_SIZE 0x1000 // 4KB
|
|
|
|
//----------------------------- DSP-WRAM (only DMAC2)
|
|
#define HW_DSP_WRAM HW_AXI_WRAM
|
|
#define HW_DSP_WRAM_END (HW_DSP_WRAM + HW_DSP_WRAM_SIZE)
|
|
#define HW_DSP_WRAM_SIZE 0 // 0B
|
|
|
|
//----------------------------- VRAM
|
|
#define HW_VRAM 0x1e000000
|
|
#define HW_VRAM_END (HW_VRAM + HW_VRAM_SIZE)
|
|
#define HW_VRAM_SIZE 0x400000 // 4MB
|
|
|
|
#endif // SDK_MG20EMU
|
|
|
|
#if !defined(SDK_MG20EMU) && !defined(SDK_NE1EMU)
|
|
//----------------------------- Private WRAM
|
|
#define HW_PRV_WRAM 0x08000000
|
|
#define HW_PRV_WRAM_END (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
|
|
#define HW_PRV_WRAM_SIZE 0x100000 // 1MB
|
|
|
|
//----------------------------- IOs
|
|
#define HW_IOREG 0x10000000
|
|
#define HW_IOREG_END 0x18000000
|
|
#define HW_REG_BASE HW_IOREG // alias
|
|
|
|
#else // SDK_MG20EMU || SDK_NE1EMU
|
|
//----------------------------- Private WRAM
|
|
#define HW_PRV_WRAM 0x10000000
|
|
#define HW_PRV_WRAM_END (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
|
|
#define HW_PRV_WRAM_SIZE 0x100000 // 1MB
|
|
|
|
//----------------------------- IOs
|
|
#define HW_IOREG 0x08000000
|
|
#define HW_IOREG_END 0x10000000
|
|
#define HW_REG_BASE HW_IOREG // alias
|
|
|
|
#ifdef SDK_MG20EMU
|
|
#define HW_MG20IOP_REG 0x40000000
|
|
#define HW_MG20IOP_REG_END 0x40100000
|
|
#endif // SDK_MG20EMU
|
|
|
|
#endif // SDK_MG20EMU || SDK_NE1EMU
|
|
|
|
#define HW_PRV_REG (HW_IOREG + 0)
|
|
#define HW_AHBP_REG (HW_IOREG + 0x00100000)
|
|
#define HW_PRV_REG_END (HW_PRV_REG + HW_PRV_REG_SIZE)
|
|
#define HW_AHBP_REG_END (HW_AHBP_REG + HW_AHBP_REG_SIZE)
|
|
#define HW_PRV_REG_SIZE 0x20000 // 128MB
|
|
#define HW_AHBP_REG_SIZE 0x80000 // 512MB
|
|
|
|
//----------------------------- System ROM
|
|
#ifdef SDK_MG20EMU
|
|
#define HW_BIOS 0x00000000
|
|
#else // SDK_MG20EMU
|
|
#define HW_BIOS 0xffff0000
|
|
#endif // SDK_MG20EMU
|
|
#define HW_BIOS_END (HW_BIOS + HW_BIOS_SIZE)
|
|
#define HW_BIOS_SIZE 0x8000 // 32KB
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
#ifdef __cplusplus
|
|
} /* extern "C" */
|
|
#endif
|
|
#endif /* CTR_HW_ARM9_MMAP_GLOBAL_H_ */
|