mirror of
https://github.com/rvtr/ctr_firmware.git
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f48f0be43f
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@153 b871894f-2f95-9b40-918c-086798483c85
87 lines
3.6 KiB
C
87 lines
3.6 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrBrom - include - PXI
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File: regname.h
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Copyright 2009 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#ifndef BROM_PXI_COMMON_REGNAME_H_
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#define BROM_PXI_COMMON_REGNAME_H_
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#include <brom/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register rename
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typedef enum
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{
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PXI_PROC_ARM11 = 0,
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PXI_PROC_ARM9 = 1
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}
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PXIProc;
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#ifdef SDK_ARM11
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#define PXI_PROC_ARM PXI_PROC_ARM11
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#define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT
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#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK
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#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_SHIFT REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT
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#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK
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#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_SHIFT REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT
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#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK
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#define reg_PXI_INTF reg_PXI_SUBPINTF
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#define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK
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#define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK
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#define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A11STATUS_MASK
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#define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A11STATUS_SHIFT
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#define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A9STATUS_MASK
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#define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT
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#else // SDK_ARM9
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#define PXI_PROC_ARM PXI_PROC_ARM9
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#define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT
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#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK
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#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_SHIFT REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT
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#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK
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#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_SHIFT REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT
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#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK
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#define reg_PXI_INTF reg_PXI_MAINPINTF
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#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK
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#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK
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#define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A9STATUS_MASK
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#define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT
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#define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A11STATUS_MASK
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#define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A11STATUS_SHIFT
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#endif
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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/* BROM_PXI_COMMON_REGNAME_H_ */
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#endif
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