rvtr/ctr_firmware
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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@153 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2009-01-05 10:51:10 +00:00
parent e060e43135
commit f48f0be43f
2 changed files with 19 additions and 19 deletions
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10
trunk/bootrom/include/brom/pxi/common/fifo.h
View File

@ -51,11 +51,11 @@ PXIFifoTag;
/* for Compatibility */
#define PXI_FIFO_DEVICE_TEST PXI_FIFO_TAG_USR_0
#define PXI_FIFO_DEVICE_FLASH PXI_FIFO_TAG_NVRAM
#define PXI_FIFO_DEVICE_RTC PXI_FIFO_TAG_RTC
#define PXI_FIFO_DEVICE_TOUCHPANEL PXI_FIFO_TAG_TOUCHPANEL
#define PXI_MAX_DEVICES PXI_MAX_FIFO_TAG
#define PXI_FIFO_DEVICE_TEST PXI_FIFO_TAG_USR_0
#define PXI_FIFO_DEVICE_FLASH PXI_FIFO_TAG_NVRAM
#define PXI_FIFO_DEVICE_RTC PXI_FIFO_TAG_RTC
#define PXI_FIFO_DEVICE_TOUCHPANEL PXI_FIFO_TAG_TOUCHPANEL
#define PXI_MAX_DEVICES PXI_MAX_FIFO_TAG
/* PXI_FIFO return code */

28
trunk/bootrom/include/brom/pxi/common/regname.h
View File

@ -33,7 +33,7 @@ PXIProc;
#ifdef SDK_ARM11
#define PXI_PROC_ARM PXI_PROC_ARM11
#define PXI_PROC_ARM PXI_PROC_ARM11
#define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT
#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK
@ -47,16 +47,16 @@ PXIProc;
#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK
#define reg_PXI_INTF reg_PXI_SUBPINTF
#define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK
#define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK
#define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A11STATUS_MASK
#define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A11STATUS_SHIFT
#define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A9STATUS_MASK
#define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT
#define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK
#define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK
#define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A11STATUS_MASK
#define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A11STATUS_SHIFT
#define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A9STATUS_MASK
#define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT
#else // SDK_ARM9
#define PXI_PROC_ARM PXI_PROC_ARM9
#define PXI_PROC_ARM PXI_PROC_ARM9
#define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT
#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK
@ -70,12 +70,12 @@ PXIProc;
#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK
#define reg_PXI_INTF reg_PXI_MAINPINTF
#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK
#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK
#define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A9STATUS_MASK
#define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT
#define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A11STATUS_MASK
#define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A11STATUS_SHIFT
#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK
#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK
#define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A9STATUS_MASK
#define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT
#define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A11STATUS_MASK
#define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A11STATUS_SHIFT
#endif