rvtr/ctr_firmware
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大半の領域をＵＳＲモードでアクセス禁止へ設定。

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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@60 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-02 04:55:14 +00:00
parent b3c5a5343f
commit eeaa276484
1 changed files with 22 additions and 9 deletions
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31
trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
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@ -336,7 +336,7 @@ void stupInitMMUTable( void )
{ {
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_ALL, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, FALSE,
@ -353,7 +353,7 @@ void stupInitMMUTable( void )
*table++ = HW_MMU6_T1_SUSEC_PACK( *table++ = HW_MMU6_T1_SUSEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_ALL, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_SHARED_DEV, HW_MMU6_T1_RGT_SHARED_DEV,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, FALSE,
@ -367,7 +367,7 @@ void stupInitMMUTable( void )
paddr = HW_MPCORE_REG; paddr = HW_MPCORE_REG;
*table++ = HW_MMU6_T1_SEC_PACK( *table++ = HW_MMU6_T1_SEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_ALL, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_NSHARED_DEV, HW_MMU6_T1_RGT_NSHARED_DEV,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, FALSE,
@ -380,7 +380,7 @@ void stupInitMMUTable( void )
{ {
*table++ = HW_MMU6_T1_SEC_PACK( *table++ = HW_MMU6_T1_SEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_ALL, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1L2C_WB_WA, HW_MMU6_T1_RGT_L1L2C_WB_WA,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, FALSE,
@ -399,19 +399,19 @@ void stupInitMMUTable( void )
{ {
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_ALL, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, FALSE,
FALSE); FALSE);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE; paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
} }
for ( paddr = HW_BROM_MMU_TBL; paddr < HW_AXI_WRAM_SHARED_END; ) for ( ; paddr < HW_AXI_WRAM_SHARED_END; )
{ {
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_ALL, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_SHARED_DEV, HW_MMU6_T2_LP_RGT_SHARED_DEV,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, FALSE,
FALSE); FALSE);
@ -422,7 +422,20 @@ void stupInitMMUTable( void )
// Main Memory Region (128MB cached) // Main Memory Region (128MB cached)
table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE]; table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE];
for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_EX_END; ) for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_END; )
{
*table++ = HW_MMU6_T1_SUSEC_PACK(
paddr,
HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1L2C_WB_WA,
HW_MMU6_T1_GLOBAL,
FALSE,
FALSE
);
paddr += HW_MMU6_T1_SEC_SIZE;
}
for ( ; paddr < HW_MAIN_MEM_EX_END; )
{ {
*table++ = HW_MMU6_T1_SUSEC_PACK( *table++ = HW_MMU6_T1_SUSEC_PACK(