mirror of
https://github.com/rvtr/ctr_firmware.git
synced 2025-10-31 07:51:08 -04:00
eeaa276484
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@60 b871894f-2f95-9b40-918c-086798483c85
456 lines
14 KiB
C
456 lines
14 KiB
C
/*---------------------------------------------------------------------------*
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Project: CtrBrom - library - init
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File: crt0_secure.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/code32.h>
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#include <brom/os.h>
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#define STUPi_HW_DTCM |Image$$DTCM$$Base|
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void stupInitMMUTable( void );
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/*---------------------------------------------------------------------------*
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Name: STUPi_StartHandler
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Description: start handler
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Arguments: None
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Returns: None.
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*---------------------------------------------------------------------------*/
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asm void STUPi_StartHandler( void )
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{
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PRESERVE8
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INASM_EXTERN( STUPi_HW_DTCM )
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INASM_EXTERN( BromMain )
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INASM_EXTERN( main )
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//---- disable cp15
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bl stupDisableCP15
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//---- initialize MMU
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bl stupInitMMU
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//---- enable cp15
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bl stupEnableCP15
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//---- initialize stack pointer
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// SVC mode
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mov r0, #HW_PSR_SVC_MODE
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msr cpsr_c, r0
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ldr sp, =HW_BROM_SVC_STACK_END
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// IRQ mode
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mov r0, #HW_PSR_IRQ_MODE
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msr cpsr_c, r0
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ldr r0, =HW_BROM_IRQ_STACK_END
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mov sp, r0
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// System mode
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mov r0, #HW_PSR_SYS_MODE
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msr cpsr_csfx, r0
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ldr r0, =HW_BROM_SYS_STACK_END
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mov sp, r0
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//---- clear wram
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// 1KB
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mov r0, #0
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ldr r1, =HW_AXI_WRAM_END
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mov r2, #0x0400
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sub r1, r1, r2
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bl STUPi_CpuClear32
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//---- lnitialize sections
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bl stupInitSections
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//---- start (to 16bit code)
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ldr r1, =BromMain
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adr lr, terminate
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bx r1
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terminate
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b terminate
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}
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/*---------------------------------------------------------------------------*
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Name: stupDisableCP15
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Description: Disable Coprocessor 15
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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ASM void stupDisableCP15( void )
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{
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// MMU/Caches/BranchPrediction disable
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
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| HW_C1_FORCE_AP_BIT \
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| HW_C1_TEX_CB_REMAP \
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| HW_C1_NMFI_FIQ \
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| HW_C1_EXCEPT_VEC_UPPER \
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| HW_C1_EXCEPT_BIG_ENDIAN \
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| HW_C1_BR_PREDICT_ENABLE \
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| HW_C1_LD_INTERWORK_DISABLE \
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| HW_C1_UNALIGN_ACCESS_ENABLE \
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| HW_C1_ALIGN_FAULT_ENABLE \
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| HW_C1_ROM_PROTECT_ENABLE \
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| HW_C1_MMU_PROTECT_ENABLE \
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| HW_C1_MMU_ENABLE
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bic r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 1
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ldr r1, =HW_C1_SMP_MODE \
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| HW_C1_EXCLUSIVE_L1C_L2C \
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| HW_C1_BR_FOLDING_ENABLE \
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| HW_C1_SBR_PREDICT_ENABLE \
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| HW_C1_DBR_PREDICT_ENABLE \
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| HW_C1_RETURN_STACK_ENABLE
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bic r0, r0, r1
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mcr p15, 0, r0, c1, c0, 1
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#if 0
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// Invalidate Caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // Inst Cache
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mcr p15, 0, r0, c7, c6, 0 // Data cache
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#endif
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// Wait for write buffer empty
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: stupEnableCP15
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Description: Enable Coprocessor 15
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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ASM void stupEnableCP15( void )
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{
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//
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// Auxiliary Control
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//
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mrc p15, 0, r0, c1, c0, 1
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ldr r1, =HW_C1_AMP_MODE \
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| HW_C1_BR_FOLDING_ENABLE \
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| HW_C1_SBR_PREDICT_ENABLE \
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| HW_C1_DBR_PREDICT_ENABLE \
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| HW_C1_RETURN_STACK_ENABLE
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 1
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//
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// Master Control
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//
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_0_SB1 \
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| HW_C1_EXCEPT_LITTLE_ENDIAN \
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| HW_C1_UNALIGN_ACCESS_ENABLE \
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| HW_C1_BR_PREDICT_ENABLE \
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| HW_C1_MMU_V6 \
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| HW_C1_IC_ENABLE \
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| HW_C1_DC_ENABLE \
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| HW_C1_MMU_ENABLE
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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// Invalidate Caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // Inst Cache
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mcr p15, 0, r0, c7, c6, 0 // Data cache
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// Wait for write buffer empty
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitMMU
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Description: Initialize MMU
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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ASM void stupInitMMU( void )
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{
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stmfd sp!, {r4, lr} // stack requires 8byte alignment
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// Invalidate ITLB DTLB
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mov r0, #0
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mcr p15, 0, r0, c8, c5, 0
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mcr p15, 0, r0, c8, c6, 0
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ldr r0, =HW_BROM_MMU_T1
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mov r2, #HW_C2_V5_T1_BOUNBARY_16KB
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// MMU L1 Table Base
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ldr r1, =HW_C2_0_T1_BASE_MASK_MIN
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mov r1, r1, ASR r2
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and r1 ,r1, r0
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orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT
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mcr p15, 0, r1, c2, c0, 0
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ldr r1, =HW_C2_1_T1_BASE_MASK
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and r1 ,r1, r0
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orr r1, r1, #HW_C2_WALK_L2C_CA_NC << HW_C2_WALK_L2C_CA_SFT
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mcr p15, 0, r1, c2, c0, 1
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// MMU L1 Table Boundary
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mcr p15, 0, r2, c2, c0, 2
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// Domain Access Permission
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#if 1 // miya
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ldr r1, =0x00000001
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#else
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ldr r1, = HW_C3_DOMAIN_PACK( \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_CLIENT, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER, \
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HW_C3_DM_AP_MANAGER \
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)
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#endif
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mcr p15, 0, r1, c3, c0, 0
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// VFP Access Permission
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ldr r1, =HW_C1_VFP_AP_PACK( \
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HW_C1_AP_PRIV, HW_C1_AP_PRIV )
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mcr p15, 0, r1, c1, c0, 2
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// Initialize MMU Table
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bl __cpp(stupInitMMUTable)
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ldmfd sp!, {r4, pc} // stack requires 8byte alignment
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}
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/*---------------------------------------------------------------------------*
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Name: stupInitMMUTable
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Description: Initialize MMU Table
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void stupInitMMUTable( void )
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{
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u32* t1Base = (u32* )HW_BROM_MMU_T1;
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u32* t2Base = (u32* )HW_BROM_MMU_T2;
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u32* table;
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u32 paddr = (u32 )NULL;
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// Initialize as Access Prohibition
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table = &t1Base[0];
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for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; )
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{
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_APX_NA,
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HW_MMU6_T1_RGT_STRONG_ORDER,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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HW_MMU6_T1_XN,
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0);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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table = &t2Base[0];
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for ( paddr = (u32 )NULL; table < (void *)HW_BROM_MMU_T1_END; )
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{
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*table++ = HW_MMU6_T2_SP_PACK(
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paddr,
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HW_MMU6_T2_APX_NA,
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HW_MMU6_T2_LP_RGT_STRONG_ORDER,
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HW_MMU6_T2_GLOBAL,
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FALSE,
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HW_MMU6_T2_SP_XN);
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}
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// BROM Region (64KBx2 cached)
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table = &t1Base[HW_BIOS_IMG/HW_MMU6_T1_SEC_SIZE];
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paddr = HW_BIOS_IMG;
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*table = HW_MMU6_T1_COURSE_PACK( paddr, 0 );
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// T2 for Page
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table = &t2Base[0];
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for ( paddr = HW_BIOS_IMG; paddr < HW_BROM_END; )
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{
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*table++ = HW_MMU6_T2_LP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
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HW_MMU6_T2_GLOBAL,
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FALSE,
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FALSE);
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paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
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}
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// Coarse page is 1KB boundary
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t2Base += MATH_ROUNDUP(HW_BROM_SIZE*2, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
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// IO Registers Region (16MB)
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table = &t1Base[HW_IOREG/HW_MMU6_T1_SEC_SIZE];
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for ( paddr = HW_IOREG; paddr < HW_IOREG + HW_MMU6_T1_SUSEC_SIZE; )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_SHARED_DEV,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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FALSE
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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// MPCore Registers Region (1MB)
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table = &t1Base[HW_MPCORE_REG/HW_MMU6_T1_SEC_SIZE];
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paddr = HW_MPCORE_REG;
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_NSHARED_DEV,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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FALSE,
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0);
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// VRAM Region (4MB cached)
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table = &t1Base[HW_VRAM/HW_MMU6_T1_SEC_SIZE];
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for ( paddr = HW_VRAM; paddr < HW_VRAM_END; )
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{
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*table++ = HW_MMU6_T1_SEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_L1L2C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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FALSE,
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0);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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// AXI-WRAM & DSP-WRAM Region (1MB cached & uncached)
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table = &t1Base[HW_DSP_WRAM/HW_MMU6_T1_SEC_SIZE];
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paddr = HW_DSP_WRAM;
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*table = HW_MMU6_T1_COURSE_PACK( paddr, 0 );
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// T2 for Page
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table = &t2Base[0];
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for ( paddr = HW_DSP_WRAM; paddr < HW_BROM_MMU_TBL; )
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{
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*table++ = HW_MMU6_T2_LP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
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HW_MMU6_T2_GLOBAL,
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FALSE,
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FALSE);
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paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
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}
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for ( ; paddr < HW_AXI_WRAM_SHARED_END; )
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{
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*table++ = HW_MMU6_T2_LP_PACK(
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paddr,
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HW_MMU6_T2_APX_S_RW_U_NA,
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HW_MMU6_T2_LP_RGT_SHARED_DEV,
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HW_MMU6_T2_GLOBAL,
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FALSE,
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FALSE);
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paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
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}
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// Coarse page is 1KB boundary
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t2Base += MATH_ROUNDUP(HW_DSP_WRAM_SIZE+HW_AXI_WRAM_SIZE, HW_MMU6_T1_CORS_SIZE)/sizeof(t2Base[0]);
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// Main Memory Region (128MB cached)
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table = &t1Base[HW_MAIN_MEM/HW_MMU6_T1_SEC_SIZE];
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for ( paddr = HW_MAIN_MEM; paddr < HW_MAIN_MEM_END; )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_S_RW_U_NA,
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HW_MMU6_T1_RGT_L1L2C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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FALSE
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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for ( ; paddr < HW_MAIN_MEM_EX_END; )
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{
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*table++ = HW_MMU6_T1_SUSEC_PACK(
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paddr,
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HW_MMU6_T1_APX_ALL,
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HW_MMU6_T1_RGT_L1L2C_WB_WA,
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HW_MMU6_T1_GLOBAL,
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FALSE,
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FALSE
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);
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paddr += HW_MMU6_T1_SEC_SIZE;
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}
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}
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#include <./crt0_misc.c>
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