rvtr/ctr_firmware
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タイマーレジスタの二重定義を整理。

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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@104 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-12 08:43:31 +00:00
parent e356cbe011
commit d58a354198
3 changed files with 9 additions and 56 deletions
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6
trunk/bootrom/build/libraries/os/ARM11/os_timer.c
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@ -289,7 +289,8 @@ ASM BOOL osEnableTimerAndWatchdog( void )
// 引数 r0 は osDisableInterrupts の返り値 // 引数 r0 は osDisableInterrupts の返り値
bl __cpp(osRestoreInterrupts) bl __cpp(osRestoreInterrupts)
and r0, r4, #HW_CPUTM_ENABLE // retuen value mov r0, r4
// and r0, r4, #HW_CPUTM_ENABLE // retuen value
ldmfd sp!, {r4, pc} // stack requires 8byte alignment ldmfd sp!, {r4, pc} // stack requires 8byte alignment
} }
@ -317,7 +318,8 @@ ASM BOOL osDisableTimerAndWatchdog( void )
// 引数 r0 は osDisableInterrupts の返り値 // 引数 r0 は osDisableInterrupts の返り値
bl __cpp(osRestoreInterrupts) bl __cpp(osRestoreInterrupts)
and r0, r4, #HW_CPUTM_ENABLE // retuen value mov r0, r4
// and r0, r4, #HW_CPUTM_ENABLE // retuen value
ldmfd sp!, {r4, pc} // stack requires 8byte alignment ldmfd sp!, {r4, pc} // stack requires 8byte alignment
} }

10
trunk/bootrom/include/brom/os/ARM11/timer.h
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@ -38,21 +38,21 @@ OSTimerID;
typedef enum typedef enum
{ {
OS_WD_WATCHDOG_MODE = HW_CPUWD_WATCHDOG_MODE, OS_WD_WATCHDOG_MODE = REG_OS_WD_CNT_M_MASK,
OS_WD_TIMER_MODE = HW_CPUWD_TIMER_MODE OS_WD_TIMER_MODE = 0
} }
OSWatchdogMode; OSWatchdogMode;
typedef enum typedef enum
{ {
OS_TM_AUTO_RELOAD = HW_CPUTM_AUTO_RELOAD, OS_TM_AUTO_RELOAD = REG_OS_TM_CNT_RLD_MASK,
OS_TM_SINGLE_SHOT = HW_CPUTM_SINGLE_SHOT OS_TM_SINGLE_SHOT = 0
} }
OSTimerRepeat; OSTimerRepeat;
typedef enum typedef enum
{ {
OS_TM_INTR_REQ_ENABLE = HW_CPUTM_INTR_ENABLE, OS_TM_INTR_REQ_ENABLE = REG_OS_TM_CNT_IT_MASK,
OS_TM_INTR_REQ_DISABLE = 0 OS_TM_INTR_REQ_DISABLE = 0
} }
OSTimerIntrReq; OSTimerIntrReq;

49
trunk/include/ctr/hw/ARM11/arm11_reg.h
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@ -515,55 +515,6 @@ extern "C" {
#define HW_C15_RGT_L1L2C_WB_WA 0x07 // L1C and L2C Write-Back, Allocate on Write #define HW_C15_RGT_L1L2C_WB_WA 0x07 // L1C and L2C Write-Back, Allocate on Write
//----------------------------------------------------------------------
// Timer and Watchdog
//----------------------------------------------------------------------
// Timer
// Timer Control Register
#define HW_CPUTM_ENABLE 0x00000001 // Global timer enable
#define HW_CPUTM_DISABLE 0x00000000
#define HW_CPUTM_AUTO_RELOAD 0x00000002 // Auto-reload mode
#define HW_CPUTM_SINGLE_SHOT 0x00000000 // Single shot mode
#define HW_CPUTM_INTR_ENABLE 0x00000004 // Interrupt ID 29 enable
#define HW_CPUTM_PRESCALER_MASK 0x0000ff00 // Interval = (PRESCALER_value+1) x (Load_value+1) / CPU_clock
#define HW_CPUTM_PRESCALER_SFT 8
// Timer Interrupt Status Register
#define HW_CPUTM_EVT_FLAG 0x00000001 // Timer Event occured
// Watchdog
// Watchdog Control Register
#define HW_CPUWD_ENABLE 0x00000001 // Global watchdog enable
#define HW_CPUWD_DISABLE 0x00000000
#define HW_CPUWD_AUTO_RELOAD 0x00000002 // Auto-reload mode
#define HW_CPUWD_SINGLE_SHOT 0x00000000 // Single shot mode
#define HW_CPUWD_INTR_ENABLE 0x00000004 // Interrupt ID 30 enable
#define HW_CPUWD_WATCHDOG_MODE 0x00000008 // Watchdog mode (default)
#define HW_CPUWD_TIMER_MODE 0x00000000 // Timer mode
#define HW_CPUWD_PRESCALER_MASK 0x0000ff00 // Interval = (PRESCALER_value+1) x (Load_value+1) / CPU_clock
#define HW_CPUWD_PRESCALER_SFT 8
// Watchdog Interrupt Status Register
#define HW_CPUWD_EVT_FLAG 0x00000001 // Watchdog Event occured
// Watchdog Reset Status Register
#define HW_CPUWD_RESET 0x00000001 // Watchdog reset
#ifdef __cplusplus #ifdef __cplusplus
} // extern "C" } // extern "C"
#endif #endif