ARM9開発用ブートROMのアセンブラ版を追加。

git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@235 b871894f-2f95-9b40-918c-086798483c85

trunk/bootrom/build/bootrom/teg-dev/ARM11/Makefile

@@ -3,7 +3,7 @@
 # Project:  CtrBrom - bootrom - teg-dev
 # File:     Makefile
 #
-# Copyright 2008 Nintendo.  All rights reserved.
+# Copyright 2008-2009 Nintendo.  All rights reserved.
 #
 # These coded instructions, statements, and computer programs contain
 # proprietary information of Nintendo of America Inc. and/or Nintendo
@@ -33,16 +33,12 @@ SRCS		=	\
                 crt0_secure.c \
                 crt0_excp.c \
 
-#SRCS		=	\
-#                main.c \
-
 #SRCDIR		=	# using default
 #LCFILE		=	# using default
 
 include	$(CTRBROM_ROOT)/build/buildtools/commondefs
 
-SRCDIR		=	. \
+SRCDIR		+=	$(ROOT)/bootrom/build/libraries/init/ARM11 \
-                $(ROOT)/bootrom/build/libraries/init/ARM11 \
                 $(ROOT)/bootrom/build/libraries/init/common \
 
 INSTALL_DIR	= ..

trunk/bootrom/build/bootrom/teg-dev/ARM9/Makefile

@@ -28,14 +28,21 @@ SUBDIRS		=
 
 TARGET_BIN	=	teg_dev9.padbin
 
+CRT0_O		=  
+
 SRCS		=	\
-                main.c \
+                crt0.c \
+                crt0_secure_sp.c \
+                crt0_excp.c \
 
 #SRCDIR		=	# using default
 #LCFILE		=	# using default
 
 include	$(CTRBROM_ROOT)/build/buildtools/commondefs
 
+SRCDIR		+=	$(ROOT)/bootrom/build/libraries/init/ARM9 \
+                $(ROOT)/bootrom/build/libraries/init/common \
+
 INSTALL_DIR	= ..
 INSTALL_TARGETS	= $(BINDIR)/$(TARGET_BIN_BASENAME).axf
 

trunk/bootrom/build/bootrom/teg-dev/ARM9/crt0_secure_sp.c

@@ -0,0 +1,106 @@
+/*---------------------------------------------------------------------------*
+  Project:  CtrBrom - library - init
+  File:     crt0_secure_sp.c
+
+  Copyright 2008 Nintendo.  All rights reserved.
+
+  These coded instructions, statements, and computer programs contain
+  proprietary information of Nintendo of America Inc. and/or Nintendo
+  Company Ltd., and are protected by Federal copyright law.  They may
+  not be disclosed to third parties or copied or duplicated in any form,
+  in whole or in part, without the prior written consent of Nintendo.
+
+  $Date::            $
+  $Rev$
+  $Author$
+ *---------------------------------------------------------------------------*/
+#include <brom/code32.h>
+#include <brom/os.h>
+
+#define BROM_ENABLE_BOOTROM_WRITE
+
+#define STUPi_HW_DTCM   |Image$$DTCM$$Base|
+
+/*---------------------------------------------------------------------------*
+  Name:         i_stupStartHandler
+
+  Description:  start handler
+
+  Arguments:    None
+
+  Returns:      None.
+ *---------------------------------------------------------------------------*/
+asm void i_stupStartHandler( void )
+{
+        PRESERVE8
+
+        INASM_EXTERN( STUPi_HW_DTCM )
+        INASM_EXTERN( stupInitExceptions )
+        INASM_EXTERN( i_osFinalize )
+
+#ifndef BROM_ENABLE_BOOTROM_WRITE
+
+        ldr     r3, =REG_ROM_ADDR
+        ldrb    r1, [r3]
+        bic     r1, #REG_SCFG_ROM_WE_MASK
+        strb    r1, [r3]
+
+#endif // BROM_ENABLE_BOOTROM_WRITE
+
+        //---- initialize stack pointer
+        // SVC mode
+        mov             r0, #HW_PSR_SVC_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
+        msr             cpsr_fsxc, r0
+        ldr             sp, =HW_BROM_SVC_STACK_END
+
+        // IRQ mode
+        mov             r0, #HW_PSR_IRQ_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
+        msr             cpsr_fsxc, r0
+        ldr             r0, =HW_BROM_IRQ_STACK_END
+        mov             sp, r0
+
+        // System mode
+        mov             r0, #HW_PSR_SYS_MODE | HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE
+        msr             cpsr_fsxc, r0
+        ldr             r0, =HW_BROM_SYS_STACK_END
+        mov             sp, r0
+
+        //---- initialize cp15
+        bl              i_stupEnableTCM
+
+        //---- initialize exceptions
+        bl              stupInitExceptions
+
+        //---- clear wram
+        // DTCM (16KB)
+        mov             r0, #0
+        ldr             r1, =STUPi_HW_DTCM
+        mov             r2, #HW_DTCM_SIZE
+        bl              i_stupCpuClear32
+
+        // 64B
+        mov             r0, #0
+        ldr             r1, =HW_PRV_WRAM_SYSRV
+        ldr             r2, =HW_EXCP_VENEER_BUF
+        sub             r2, r2, r1
+        bl              i_stupCpuClear32
+
+        ldr             r1, =HW_EXCP_VENEER_BUF_END
+        ldr             r2, =HW_PRV_WRAM_SYSRV_END
+        sub             r2, r2, r1
+        bl              i_stupCpuClear32
+
+        // os finalize
+        bl              i_osFinalize
+
+        // enable JTAG
+        ldr             r3, =REG_JTAG_ADDR
+        ldr             r0, =REG_SCFG_JTAG_A11JE_MASK | REG_SCFG_JTAG_A9JE_MASK | REG_SCFG_JTAG_DSPJE_MASK
+        str             r0, [r3]
+
+terminate
+        b               terminate
+}
+
+#include <./../../../../libraries/init/ARM9/crt0_pu.c>
+#include <./../../../../libraries/init/ARM9/crt0_misc_sp.c>

trunk/include/ctr/hw/ARM9/mmap_global.h

@@ -78,7 +78,7 @@ extern  "C" {
 
 #endif // SDK_MG20EMU
 
-#ifndef SDK_MG20EMU
+#if !defined(SDK_MG20EMU) && !defined(SDK_NE1EMU)
 //----------------------------- Private WRAM
 #define HW_PRV_WRAM             0x08000000
 #define HW_PRV_WRAM_END         (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
@@ -89,7 +89,7 @@ extern  "C" {
 #define HW_IOREG_END            0x18000000
 #define HW_REG_BASE             HW_IOREG        // alias
 
-#else // SDK_MG20EMU
+#else // SDK_MG20EMU || SDK_NE1EMU
 //----------------------------- Private WRAM
 #define HW_PRV_WRAM             0x10000000
 #define HW_PRV_WRAM_END         (HW_PRV_WRAM + HW_PRV_WRAM_SIZE)
@@ -100,11 +100,13 @@ extern  "C" {
 #define HW_IOREG_END            0x10000000
 #define HW_REG_BASE             HW_IOREG        // alias
 
+#ifdef SDK_MG20EMU
 #define HW_MG20IOP_REG          0x40000000
 #define HW_MG20IOP_REG_END      0x40100000
-
 #endif // SDK_MG20EMU
 
+#endif // SDK_MG20EMU || SDK_NE1EMU
+
 #define HW_PRV_REG              (HW_IOREG + 0)
 #define HW_AHBP_REG             (HW_IOREG + 0x00100000)
 #define HW_PRV_REG_END          (HW_PRV_REG + HW_PRV_REG_SIZE)