rvtr/ctr_firmware
1
Fork 0
mirror of https://github.com/rvtr/ctr_firmware.git synced 2025-10-31 07:51:08 -04:00
Code Issues Actions Packages Projects Releases Wiki Activity

大半の領域を共有／実行不可属性へ変更。

Browse Source 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@61 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima 2008-12-02 05:47:25 +00:00
parent eeaa276484
commit 668396cf75
1 changed files with 35 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
View File

@ -307,7 +307,7 @@ void stupInitMMUTable( void )
HW_MMU6_APX_NA, HW_MMU6_APX_NA,
HW_MMU6_T1_RGT_STRONG_ORDER, HW_MMU6_T1_RGT_STRONG_ORDER,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, HW_MMU6_T1_SHARED,
HW_MMU6_T1_XN, HW_MMU6_T1_XN,
0); 0);
paddr += HW_MMU6_T1_SEC_SIZE; paddr += HW_MMU6_T1_SEC_SIZE;
@ -321,7 +321,7 @@ void stupInitMMUTable( void )
HW_MMU6_T2_APX_NA, HW_MMU6_T2_APX_NA,
HW_MMU6_T2_LP_RGT_STRONG_ORDER, HW_MMU6_T2_LP_RGT_STRONG_ORDER,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, HW_MMU6_T2_SHARED,
HW_MMU6_T2_SP_XN); HW_MMU6_T2_SP_XN);
} }
@ -337,9 +337,9 @@ void stupInitMMUTable( void )
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_S_RW_U_NA, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, HW_MMU6_T2_LP_RGT_L1C_WB_WA,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, HW_MMU6_T2_SHARED,
FALSE); FALSE);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE; paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
} }
@ -356,8 +356,8 @@ void stupInitMMUTable( void )
HW_MMU6_T1_APX_S_RW_U_NA, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_SHARED_DEV, HW_MMU6_T1_RGT_SHARED_DEV,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, HW_MMU6_T1_SHARED,
FALSE HW_MMU6_T1_XN
); );
paddr += HW_MMU6_T1_SEC_SIZE; paddr += HW_MMU6_T1_SEC_SIZE;
} }
@ -371,7 +371,7 @@ void stupInitMMUTable( void )
HW_MMU6_T1_RGT_NSHARED_DEV, HW_MMU6_T1_RGT_NSHARED_DEV,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, FALSE,
FALSE, HW_MMU6_T1_XN,
0); 0);
// VRAM Region (4MB cached) // VRAM Region (4MB cached)
@ -381,10 +381,10 @@ void stupInitMMUTable( void )
*table++ = HW_MMU6_T1_SEC_PACK( *table++ = HW_MMU6_T1_SEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_S_RW_U_NA, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1L2C_WB_WA, HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, HW_MMU6_T1_SHARED,
FALSE, HW_MMU6_T1_XN,
0); 0);
paddr += HW_MMU6_T1_SEC_SIZE; paddr += HW_MMU6_T1_SEC_SIZE;
} }
@ -400,20 +400,33 @@ void stupInitMMUTable( void )
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_S_RW_U_NA, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_L1L2C_WB_WA, HW_MMU6_T2_LP_RGT_L1C_WB_WA,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, HW_MMU6_T2_SHARED,
FALSE); HW_MMU6_T2_LP_XN);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE; paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
} }
for ( ; paddr < HW_AXI_WRAM_SHARED_END; ) // HW_BROM_MMU_TBL
while ( paddr < HW_BROM_MMU_TBL_END )
{ {
*table++ = HW_MMU6_T2_LP_PACK( *table++ = HW_MMU6_T2_LP_PACK(
paddr, paddr,
HW_MMU6_T2_APX_S_RW_U_NA, HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_SHARED_DEV, HW_MMU6_T2_LP_RGT_SHARED_DEV,
HW_MMU6_T2_GLOBAL, HW_MMU6_T2_GLOBAL,
FALSE, HW_MMU6_T2_SHARED,
HW_MMU6_T2_LP_XN);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
}
// HW_AXI_WRAM_SHARED
while ( paddr < HW_AXI_WRAM_SHARED_END )
{
*table++ = HW_MMU6_T2_LP_PACK(
paddr,
HW_MMU6_T2_APX_S_RW_U_NA,
HW_MMU6_T2_LP_RGT_SHARED_DEV,
HW_MMU6_T2_GLOBAL,
HW_MMU6_T2_SHARED,
FALSE); FALSE);
paddr += HW_MMU6_T2_LP_ALIAS_SIZE; paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
} }
@ -428,23 +441,23 @@ void stupInitMMUTable( void )
*table++ = HW_MMU6_T1_SUSEC_PACK( *table++ = HW_MMU6_T1_SUSEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_S_RW_U_NA, HW_MMU6_T1_APX_S_RW_U_NA,
HW_MMU6_T1_RGT_L1L2C_WB_WA, HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, HW_MMU6_T1_SHARED,
FALSE HW_MMU6_T1_XN
); );
paddr += HW_MMU6_T1_SEC_SIZE; paddr += HW_MMU6_T1_SEC_SIZE;
} }
for ( ; paddr < HW_MAIN_MEM_EX_END; ) while ( paddr < HW_MAIN_MEM_EX_END )
{ {
*table++ = HW_MMU6_T1_SUSEC_PACK( *table++ = HW_MMU6_T1_SUSEC_PACK(
paddr, paddr,
HW_MMU6_T1_APX_ALL, HW_MMU6_T1_APX_ALL,
HW_MMU6_T1_RGT_L1L2C_WB_WA, HW_MMU6_T1_RGT_L1C_WB_WA,
HW_MMU6_T1_GLOBAL, HW_MMU6_T1_GLOBAL,
FALSE, HW_MMU6_T1_SHARED,
FALSE HW_MMU6_T1_XN
); );
paddr += HW_MMU6_T1_SEC_SIZE; paddr += HW_MMU6_T1_SEC_SIZE;
} }