From 668396cf75c607914f6c1ecb34293cd1d404b743 Mon Sep 17 00:00:00 2001
From: nakasima <nakasima@b871894f-2f95-9b40-918c-086798483c85>
Date: Tue, 2 Dec 2008 05:47:25 +0000
Subject: [PATCH] =?UTF-8?q?=E5=A4=A7=E5=8D=8A=E3=81=AE=E9=A0=98=E5=9F=9F?=
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 =?UTF-8?q?=E5=8F=AF=E5=B1=9E=E6=80=A7=E3=81=B8=E5=A4=89=E6=9B=B4=E3=80=82?=
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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@61 b871894f-2f95-9b40-918c-086798483c85
---
 .../build/libraries/init/ARM11/crt0_secure.c  | 57 ++++++++++++-------
 1 file changed, 35 insertions(+), 22 deletions(-)

diff --git a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
index fb8d11b..5cb9d67 100644
--- a/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
+++ b/trunk/bootrom/build/libraries/init/ARM11/crt0_secure.c
@@ -307,7 +307,7 @@ void stupInitMMUTable( void )
                   HW_MMU6_APX_NA,
                   HW_MMU6_T1_RGT_STRONG_ORDER,
                   HW_MMU6_T1_GLOBAL,
-                  FALSE,
+                  HW_MMU6_T1_SHARED,
                   HW_MMU6_T1_XN,
                   0);
         paddr += HW_MMU6_T1_SEC_SIZE;
@@ -321,7 +321,7 @@ void stupInitMMUTable( void )
                   HW_MMU6_T2_APX_NA,
                   HW_MMU6_T2_LP_RGT_STRONG_ORDER,
                   HW_MMU6_T2_GLOBAL,
-                  FALSE,
+                  HW_MMU6_T2_SHARED,
                   HW_MMU6_T2_SP_XN);
     }
 
@@ -337,9 +337,9 @@ void stupInitMMUTable( void )
         *table++ = HW_MMU6_T2_LP_PACK(
                   paddr,
                   HW_MMU6_T2_APX_S_RW_U_NA,
-                  HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
+                  HW_MMU6_T2_LP_RGT_L1C_WB_WA,
                   HW_MMU6_T2_GLOBAL,
-                  FALSE,
+                  HW_MMU6_T2_SHARED,
                   FALSE);
         paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
     }
@@ -356,8 +356,8 @@ void stupInitMMUTable( void )
                   HW_MMU6_T1_APX_S_RW_U_NA,
                   HW_MMU6_T1_RGT_SHARED_DEV,
                   HW_MMU6_T1_GLOBAL,
-                  FALSE,
-                  FALSE
+                  HW_MMU6_T1_SHARED,
+                  HW_MMU6_T1_XN
                   );
         paddr += HW_MMU6_T1_SEC_SIZE;
     }
@@ -371,7 +371,7 @@ void stupInitMMUTable( void )
                   HW_MMU6_T1_RGT_NSHARED_DEV,
                   HW_MMU6_T1_GLOBAL,
                   FALSE,
-                  FALSE,
+                  HW_MMU6_T1_XN,
                   0);
 
     // VRAM Region (4MB cached)
@@ -381,10 +381,10 @@ void stupInitMMUTable( void )
         *table++ = HW_MMU6_T1_SEC_PACK(
                   paddr,
                   HW_MMU6_T1_APX_S_RW_U_NA,
-                  HW_MMU6_T1_RGT_L1L2C_WB_WA,
+                  HW_MMU6_T1_RGT_L1C_WB_WA,
                   HW_MMU6_T1_GLOBAL,
-                  FALSE,
-                  FALSE,
+                  HW_MMU6_T1_SHARED,
+                  HW_MMU6_T1_XN,
                   0);
         paddr += HW_MMU6_T1_SEC_SIZE;
     }
@@ -400,20 +400,33 @@ void stupInitMMUTable( void )
         *table++ = HW_MMU6_T2_LP_PACK(
                   paddr,
                   HW_MMU6_T2_APX_S_RW_U_NA,
-                  HW_MMU6_T2_LP_RGT_L1L2C_WB_WA,
+                  HW_MMU6_T2_LP_RGT_L1C_WB_WA,
                   HW_MMU6_T2_GLOBAL,
-                  FALSE,
-                  FALSE);
+                  HW_MMU6_T2_SHARED,
+                  HW_MMU6_T2_LP_XN);
         paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
     }
-    for ( ; paddr < HW_AXI_WRAM_SHARED_END; )
+    // HW_BROM_MMU_TBL
+    while ( paddr < HW_BROM_MMU_TBL_END )
     {
         *table++ = HW_MMU6_T2_LP_PACK(
                   paddr,
                   HW_MMU6_T2_APX_S_RW_U_NA,
                   HW_MMU6_T2_LP_RGT_SHARED_DEV,
                   HW_MMU6_T2_GLOBAL,
-                  FALSE,
+                  HW_MMU6_T2_SHARED,
+                  HW_MMU6_T2_LP_XN);
+        paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
+    }
+    // HW_AXI_WRAM_SHARED
+    while ( paddr < HW_AXI_WRAM_SHARED_END )
+    {
+        *table++ = HW_MMU6_T2_LP_PACK(
+                  paddr,
+                  HW_MMU6_T2_APX_S_RW_U_NA,
+                  HW_MMU6_T2_LP_RGT_SHARED_DEV,
+                  HW_MMU6_T2_GLOBAL,
+                  HW_MMU6_T2_SHARED,
                   FALSE);
         paddr += HW_MMU6_T2_LP_ALIAS_SIZE;
     }
@@ -428,23 +441,23 @@ void stupInitMMUTable( void )
         *table++ = HW_MMU6_T1_SUSEC_PACK(
                   paddr,
                   HW_MMU6_T1_APX_S_RW_U_NA,
-                  HW_MMU6_T1_RGT_L1L2C_WB_WA,
+                  HW_MMU6_T1_RGT_L1C_WB_WA,
                   HW_MMU6_T1_GLOBAL,
-                  FALSE,
-                  FALSE
+                  HW_MMU6_T1_SHARED,
+                  HW_MMU6_T1_XN
                   );
         paddr += HW_MMU6_T1_SEC_SIZE;
     }
-    for ( ; paddr < HW_MAIN_MEM_EX_END; )
+    while ( paddr < HW_MAIN_MEM_EX_END )
     {
 
         *table++ = HW_MMU6_T1_SUSEC_PACK(
                   paddr,
                   HW_MMU6_T1_APX_ALL,
-                  HW_MMU6_T1_RGT_L1L2C_WB_WA,
+                  HW_MMU6_T1_RGT_L1C_WB_WA,
                   HW_MMU6_T1_GLOBAL,
-                  FALSE,
-                  FALSE
+                  HW_MMU6_T1_SHARED,
+                  HW_MMU6_T1_XN
                   );
         paddr += HW_MMU6_T1_SEC_SIZE;
     }