mirror of
https://github.com/rvtr/ctr_firmware.git
synced 2025-10-31 07:51:08 -04:00
キャッシュライブラリ追加。
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@132 b871894f-2f95-9b40-918c-086798483c85
This commit is contained in:
nakasima
parent
85dd27858e
commit
48bd2a2dc2
@ -117,7 +117,7 @@ asm void STUPi_EnableTCM( void )
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// プロテクションユニット/キャッシュ/TCM ディセーブル
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \
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ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \
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| HW_C1_LD_INTERWORK_DISABLE \
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@ -103,7 +103,7 @@ asm void STUPi_InitCP15(void)
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// プロテクションユニット/キャッシュ/TCM ディセーブル
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \
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ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \
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| HW_C1_LD_INTERWORK_DISABLE \
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@ -249,9 +249,9 @@ asm void STUPi_InitCP15(void)
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// システム制御コプロセッサ マスター設定
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//
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mrc p15, 0, r0, c1, c0, 0
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ldr r1,=HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE | HW_C1_CACHE_ROUND_ROBIN \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \
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ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \
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| HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \
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| HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \
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| HW_C1_PROTECT_UNIT_ENABLE
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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@ -28,11 +28,12 @@ BROM_CODEGEN_ALL ?= TRUE
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SRCDIR = . ../common
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SRCS = \
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os_alarm.c \
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os_cache.c \
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os_init.c \
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os_system.c \
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os_timer.c \
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os_tick.c \
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os_alarm.c \
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os_irqHandler.c \
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os_interrupt.c \
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os_interrupt_common.c \
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@ -31,11 +31,12 @@ BROM_PROC = ARM9
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SRCDIR = . ../common
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SRCS = \
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os_alarm.c \
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os_cache.c \
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os_init.c \
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os_system.c \
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os_timer.c \
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os_tick.c \
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os_alarm.c \
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os_irqHandler.c \
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os_interrupt.c \
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os_interrupt_common.c \
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854
trunk/bootrom/build/libraries/os/common/os_cache.c
Normal file
854
trunk/bootrom/build/libraries/os/common/os_cache.c
Normal file
@ -0,0 +1,854 @@
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/*---------------------------------------------------------------------------*
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Project: CtrBrom - libraries - OS
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File: os_cache.c
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Copyright 2008 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: $
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <brom/os.h>
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#include <brom/code32.h>
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//===========================================================================
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// DATA CACHE CONTROL
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//===========================================================================
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/*---------------------------------------------------------------------------*
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Name: osEnableDCache
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Description: enable data cache
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Arguments: None
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Returns: previous state
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*---------------------------------------------------------------------------*/
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ASM BOOL osEnableDCache( void )
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{
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PRESERVE8
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mrc p15, 0, r1, c1, c0, 0
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and r0, r1, #HW_C1_DC_ENABLE
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mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT
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orr r1, r1, #HW_C1_DC_ENABLE
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mcr p15, 0, r1, c1, c0, 0
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osDisableDCache
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Description: disable data cache
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Arguments: None
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Returns: previous stats
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*---------------------------------------------------------------------------*/
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ASM BOOL osDisableDCache( void )
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{
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mrc p15, 0, r1, c1, c0, 0
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and r0, r1, #HW_C1_DC_ENABLE
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mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT
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bic r1, r1, #HW_C1_DC_ENABLE
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mcr p15, 0, r1, c1, c0, 0
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osRestoreDCache
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Description: set state of data cache
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Arguments: data cache state to be set
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Returns: previous state
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*---------------------------------------------------------------------------*/
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ASM BOOL osRestoreDCache( BOOL enable )
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{
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//---- 引数処理
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cmp r0, #0
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moveq r2, #0
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movne r2, #HW_C1_DC_ENABLE
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mrc p15, 0, r1, c1, c0, 0
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and r0, r1, #HW_C1_DC_ENABLE
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mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT
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bic r1, r1, #HW_C1_DC_ENABLE
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orr r1, r1, r2
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mcr p15, 0, r1, c1, c0, 0
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bx lr
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}
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//===========================================================================
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// DATA CACHE (for all range)
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//===========================================================================
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/*---------------------------------------------------------------------------*
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Name: osInvalidateDCacheAll
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Description: invalidate all data cache
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Arguments: None.
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osInvalidateDCacheAll( void )
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{
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mov r0, #0
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mcr p15, 0, r0, c7, c6, 0
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osStoreDCacheAll
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Description: clean all data cache
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(write cache data to memory)
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Arguments: None.
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osStoreDCacheAll( void )
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{
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mov r1, #0
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LSYM(1)
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mov r0, #0
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LSYM(2)
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orr r2, r1, r0
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mcr p15, 0, r2, c7, c10, 2
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, #HW_DC_SIZE/4
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blt BSYM(2)
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add r1, r1, #1<<HW_C7_CACHE_WAY_NO_SFT
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cmp r1, #0
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bne BSYM(1)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osFlushDCacheAll
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Description: clean and invalidate all data cache
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(write cache data to memory, and invalidate cache)
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Arguments: None.
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osFlushDCacheAll( void )
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{
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mov r12, #0
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mov r1, #0 // r1: セットＮｏカウンタ（0 ～ 3）
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LSYM(1)
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mov r0, #0 // r0: ラインカウンタ（0 ～ DCACHE_SIZE/4）
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LSYM(2)
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orr r2, r1, r0
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mcr p15, 0, r12, c7, c10, 4 /* wait write buffer empty */
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mcr p15, 0, r2, c7, c14, 2 /* flush */
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, #HW_DC_SIZE/4
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blt BSYM(2)
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add r1, r1, #1<<HW_C7_CACHE_WAY_NO_SFT
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cmp r1, #0
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bne BSYM(1)
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bx lr
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}
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//===========================================================================
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// DATA CACHE (for specified range)
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//===========================================================================
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/*---------------------------------------------------------------------------*
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Name: osInvalidateDCacheRange
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Description: invalidate data cache in specified range
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osInvalidateDCacheRange( void* startAddr, u32 nBytes )
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{
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add r1, r1, r0
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bic r0, r0, #HW_CACHE_LINE_SIZE - 1
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LSYM(1)
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mcr p15, 0, r0, c7, c6, 1
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, r1
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blt BSYM(1)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osStoreDCacheRange
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Description: clean data cache in specified range
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(write cache data to memory)
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osStoreDCacheRange( void* startAddr, u32 nBytes )
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{
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add r1, r1, r0
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bic r0, r0, #HW_CACHE_LINE_SIZE - 1
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LSYM(1)
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mcr p15, 0, r0, c7, c10, 1
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, r1
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blt BSYM(1)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osFlushDCacheRange
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Description: clean and invalidate data cache in specified range
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(write cache data to memory, and invalidate cache)
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osFlushDCacheRange( void* startAddr, u32 nBytes )
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{
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mov r12, #0
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add r1, r1, r0
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bic r0, r0, #HW_CACHE_LINE_SIZE - 1
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LSYM(1)
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mcr p15, 0, r12, c7, c10, 4 /* wait write buffer empty */
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mcr p15, 0, r0, c7, c14, 1 /* flush */
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, r1
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blt BSYM(1)
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bx lr
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}
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/*---------------------------------------------------------------------------*
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Name: osInvalidateDCacheRangeOrAll
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Description: invalidate data cache in specified range or all
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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void osInvalidateDCacheRangeOrAll( void* startAddr, u32 nBytes )
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{
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if ( nBytes < HW_DC_SIZE )
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{
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osInvalidateDCacheRange( startAddr, nBytes );
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}
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else
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{
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osInvalidateDCacheAll();
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}
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}
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/*---------------------------------------------------------------------------*
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Name: osStoreDCacheRangeOrAll
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Description: clean data cache in specified range
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(write cache data to memory)
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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void osStoreDCacheRangeOrAll( void* startAddr, u32 nBytes )
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{
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if ( nBytes < HW_DC_SIZE )
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{
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osStoreDCacheRange( startAddr, nBytes );
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}
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else
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{
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osStoreDCacheAll();
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}
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}
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/*---------------------------------------------------------------------------*
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Name: osFlushDCacheRangeOrAll
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Description: clean data cache in specified range
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(write cache data to memory)
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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void osFlushDCacheRangeOrAll( void* startAddr, u32 nBytes )
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{
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if ( nBytes < HW_DC_SIZE )
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{
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osFlushDCacheRange( startAddr, nBytes );
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}
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else
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{
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osFlushDCacheAll();
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}
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}
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//===========================================================================
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// DATA CACHE (for specified range)
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//===========================================================================
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/*---------------------------------------------------------------------------*
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Name: osLockdownDCacheRange
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Description: lock specified area to prevent not to release data cache
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Arguments: startAddr start address
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nBytes size (in byte)
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Returns: None.
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*---------------------------------------------------------------------------*/
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ASM void osLockdownDCacheRange( void* startAddr, u32 nBytes )
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{
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#ifdef SDK_ARM9
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INASM_EXTERN( osDisableInterrupts )
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INASM_EXTERN( osRestoreInterrupts )
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add r1, r1, r0 // r1: エンドアドレス
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bic r0, r0, #HW_CACHE_LINE_SIZE - 1
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mrc p15, 0, r3, c9, c0, 0
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and r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK // r3: カレントセットＮｏ
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cmp r3, #3 // ３セットをロックダウンしていればエラー
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mvneq r0, #0
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bxeq lr
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stmfd sp!, { lr, r0, r1 }
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ldr r0, =osDisableInterrupts
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blx r0
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mov r2, r0
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ldmfd sp!, { lr, r0, r1 }
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orr r3, r3, #HW_C9_LOCKDOWN_LOAD_MODE // キャッシュロックダウン・ロードモード
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mcr p15, 0, r3, c9, c0, 0
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LSYM(1)
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mcr p15, 0, r0, c7, c14, 1 // キャッシュに乗っているデータを一旦クリーン／無効化する
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ldr r12, [r0] // データを読み込みキャッシュに乗せる
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add r0, r0, #HW_CACHE_LINE_SIZE
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cmp r0, r1
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blt BSYM(1)
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add r3, r3, #1 // キャッシュ通常モード ＆ セットＮｏのインクリメント
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bic r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE
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mcr p15, 0, r3, c9, c0, 0
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stmfd sp!, { lr }
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mov r0, r2
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ldr r1, =osRestoreInterrupts
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blx r1
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ldmfd sp!, { lr }
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bx lr
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#else // SDK_ARM11
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#endif
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}
|
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|
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|
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/*---------------------------------------------------------------------------*
|
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Name: osUnlockdownDCacheAll
|
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|
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Description: unlock all data cache to enable to release
|
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|
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Arguments: none.
|
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|
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Returns: None.
|
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*---------------------------------------------------------------------------*/
|
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|
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ASM void osUnlockdownDCacheAll( void )
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{
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#ifdef SDK_ARM9
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mov r3, #0
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mcr p15, 0, r3, c9, c0, 0
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bx lr
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#else // SDK_ARM11
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#endif
|
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}
|
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|
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/*---------------------------------------------------------------------------*
|
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Name: osUnlockdownDCache
|
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|
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Description: unlock any data cache to enable to release
|
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|
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Arguments: num - specify number of datablock to unlock.
|
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|
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Returns: None.
|
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*---------------------------------------------------------------------------*/
|
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|
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ASM void osUnlockdownDCache( u32 num )
|
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{
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#ifdef SDK_ARM9
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mrc p15, 0, r3, c9, c0, 0
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and r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK
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subs r3, r3, r0
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movmi r3, #0
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mcr p15, 0, r3, c9, c0, 0
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bx lr
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#else // SDK_ARM11
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#endif
|
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}
|
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|
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|
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/*---------------------------------------------------------------------------*
|
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Name: osWaitWriteBufferEmpty
|
||||
|
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Description: wait till write buffer becomes to be empty
|
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|
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Arguments: None.
|
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|
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Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
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|
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ASM void osWaitWriteBufferEmpty( void )
|
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{
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4
|
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bx lr
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osTouchDCacheRange
|
||||
|
||||
Description: include specified area to data cache in advance
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osTouchDCacheRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
add r1, r1, r0
|
||||
bic r0, r0, #HW_CACHE_LINE_SIZE - 1
|
||||
|
||||
LSYM(1)
|
||||
#ifdef SDK_ARM11
|
||||
pld [r0]
|
||||
#else // SDK_ARM9
|
||||
ldr r2, [r0]
|
||||
#endif // SDK_ARM9
|
||||
add r0, r0, #HW_CACHE_LINE_SIZE
|
||||
cmp r0, r1
|
||||
blt BSYM(1)
|
||||
bx lr
|
||||
}
|
||||
|
||||
#ifdef SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osKeepDataAccessOrder
|
||||
|
||||
Description: keep data access order
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osKeepDataAccessOrder( void )
|
||||
{
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c10, 5
|
||||
bx lr
|
||||
}
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// INSTRUCTION CACHE CONTROL
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableICache
|
||||
|
||||
Description: enable instruction cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous state
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM BOOL osEnableICache( void )
|
||||
{
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
and r0, r1, #HW_C1_IC_ENABLE
|
||||
mov r0, r0, LSR #HW_C1_IC_ENABLE_SFT
|
||||
orr r1, r1, #HW_C1_IC_ENABLE
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableICache
|
||||
|
||||
Description: disable instruction cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous stats
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM BOOL osDisableICache( void )
|
||||
{
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
and r0, r1, #HW_C1_IC_ENABLE
|
||||
mov r0, r0, LSR #HW_C1_IC_ENABLE_SFT
|
||||
bic r1, r1, #HW_C1_IC_ENABLE
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreICache
|
||||
|
||||
Description: set state of instruction cache
|
||||
|
||||
Arguments: instruction cache state to be set
|
||||
|
||||
Returns: previous stats
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM BOOL osRestoreICache( BOOL enable )
|
||||
{
|
||||
//---- 引数処理
|
||||
cmp r0, #0
|
||||
moveq r2, #0
|
||||
movne r2, #HW_C1_IC_ENABLE
|
||||
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
and r0, r1, #HW_C1_IC_ENABLE
|
||||
mov r0, r0, LSR #HW_C1_IC_ENABLE_SFT
|
||||
bic r1, r1, #HW_C1_IC_ENABLE
|
||||
orr r1, r1, r2
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
bx lr
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// INSTRUCTION CACHE
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheAll
|
||||
|
||||
Description: invalidate all instruction cache
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osInvalidateICacheAll( void )
|
||||
{
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c5, 0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheRange
|
||||
|
||||
Description: invalidate instruction cache in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osInvalidateICacheRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
add r1, r1, r0
|
||||
bic r0, r0, #HW_CACHE_LINE_SIZE - 1
|
||||
|
||||
LSYM(1)
|
||||
mcr p15, 0, r0, c7, c5, 1
|
||||
add r0, r0, #HW_CACHE_LINE_SIZE
|
||||
cmp r0, r1
|
||||
blt BSYM(1)
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheRangeOrAll
|
||||
|
||||
Description: invalidate instruction cache in specified range or all
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void osInvalidateICacheRangeOrAll( void* startAddr, u32 nBytes )
|
||||
{
|
||||
if ( nBytes < HW_DC_SIZE )
|
||||
{
|
||||
osInvalidateICacheRange( startAddr, nBytes );
|
||||
}
|
||||
else
|
||||
{
|
||||
osInvalidateICacheAll();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef SDK_ARM9
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osLockdownICacheRange
|
||||
|
||||
Description: lock specified area to prevent not to release instruction cache
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osLockdownICacheRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
INASM_EXTERN( osDisableInterrupts )
|
||||
INASM_EXTERN( osRestoreInterrupts )
|
||||
|
||||
add r1, r1, r0 // r1: エンドアドレス
|
||||
bic r0, r0, #HW_CACHE_LINE_SIZE - 1
|
||||
mrc p15, 0, r3, c9, c0, 1
|
||||
and r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK // r3: カレントセットＮｏ
|
||||
cmp r3, #3 // ３セットをロックダウンしていればエラー
|
||||
mvneq r0, #0
|
||||
bxeq lr
|
||||
|
||||
stmfd sp!, { lr, r0, r1 }
|
||||
ldr r0, =osDisableInterrupts
|
||||
blx r0
|
||||
mov r2, r0
|
||||
ldmfd sp!, { lr, r0, r1 }
|
||||
|
||||
orr r3, r3, #HW_C9_LOCKDOWN_LOAD_MODE // キャッシュロックダウン・ロードモード
|
||||
mcr p15, 0, r3, c9, c0, 1
|
||||
|
||||
LSYM(1)
|
||||
mcr p15, 0, r0, c7, c5, 1 // キャッシュから一旦無効化
|
||||
mcr p15, 0, r0, c7, c13, 1 // プリフェッチ
|
||||
add r0, r0, #HW_CACHE_LINE_SIZE
|
||||
cmp r0, r1
|
||||
blt BSYM(1)
|
||||
add r3, r3, #1 // キャッシュ通常モード ＆ セットＮｏのインクリメント
|
||||
bic r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE
|
||||
mcr p15, 0, r3, c9, c0, 1
|
||||
|
||||
stmfd sp!, { lr }
|
||||
mov r0, r2
|
||||
ldr r1, =osRestoreInterrupts
|
||||
blx r1
|
||||
ldmfd sp!, { lr }
|
||||
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osUnlockdownICacheAll
|
||||
|
||||
Description: unlock all instruction cache to enable to release
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osUnlockdownICacheAll( void )
|
||||
{
|
||||
mov r3, #0
|
||||
mcr p15, 0, r3, c9, c0, 1
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osUnlockdownICache
|
||||
|
||||
Description: unlock any instruction cache to enable to release
|
||||
|
||||
Arguments: num - specify number of datablock to unlock.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osUnlockdownICache( u32 num )
|
||||
{
|
||||
mrc p15, 0, r3, c9, c0, 1
|
||||
and r3, r3, #HW_C9_LOCKDOWN_WAY_NO_MASK
|
||||
subs r3, r3, r0
|
||||
movmi r3, #0
|
||||
mcr p15, 0, r3, c9, c0, 1
|
||||
bx lr
|
||||
}
|
||||
|
||||
#else // SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osPrefetchICacheRange
|
||||
|
||||
Description: include specified area to instruction cache in advance
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osPrefetchICacheRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
add r1, r1, r0
|
||||
bic r0, r0, #HW_CACHE_LINE_SIZE - 1
|
||||
|
||||
LSYM(1)
|
||||
mcr p15, 0, r0, c7, c13, 1
|
||||
add r0, r0, #HW_CACHE_LINE_SIZE
|
||||
cmp r0, r1
|
||||
blt BSYM(1)
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateInstPrefetchBuffer
|
||||
|
||||
Description: invalidate instruction prefetch buffer
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osInvalidateInstPrefetchBuffer( void )
|
||||
{
|
||||
mov r3, #0
|
||||
mcr p15, 0, r3, c7, c5, 4
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDoInstMemoryBarrierAll
|
||||
|
||||
Description: do all Instruction Memory Barrier
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void osDoInstMemoryBarrierAll( void )
|
||||
{
|
||||
osStoreDCacheAll();
|
||||
osWaitWriteBufferEmpty();
|
||||
osInvalidateICacheAll();
|
||||
osInvalidateInstPrefetchBuffer();
|
||||
osInvalidateBCacheAll();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDoInstMemoryBarrierRange
|
||||
|
||||
Description: do Instruction Memory Barrier in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void osDoInstMemoryBarrierRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
osStoreDCacheRange( startAddr, nBytes );
|
||||
osWaitWriteBufferEmpty();
|
||||
osInvalidateICacheRange( startAddr, nBytes );
|
||||
osInvalidateInstPrefetchBuffer();
|
||||
osInvalidateBCacheRange( startAddr, nBytes );
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// BRANCH TARGET ADDRESS CACHE
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateBCacheAll
|
||||
|
||||
Description: invalidate all branch target address cache
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osInvalidateBCacheAll( void )
|
||||
{
|
||||
mov r3, #0
|
||||
mcr p15, 0, r3, c7, c5, 6
|
||||
bx lr
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateBCacheRange
|
||||
|
||||
Description: invalidate branch target address cache in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
ASM void osInvalidateBCacheRange( void* startAddr, u32 nBytes )
|
||||
{
|
||||
add r1, r1, r0
|
||||
bic r0, r0, #1
|
||||
|
||||
LSYM(1)
|
||||
mcr p15, 0, r0, c7, c5, 7
|
||||
add r0, r0, #2
|
||||
cmp r0, r1
|
||||
blt BSYM(1)
|
||||
bx lr
|
||||
}
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
|
||||
#include <brom/codereset.h>
|
||||
|
||||
@ -37,6 +37,7 @@ extern "C" {
|
||||
#include <brom/os/common/thread.h>
|
||||
#include <brom/os/common/timer.h>
|
||||
#include <brom/os/common/interrupt.h>
|
||||
#include <brom/os/common/cache.h>
|
||||
#if 0
|
||||
#include <brom/os/common/systemWork.h>
|
||||
#include <brom/os/common/exception.h>
|
||||
|
||||
549
trunk/bootrom/include/brom/os/common/cache.h
Normal file
549
trunk/bootrom/include/brom/os/common/cache.h
Normal file
@ -0,0 +1,549 @@
|
||||
/*---------------------------------------------------------------------------*
|
||||
Project: CtrBrom - OS - include
|
||||
File: cache.h
|
||||
|
||||
Copyright 2008 Nintendo. All rights reserved.
|
||||
|
||||
These coded instructions, statements, and computer programs contain
|
||||
proprietary information of Nintendo of America Inc. and/or Nintendo
|
||||
Company Ltd., and are protected by Federal copyright law. They may
|
||||
not be disclosed to third parties or copied or duplicated in any form,
|
||||
in whole or in part, without the prior written consent of Nintendo.
|
||||
|
||||
$Date:: $
|
||||
$Rev$
|
||||
$Author$
|
||||
*---------------------------------------------------------------------------*/
|
||||
#ifndef BROM_OS_CACHE_H_
|
||||
#define BROM_OS_CACHE_H_
|
||||
|
||||
#include <brom/misc.h>
|
||||
#include <brom/types.h>
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// DATA CACHE CONTROL
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableDCache
|
||||
|
||||
Description: enable data cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous state
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osEnableDCache( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableDCache
|
||||
|
||||
Description: disable data cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous stats
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osDisableDCache( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreDCache
|
||||
|
||||
Description: set state of data cache
|
||||
|
||||
Arguments: data cache state to be set
|
||||
|
||||
Returns: previous state
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osRestoreDCache( BOOL enable );
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// DATA CACHE (for all range)
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateDCacheAll
|
||||
|
||||
Description: invalidate all data cache
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateDCacheAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osStoreDCacheAll
|
||||
|
||||
Description: clean all data cache
|
||||
(write cache data to memory)
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osStoreDCacheAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osFlushDCacheAll
|
||||
|
||||
Description: clean and invalidate all data cache
|
||||
(write cache data to memory, and invalidate cache)
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osFlushDCacheAll( void );
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// DATA CACHE (for specified range)
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateDCacheRange
|
||||
|
||||
Description: invalidate data cache in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateDCacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osStoreDCacheRange
|
||||
|
||||
Description: clean data cache in specified range
|
||||
(write cache data to memory)
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osStoreDCacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osFlushDCacheRange
|
||||
|
||||
Description: clean and invalidate data cache in specified range
|
||||
(write cache data to memory, and invalidate cache)
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osFlushDCacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateDCacheRangeOrAll
|
||||
|
||||
Description: invalidate data cache in specified range or all
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateDCacheRangeOrAll( void* startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osStoreDCacheRangeOrAll
|
||||
|
||||
Description: clean data cache in specified range or all
|
||||
(write cache data to memory)
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osStoreDCacheRangeOrAll( void* startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osFlushDCacheRangeOrAll
|
||||
|
||||
Description: clean data cache in specified range or all
|
||||
(write cache data to memory)
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osFlushDCacheRangeOrAll( void* startAddr, u32 nBytes );
|
||||
|
||||
//===========================================================================
|
||||
// DATA CACHE (for specified range)
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osLockdownDCacheRange
|
||||
|
||||
Description: lock specified area to prevent not to release data cache
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osLockdownDCacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osUnlockdownDCacheAll
|
||||
|
||||
Description: unlock all data cache to enable to release
|
||||
|
||||
Arguments: none.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osUnlockdownDCacheAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: dcUnlockdown
|
||||
|
||||
Description: unlock any data cache to enable to release
|
||||
|
||||
Arguments: num - specify number of datablock to unlock.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osUnlockdownDCache( u32 num );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osWaitWriteBufferEmpty
|
||||
|
||||
Description: wait till write buffer becomes to be empty
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osWaitWriteBufferEmpty( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osTouchDCacheRange
|
||||
|
||||
Description: include specified area to data cache in advance
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osTouchDCacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
#ifdef SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osKeepDataAccessOrder
|
||||
|
||||
Description: keep data access order
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osKeepDataAccessOrder( void );
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// ALIAS OF DATA CACHE function
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osCleanDCacheAll
|
||||
|
||||
Description: alias for osStoreDcacheAll
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static inline void osCleanDCacheAll( void )
|
||||
{
|
||||
osStoreDCacheAll();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osCleanAndInvalidateDCacheAll
|
||||
|
||||
Description: alias for osFlushDCacheAll
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static inline void osCleanAndInvalidateDCacheAll( void )
|
||||
{
|
||||
osFlushDCacheAll();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osCleanDCacheRange
|
||||
|
||||
Description: alias for osStoreDCacheRange
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static inline void osCleanDCacheRange( void *startAddr, u32 nBytes )
|
||||
{
|
||||
osStoreDCacheRange( startAddr, nBytes );
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osCleanAndInvalidateDCacheRange
|
||||
|
||||
Description: alias for osFlushDCacheRange
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static inline void osCleanAndInvalidateDCacheRange( void *startAddr, u32 nBytes )
|
||||
{
|
||||
osFlushDCacheRange( startAddr, nBytes );
|
||||
}
|
||||
|
||||
#ifdef SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osPreloadDCacheRange
|
||||
|
||||
Description: alias for osTouchDCacheRange
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
static inline void osPreloadDCacheRange( void *startAddr, u32 nBytes )
|
||||
{
|
||||
osTouchDCacheRange( startAddr, nBytes );
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDoDataMemoryBarrier
|
||||
|
||||
Description: Do Data Memory Barrier
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: None
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
static inline void osDoDataMemoryBarrier( void )
|
||||
{
|
||||
osKeepDataAccessOrder();
|
||||
}
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
//===========================================================================
|
||||
// INSTRUCTION CACHE CONTROL
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osEnableICache
|
||||
|
||||
Description: enable instruction cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous state
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osEnableICache( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDisableICache
|
||||
|
||||
Description: disable instruction cache
|
||||
|
||||
Arguments: None
|
||||
|
||||
Returns: previous stats
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osDisableICache( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osRestoreICache
|
||||
|
||||
Description: set state of instruction cache
|
||||
|
||||
Arguments: instruction cache state to be set
|
||||
|
||||
Returns: previous stats
|
||||
*---------------------------------------------------------------------------*/
|
||||
BOOL osRestoreICache( BOOL enable );
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// INSTRUCTION CACHE
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheAll
|
||||
|
||||
Description: invalidate all instruction cache
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateICacheAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheRange
|
||||
|
||||
Description: invalidate instruction cache in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateICacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateICacheRangeOrAll
|
||||
|
||||
Description: invalidate instruction cache in specified range or all
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateICacheRangeOrAll( void* startAddr, u32 nBytes );
|
||||
|
||||
#ifdef SDK_ARM9
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osLockdownICacheRange
|
||||
|
||||
Description: lock specified area to prevent not to release instruction cache
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osLockdownICacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osUnlockdownICache
|
||||
|
||||
Description: unlock any instruction cache to enable to release
|
||||
|
||||
Arguments: num - specify number of datablock to unlock.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osUnlockdownICache( u32 num );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osUnlockdownICacheAll
|
||||
|
||||
Description: unlock all instruction cache to enable to release
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osUnlockdownICacheAll( void );
|
||||
|
||||
#else // SDK_ARM11
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osPrefetchICacheRange
|
||||
|
||||
Description: include specified area to instruction cache in advance
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osPrefetchICacheRange( void *startAddr, u32 nBytes );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateInstPrefetchBuffer
|
||||
|
||||
Description: invalidate instruction prefetch buffer
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateInstPrefetchBuffer( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDoInstMemoryBarrierAll
|
||||
|
||||
Description: do all Instruction Memory Barrier
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osDoInstMemoryBarrierAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osDoInstMemoryBarrierRange
|
||||
|
||||
Description: do Instruction Memory Barrier in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osDoInstMemoryBarrierRange( void* startAddr, u32 nBytes );
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// BRANCH TARGET ADDRESS CACHE
|
||||
//===========================================================================
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateBCacheAll
|
||||
|
||||
Description: invalidate all branch target address cache
|
||||
|
||||
Arguments: None.
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateBCacheAll( void );
|
||||
|
||||
/*---------------------------------------------------------------------------*
|
||||
Name: osInvalidateBCacheRange
|
||||
|
||||
Description: invalidate branch target address cache in specified range
|
||||
|
||||
Arguments: startAddr start address
|
||||
nBytes size (in byte)
|
||||
|
||||
Returns: None.
|
||||
*---------------------------------------------------------------------------*/
|
||||
void osInvalidateBCacheRange( void* startAddr, u32 nBytes );
|
||||
|
||||
#endif // SDK_ARM11
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif // BROM_OS_CACHE_H_
|
||||
@ -28,8 +28,8 @@ extern "C" {
|
||||
#define HW_CPU_CLOCK_ARM9 (67027964 * 2)
|
||||
#define HW_CPU_CLOCK HW_CPU_CLOCK_ARM9
|
||||
|
||||
#define HW_ICACHE_SIZE 0x2000 // 命令キャッシュ
|
||||
#define HW_DCACHE_SIZE 0x1000 // データキャッシュ
|
||||
#define HW_IC_SIZE 0x2000 // 命令キャッシュ
|
||||
#define HW_DC_SIZE 0x1000 // データキャッシュ
|
||||
#define HW_CACHE_LINE_SIZE 32
|
||||
|
||||
#define HW_SYSTEM_CLOCK 33514000 // 正確には33513982?
|
||||
@ -52,14 +52,14 @@ extern "C" {
|
||||
#define HW_C1_CACHE_PSEUDO_RANDOM 0x00000000 // 擬似ランダム
|
||||
#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // 例外ベクタ 上位アドレス（こちらに設定して下さい）
|
||||
#define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // 下位アドレス
|
||||
#define HW_C1_ICACHE_ENABLE 0x00001000 // 命令キャッシュ イネーブル
|
||||
#define HW_C1_DCACHE_ENABLE 0x00000004 // データキャッシュ イネーブル
|
||||
#define HW_C1_IC_ENABLE 0x00001000 // 命令キャッシュ イネーブル
|
||||
#define HW_C1_DC_ENABLE 0x00000004 // データキャッシュ イネーブル
|
||||
#define HW_C1_LITTLE_ENDIAN 0x00000000 // リトルエンディアン
|
||||
#define HW_C1_BIG_ENDIAN 0x00000080 // ビッグエンディアン
|
||||
#define HW_C1_PROTECT_UNIT_ENABLE 0x00000001 // プロテクションユニット イネーブル
|
||||
|
||||
#define HW_C1_ICACHE_ENABLE_SHIFT 12
|
||||
#define HW_C1_DCACHE_ENABLE_SHIFT 2
|
||||
#define HW_C1_IC_ENABLE_SFT 12
|
||||
#define HW_C1_DC_ENABLE_SFT 2
|
||||
|
||||
|
||||
// レジスタ２（プロテクションリージョン・キャッシュ設定）
|
||||
@ -109,8 +109,8 @@ extern "C" {
|
||||
#define HW_C6_PR_SIZE_MASK 0x0000003e // プロテクションリージョン サイズ
|
||||
#define HW_C6_PR_BASE_MASK 0xfffff000 // ベースアドレス
|
||||
|
||||
#define HW_C6_PR_SIZE_SHIFT 1
|
||||
#define HW_C6_PR_BASE_SHIFT 12
|
||||
#define HW_C6_PR_SIZE_SFT 1
|
||||
#define HW_C6_PR_BASE_SFT 12
|
||||
|
||||
#define HW_C6_PR_ENABLE 1 // プロテクションリージョン イネーブル
|
||||
#define HW_C6_PR_DISABLE 0 // ディセーブル
|
||||
@ -147,17 +147,17 @@ extern "C" {
|
||||
|
||||
#define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 // 命令キャッシュ インデックス
|
||||
#define HW_C7_DCACHE_INDEX_MASK 0x000003e0 // データキャッシュ インデックス
|
||||
#define HW_C7_CACHE_SET_NO_MASK 0xc0000000 // キャッシュ セットＮｏ
|
||||
#define HW_C7_CACHE_WAY_NO_MASK 0xc0000000 // キャッシュ ウェイＮｏ
|
||||
|
||||
#define HW_C7_CACHE_INDEX_SHIFT 5
|
||||
#define HW_C7_CACHE_SET_NO_SHIFT 30
|
||||
#define HW_C7_CACHE_INDEX_SFT 5
|
||||
#define HW_C7_CACHE_WAY_NO_SFT 30
|
||||
|
||||
|
||||
// レジスタ９.０（キャッシュロックダウン）
|
||||
|
||||
#define HW_C9_LOCKDOWN_SET_NO_MASK 0x00000003 // キャッシュロックダウン セットＮｏ
|
||||
#define HW_C9_LOCKDOWN_WAY_NO_MASK 0x00000003 // キャッシュロックダウン ウェイＮｏ
|
||||
|
||||
#define HW_C9_LOCKDOWN_SET_NO_SHIFT 0
|
||||
#define HW_C9_LOCKDOWN_WAY_NO_SFT 0
|
||||
|
||||
#define HW_C9_LOCKDOWN_LOAD_MODE 0x80000000 // キャッシュロックダウン ロードモード
|
||||
|
||||
@ -167,8 +167,8 @@ extern "C" {
|
||||
#define HW_C9_TCMR_SIZE_MASK 0x0000003e // ＴＣＭリージョン サイズ
|
||||
#define HW_C9_TCMR_BASE_MASK 0xfffff000 // ベースアドレス
|
||||
|
||||
#define HW_C9_TCMR_SIZE_SHIFT 1
|
||||
#define HW_C9_TCMR_BASE_SHIFT 12
|
||||
#define HW_C9_TCMR_SIZE_SFT 1
|
||||
#define HW_C9_TCMR_BASE_SFT 12
|
||||
|
||||
#define HW_C9_TCMR_4KB 0x06 // リージョンサイズ ４ＫＢｙｔｅ
|
||||
#define HW_C9_TCMR_8KB 0x08 // ８ＫＢｙｔｅ
|
||||
|
||||
Loading…
Reference in New Issue
Block a user