From 48bd2a2dc281985f407c1a0edb991bdd44d4b95e Mon Sep 17 00:00:00 2001 From: nakasima Date: Fri, 19 Dec 2008 08:38:35 +0000 Subject: [PATCH] =?UTF-8?q?=E3=82=AD=E3=83=A3=E3=83=83=E3=82=B7=E3=83=A5?= =?UTF-8?q?=E3=83=A9=E3=82=A4=E3=83=96=E3=83=A9=E3=83=AA=E8=BF=BD=E5=8A=A0?= =?UTF-8?q?=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-09-30%20-%20paladin.7z/paladin/ctr_firmware@132 b871894f-2f95-9b40-918c-086798483c85 --- .../build/libraries/init/ARM9/crt0_misc_sp.c | 2 +- .../libraries/init/ARM9/crt0_secure_sp.c | 8 +- .../bootrom/build/libraries/os/ARM11/Makefile | 3 +- .../bootrom/build/libraries/os/ARM9/Makefile | 3 +- .../build/libraries/os/common/os_cache.c | 854 ++++++++++++++++++ trunk/bootrom/include/brom/os.h | 1 + trunk/bootrom/include/brom/os/common/cache.h | 549 +++++++++++ trunk/include/ctr/hw/ARM9/arm9_reg.h | 30 +- 8 files changed, 1428 insertions(+), 22 deletions(-) create mode 100644 trunk/bootrom/build/libraries/os/common/os_cache.c create mode 100644 trunk/bootrom/include/brom/os/common/cache.h diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c index e875e35..f62c7de 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_misc_sp.c @@ -117,7 +117,7 @@ asm void STUPi_EnableTCM( void ) // プロテクションユニット/キャッシュ/TCM ディセーブル mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \ + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ | HW_C1_LD_INTERWORK_DISABLE \ diff --git a/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c b/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c index b83d7e2..0b6a9f5 100644 --- a/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c +++ b/trunk/bootrom/build/libraries/init/ARM9/crt0_secure_sp.c @@ -103,7 +103,7 @@ asm void STUPi_InitCP15(void) // プロテクションユニット/キャッシュ/TCM ディセーブル mrc p15, 0, r0, c1, c0, 0 - ldr r1, =HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE \ + ldr r1, =HW_C1_IC_ENABLE | HW_C1_DC_ENABLE \ | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ | HW_C1_ITCM_LOAD_MODE | HW_C1_DTCM_LOAD_MODE \ | HW_C1_LD_INTERWORK_DISABLE \ @@ -249,9 +249,9 @@ asm void STUPi_InitCP15(void) // システム制御コプロセッサ マスター設定 // mrc p15, 0, r0, c1, c0, 0 - ldr r1,=HW_C1_ICACHE_ENABLE | HW_C1_DCACHE_ENABLE | HW_C1_CACHE_ROUND_ROBIN \ - | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ - | HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \ + ldr r1,=HW_C1_IC_ENABLE | HW_C1_DC_ENABLE | HW_C1_CACHE_ROUND_ROBIN \ + | HW_C1_ITCM_ENABLE | HW_C1_DTCM_ENABLE \ + | HW_C1_SB1_BITSET | HW_C1_EXCEPT_VEC_UPPER \ | HW_C1_PROTECT_UNIT_ENABLE orr r0, r0, r1 mcr p15, 0, r0, c1, c0, 0 diff --git a/trunk/bootrom/build/libraries/os/ARM11/Makefile b/trunk/bootrom/build/libraries/os/ARM11/Makefile index 128c4e6..6d0dce3 100644 --- a/trunk/bootrom/build/libraries/os/ARM11/Makefile +++ b/trunk/bootrom/build/libraries/os/ARM11/Makefile @@ -28,11 +28,12 @@ BROM_CODEGEN_ALL ?= TRUE SRCDIR = . ../common SRCS = \ - os_alarm.c \ + os_cache.c \ os_init.c \ os_system.c \ os_timer.c \ os_tick.c \ + os_alarm.c \ os_irqHandler.c \ os_interrupt.c \ os_interrupt_common.c \ diff --git a/trunk/bootrom/build/libraries/os/ARM9/Makefile b/trunk/bootrom/build/libraries/os/ARM9/Makefile index 53a400a..489bff3 100644 --- a/trunk/bootrom/build/libraries/os/ARM9/Makefile +++ b/trunk/bootrom/build/libraries/os/ARM9/Makefile @@ -31,11 +31,12 @@ BROM_PROC = ARM9 SRCDIR = . ../common SRCS = \ - os_alarm.c \ + os_cache.c \ os_init.c \ os_system.c \ os_timer.c \ os_tick.c \ + os_alarm.c \ os_irqHandler.c \ os_interrupt.c \ os_interrupt_common.c \ diff --git a/trunk/bootrom/build/libraries/os/common/os_cache.c b/trunk/bootrom/build/libraries/os/common/os_cache.c new file mode 100644 index 0000000..a93e3e2 --- /dev/null +++ b/trunk/bootrom/build/libraries/os/common/os_cache.c @@ -0,0 +1,854 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - libraries - OS + File: os_cache.c + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: $ + $Rev$ + $Author$ + *---------------------------------------------------------------------------*/ +#include + +#include + +//=========================================================================== +// DATA CACHE CONTROL +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osEnableDCache + + Description: enable data cache + + Arguments: None + + Returns: previous state + *---------------------------------------------------------------------------*/ + +ASM BOOL osEnableDCache( void ) +{ + PRESERVE8 + + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #HW_C1_DC_ENABLE + mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT + orr r1, r1, #HW_C1_DC_ENABLE + mcr p15, 0, r1, c1, c0, 0 + bx lr +} + +/*---------------------------------------------------------------------------* + Name: osDisableDCache + + Description: disable data cache + + Arguments: None + + Returns: previous stats + *---------------------------------------------------------------------------*/ + +ASM BOOL osDisableDCache( void ) +{ + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #HW_C1_DC_ENABLE + mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT + bic r1, r1, #HW_C1_DC_ENABLE + mcr p15, 0, r1, c1, c0, 0 + bx lr +} + +/*---------------------------------------------------------------------------* + Name: osRestoreDCache + + Description: set state of data cache + + Arguments: data cache state to be set + + Returns: previous state + *---------------------------------------------------------------------------*/ + +ASM BOOL osRestoreDCache( BOOL enable ) +{ + //---- 引数処理 + cmp r0, #0 + moveq r2, #0 + movne r2, #HW_C1_DC_ENABLE + + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #HW_C1_DC_ENABLE + mov r0, r0, LSR #HW_C1_DC_ENABLE_SFT + bic r1, r1, #HW_C1_DC_ENABLE + orr r1, r1, r2 + mcr p15, 0, r1, c1, c0, 0 + bx lr +} + +//=========================================================================== +// DATA CACHE (for all range) +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osInvalidateDCacheAll + + Description: invalidate all data cache + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ + +ASM void osInvalidateDCacheAll( void ) +{ + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr +} + +/*---------------------------------------------------------------------------* + Name: osStoreDCacheAll + + Description: clean all data cache + (write cache data to memory) + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ + +ASM void osStoreDCacheAll( void ) +{ + mov r1, #0 +LSYM(1) + mov r0, #0 +LSYM(2) + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, #HW_DC_SIZE/4 + blt BSYM(2) + + add r1, r1, #1< + diff --git a/trunk/bootrom/include/brom/os.h b/trunk/bootrom/include/brom/os.h index 14de3f6..e2a8c8d 100644 --- a/trunk/bootrom/include/brom/os.h +++ b/trunk/bootrom/include/brom/os.h @@ -37,6 +37,7 @@ extern "C" { #include #include #include +#include #if 0 #include #include diff --git a/trunk/bootrom/include/brom/os/common/cache.h b/trunk/bootrom/include/brom/os/common/cache.h new file mode 100644 index 0000000..f6a3044 --- /dev/null +++ b/trunk/bootrom/include/brom/os/common/cache.h @@ -0,0 +1,549 @@ +/*---------------------------------------------------------------------------* + Project: CtrBrom - OS - include + File: cache.h + + Copyright 2008 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: $ + $Rev$ + $Author$ + *---------------------------------------------------------------------------*/ +#ifndef BROM_OS_CACHE_H_ +#define BROM_OS_CACHE_H_ + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +//=========================================================================== +// DATA CACHE CONTROL +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osEnableDCache + + Description: enable data cache + + Arguments: None + + Returns: previous state + *---------------------------------------------------------------------------*/ +BOOL osEnableDCache( void ); + +/*---------------------------------------------------------------------------* + Name: osDisableDCache + + Description: disable data cache + + Arguments: None + + Returns: previous stats + *---------------------------------------------------------------------------*/ +BOOL osDisableDCache( void ); + +/*---------------------------------------------------------------------------* + Name: osRestoreDCache + + Description: set state of data cache + + Arguments: data cache state to be set + + Returns: previous state + *---------------------------------------------------------------------------*/ +BOOL osRestoreDCache( BOOL enable ); + + +//=========================================================================== +// DATA CACHE (for all range) +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osInvalidateDCacheAll + + Description: invalidate all data cache + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateDCacheAll( void ); + +/*---------------------------------------------------------------------------* + Name: osStoreDCacheAll + + Description: clean all data cache + (write cache data to memory) + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osStoreDCacheAll( void ); + +/*---------------------------------------------------------------------------* + Name: osFlushDCacheAll + + Description: clean and invalidate all data cache + (write cache data to memory, and invalidate cache) + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osFlushDCacheAll( void ); + + +//=========================================================================== +// DATA CACHE (for specified range) +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osInvalidateDCacheRange + + Description: invalidate data cache in specified range + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateDCacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osStoreDCacheRange + + Description: clean data cache in specified range + (write cache data to memory) + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osStoreDCacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osFlushDCacheRange + + Description: clean and invalidate data cache in specified range + (write cache data to memory, and invalidate cache) + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osFlushDCacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osInvalidateDCacheRangeOrAll + + Description: invalidate data cache in specified range or all + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateDCacheRangeOrAll( void* startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osStoreDCacheRangeOrAll + + Description: clean data cache in specified range or all + (write cache data to memory) + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osStoreDCacheRangeOrAll( void* startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osFlushDCacheRangeOrAll + + Description: clean data cache in specified range or all + (write cache data to memory) + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osFlushDCacheRangeOrAll( void* startAddr, u32 nBytes ); + +//=========================================================================== +// DATA CACHE (for specified range) +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osLockdownDCacheRange + + Description: lock specified area to prevent not to release data cache + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osLockdownDCacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osUnlockdownDCacheAll + + Description: unlock all data cache to enable to release + + Arguments: none. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osUnlockdownDCacheAll( void ); + +/*---------------------------------------------------------------------------* + Name: dcUnlockdown + + Description: unlock any data cache to enable to release + + Arguments: num - specify number of datablock to unlock. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osUnlockdownDCache( u32 num ); + +/*---------------------------------------------------------------------------* + Name: osWaitWriteBufferEmpty + + Description: wait till write buffer becomes to be empty + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osWaitWriteBufferEmpty( void ); + +/*---------------------------------------------------------------------------* + Name: osTouchDCacheRange + + Description: include specified area to data cache in advance + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osTouchDCacheRange( void *startAddr, u32 nBytes ); + +#ifdef SDK_ARM11 + +/*---------------------------------------------------------------------------* + Name: osKeepDataAccessOrder + + Description: keep data access order + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ +void osKeepDataAccessOrder( void ); + +#endif // SDK_ARM11 + + +//=========================================================================== +// ALIAS OF DATA CACHE function +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osCleanDCacheAll + + Description: alias for osStoreDcacheAll + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +static inline void osCleanDCacheAll( void ) +{ + osStoreDCacheAll(); +} + +/*---------------------------------------------------------------------------* + Name: osCleanAndInvalidateDCacheAll + + Description: alias for osFlushDCacheAll + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +static inline void osCleanAndInvalidateDCacheAll( void ) +{ + osFlushDCacheAll(); +} + +/*---------------------------------------------------------------------------* + Name: osCleanDCacheRange + + Description: alias for osStoreDCacheRange + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +static inline void osCleanDCacheRange( void *startAddr, u32 nBytes ) +{ + osStoreDCacheRange( startAddr, nBytes ); +} + +/*---------------------------------------------------------------------------* + Name: osCleanAndInvalidateDCacheRange + + Description: alias for osFlushDCacheRange + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +static inline void osCleanAndInvalidateDCacheRange( void *startAddr, u32 nBytes ) +{ + osFlushDCacheRange( startAddr, nBytes ); +} + +#ifdef SDK_ARM11 + +/*---------------------------------------------------------------------------* + Name: osPreloadDCacheRange + + Description: alias for osTouchDCacheRange + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ + +static inline void osPreloadDCacheRange( void *startAddr, u32 nBytes ) +{ + osTouchDCacheRange( startAddr, nBytes ); +} + +/*---------------------------------------------------------------------------* + Name: osDoDataMemoryBarrier + + Description: Do Data Memory Barrier + + Arguments: None + + Returns: None + *---------------------------------------------------------------------------*/ + +static inline void osDoDataMemoryBarrier( void ) +{ + osKeepDataAccessOrder(); +} + +#endif // SDK_ARM11 + +//=========================================================================== +// INSTRUCTION CACHE CONTROL +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osEnableICache + + Description: enable instruction cache + + Arguments: None + + Returns: previous state + *---------------------------------------------------------------------------*/ +BOOL osEnableICache( void ); + +/*---------------------------------------------------------------------------* + Name: osDisableICache + + Description: disable instruction cache + + Arguments: None + + Returns: previous stats + *---------------------------------------------------------------------------*/ +BOOL osDisableICache( void ); + +/*---------------------------------------------------------------------------* + Name: osRestoreICache + + Description: set state of instruction cache + + Arguments: instruction cache state to be set + + Returns: previous stats + *---------------------------------------------------------------------------*/ +BOOL osRestoreICache( BOOL enable ); + + +//=========================================================================== +// INSTRUCTION CACHE +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osInvalidateICacheAll + + Description: invalidate all instruction cache + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateICacheAll( void ); + +/*---------------------------------------------------------------------------* + Name: osInvalidateICacheRange + + Description: invalidate instruction cache in specified range + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateICacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osInvalidateICacheRangeOrAll + + Description: invalidate instruction cache in specified range or all + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateICacheRangeOrAll( void* startAddr, u32 nBytes ); + +#ifdef SDK_ARM9 + +/*---------------------------------------------------------------------------* + Name: osLockdownICacheRange + + Description: lock specified area to prevent not to release instruction cache + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osLockdownICacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osUnlockdownICache + + Description: unlock any instruction cache to enable to release + + Arguments: num - specify number of datablock to unlock. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osUnlockdownICache( u32 num ); + +/*---------------------------------------------------------------------------* + Name: osUnlockdownICacheAll + + Description: unlock all instruction cache to enable to release + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osUnlockdownICacheAll( void ); + +#else // SDK_ARM11 + +/*---------------------------------------------------------------------------* + Name: osPrefetchICacheRange + + Description: include specified area to instruction cache in advance + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osPrefetchICacheRange( void *startAddr, u32 nBytes ); + +/*---------------------------------------------------------------------------* + Name: osInvalidateInstPrefetchBuffer + + Description: invalidate instruction prefetch buffer + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateInstPrefetchBuffer( void ); + +/*---------------------------------------------------------------------------* + Name: osDoInstMemoryBarrierAll + + Description: do all Instruction Memory Barrier + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osDoInstMemoryBarrierAll( void ); + +/*---------------------------------------------------------------------------* + Name: osDoInstMemoryBarrierRange + + Description: do Instruction Memory Barrier in specified range + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osDoInstMemoryBarrierRange( void* startAddr, u32 nBytes ); + + +//=========================================================================== +// BRANCH TARGET ADDRESS CACHE +//=========================================================================== +/*---------------------------------------------------------------------------* + Name: osInvalidateBCacheAll + + Description: invalidate all branch target address cache + + Arguments: None. + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateBCacheAll( void ); + +/*---------------------------------------------------------------------------* + Name: osInvalidateBCacheRange + + Description: invalidate branch target address cache in specified range + + Arguments: startAddr start address + nBytes size (in byte) + + Returns: None. + *---------------------------------------------------------------------------*/ +void osInvalidateBCacheRange( void* startAddr, u32 nBytes ); + +#endif // SDK_ARM11 + + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // BROM_OS_CACHE_H_ diff --git a/trunk/include/ctr/hw/ARM9/arm9_reg.h b/trunk/include/ctr/hw/ARM9/arm9_reg.h index 92780cc..0b5419d 100644 --- a/trunk/include/ctr/hw/ARM9/arm9_reg.h +++ b/trunk/include/ctr/hw/ARM9/arm9_reg.h @@ -28,8 +28,8 @@ extern "C" { #define HW_CPU_CLOCK_ARM9 (67027964 * 2) #define HW_CPU_CLOCK HW_CPU_CLOCK_ARM9 -#define HW_ICACHE_SIZE 0x2000 // 命令キャッシュ -#define HW_DCACHE_SIZE 0x1000 // データキャッシュ +#define HW_IC_SIZE 0x2000 // 命令キャッシュ +#define HW_DC_SIZE 0x1000 // データキャッシュ #define HW_CACHE_LINE_SIZE 32 #define HW_SYSTEM_CLOCK 33514000 // 正確には33513982? @@ -52,14 +52,14 @@ extern "C" { #define HW_C1_CACHE_PSEUDO_RANDOM 0x00000000 // 擬似ランダム #define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // 例外ベクタ 上位アドレス（こちらに設定して下さい） #define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // 下位アドレス -#define HW_C1_ICACHE_ENABLE 0x00001000 // 命令キャッシュ イネーブル -#define HW_C1_DCACHE_ENABLE 0x00000004 // データキャッシュ イネーブル +#define HW_C1_IC_ENABLE 0x00001000 // 命令キャッシュ イネーブル +#define HW_C1_DC_ENABLE 0x00000004 // データキャッシュ イネーブル #define HW_C1_LITTLE_ENDIAN 0x00000000 // リトルエンディアン #define HW_C1_BIG_ENDIAN 0x00000080 // ビッグエンディアン #define HW_C1_PROTECT_UNIT_ENABLE 0x00000001 // プロテクションユニット イネーブル -#define HW_C1_ICACHE_ENABLE_SHIFT 12 -#define HW_C1_DCACHE_ENABLE_SHIFT 2 +#define HW_C1_IC_ENABLE_SFT 12 +#define HW_C1_DC_ENABLE_SFT 2 // レジスタ２（プロテクションリージョン・キャッシュ設定） @@ -109,8 +109,8 @@ extern "C" { #define HW_C6_PR_SIZE_MASK 0x0000003e // プロテクションリージョン サイズ #define HW_C6_PR_BASE_MASK 0xfffff000 // ベースアドレス -#define HW_C6_PR_SIZE_SHIFT 1 -#define HW_C6_PR_BASE_SHIFT 12 +#define HW_C6_PR_SIZE_SFT 1 +#define HW_C6_PR_BASE_SFT 12 #define HW_C6_PR_ENABLE 1 // プロテクションリージョン イネーブル #define HW_C6_PR_DISABLE 0 // ディセーブル @@ -147,17 +147,17 @@ extern "C" { #define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 // 命令キャッシュ インデックス #define HW_C7_DCACHE_INDEX_MASK 0x000003e0 // データキャッシュ インデックス -#define HW_C7_CACHE_SET_NO_MASK 0xc0000000 // キャッシュ セットＮｏ +#define HW_C7_CACHE_WAY_NO_MASK 0xc0000000 // キャッシュ ウェイＮｏ -#define HW_C7_CACHE_INDEX_SHIFT 5 -#define HW_C7_CACHE_SET_NO_SHIFT 30 +#define HW_C7_CACHE_INDEX_SFT 5 +#define HW_C7_CACHE_WAY_NO_SFT 30 // レジスタ９.０（キャッシュロックダウン） -#define HW_C9_LOCKDOWN_SET_NO_MASK 0x00000003 // キャッシュロックダウン セットＮｏ +#define HW_C9_LOCKDOWN_WAY_NO_MASK 0x00000003 // キャッシュロックダウン ウェイＮｏ -#define HW_C9_LOCKDOWN_SET_NO_SHIFT 0 +#define HW_C9_LOCKDOWN_WAY_NO_SFT 0 #define HW_C9_LOCKDOWN_LOAD_MODE 0x80000000 // キャッシュロックダウン ロードモード @@ -167,8 +167,8 @@ extern "C" { #define HW_C9_TCMR_SIZE_MASK 0x0000003e // ＴＣＭリージョン サイズ #define HW_C9_TCMR_BASE_MASK 0xfffff000 // ベースアドレス -#define HW_C9_TCMR_SIZE_SHIFT 1 -#define HW_C9_TCMR_BASE_SHIFT 12 +#define HW_C9_TCMR_SIZE_SFT 1 +#define HW_C9_TCMR_BASE_SFT 12 #define HW_C9_TCMR_4KB 0x06 // リージョンサイズ ４ＫＢｙｔｅ #define HW_C9_TCMR_8KB 0x08 // ８ＫＢｙｔｅ