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https://github.com/rvtr/TwlIPL.git
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hyenaコンポーネントでWRAMが足りなくなったためWRAM-Bの32KBを追加。
git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@351 b08762b0-b915-fc4b-9d8c-17b2551a87ff
This commit is contained in:
nakasima
parent
22adb17b32
commit
d082cb325c
@ -27,6 +27,10 @@ include $(NITROSYSTEM_ROOT)/build/buildtools/modulerules
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%.tad: $(BINDIR)/$(TARGET_BIN)
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$(MAKETAD) $< $@
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# .rbin
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$(BINDIR)/$(TARGET_BIN_BASENAME).rbin: $(OBJS)
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objcopy -I elf32-little -O binary $< $@
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#----------------------------------------------------------------------------
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TWL_SYSMENU_MODULERULES_ = TRUE
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endif # TWL_SYSMENU_MODULERULES_
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@ -25,6 +25,8 @@ TWL_CODEGEN ?= ARM
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#----------------------------------------------------------------------------
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SUBDIRS = wram_regs
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SRCS = main.c
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TARGET_NAME = hyena
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@ -50,7 +52,7 @@ endif
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#MACRO_FLAGS += -DSDK_ARM7COMP_LTD
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MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037c0000' \
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MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037b8000' \
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-DADDRESS_FLXMAIN='0x02280000' \
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-DADDRESS_BOOTCORE='0x0380f000' \
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-DCRT0_O='$(CRT0_O)'
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49
build/components/hyena.TWL/wram_regs/Makefile
Normal file
49
build/components/hyena.TWL/wram_regs/Makefile
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@ -0,0 +1,49 @@
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#! make -f
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#----------------------------------------------------------------------------
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# Project: TwlFirm - tools - nandfirm-ds-launcher
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# File: Makefile
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#
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# Copyright 2007 Nintendo. All rights reserved.
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#
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# These coded instructions, statements, and computer programs contain
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# proprietary information of Nintendo of America Inc. and/or Nintendo
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# Company Ltd., and are protected by Federal copyright law. They may
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# not be disclosed to third parties or copied or duplicated in any form,
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# in whole or in part, without the prior written consent of Nintendo.
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#
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# $Log: $
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# $NoKeywords: $
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#----------------------------------------------------------------------------
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TWL_PROC = ARM7
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SUBDIRS =
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LINCLUDES = ../include
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#----------------------------------------------------------------------------
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TARGET_BIN = wram_regs.rbin
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SRCS = \
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wram_regs.c \
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#SRCDIR = # using default
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#LCFILE = # using default
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include $(TWL_IPL_RED_ROOT)/build/buildtools/commondefs
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INSTALL_DIR = .
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INSTALL_TARGETS = $(BINDIR)/$(TARGET_BIN)
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#----------------------------------------------------------------------------
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do-build: $(TARGETS)
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include $(TWL_IPL_RED_ROOT)/build/buildtools/modulerules
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#===== End of Makefile =====
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121
build/components/hyena.TWL/wram_regs/wram_regs.c
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121
build/components/hyena.TWL/wram_regs/wram_regs.c
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@ -0,0 +1,121 @@
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/*---------------------------------------------------------------------------*
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Project: TwlIPL - wram_regs
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File: wram_regs.c
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: 2007-12-11#$
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$Rev: 2990 $
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$Author: nakasima $
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*---------------------------------------------------------------------------*/
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#include <twl/mi.h>
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#define HW_HYENA_WRAM_A_OFS (HW_WRAM_A_LTD - HW_WRAM_BASE)
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#define HW_HYENA_WRAM_A_OFS_END (HW_WRAM_A_LTD_END - HW_WRAM_BASE)
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#define HW_HYENA_WRAM_B_OFS (HW_HYENA_WRAM_A_OFS - HW_WRAM_B_SIZE)
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#define HW_HYENA_WRAM_B_OFS_END (HW_HYENA_WRAM_A_OFS)
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#define HW_HYENA_WRAM_C_OFS (HW_HYENA_WRAM_B_OFS - HW_WRAM_C_SIZE)
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#define HW_HYENA_WRAM_C_OFS_END (HW_HYENA_WRAM_B_OFS)
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// MAP_TS_LTD for hyena
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// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
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// WRAM-B Lock:ON, Master:ARM7, Enable:Slot7 (32Kbytes), Address(7):0x037b8000-0x037bffff, Address(9):None
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// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-6(224Kbytes), Address(7):0x03780000-0x037b7fff, Address(9):0x03780000-0x037bffff
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// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03740000-0x0377ffff, Address(9):0x03740000-0x0377ffff
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// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
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// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
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// MAP_TS_LTD original
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// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
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// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03900000-0x0393ffff, Address(9):0x03900000-0x0393ffff
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// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03940000-0x0397ffff, Address(9):0x03940000-0x0397ffff
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// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
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// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
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u32 REBOOTi_WramRegDS[0x30/sizeof(u32)] =
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{
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// ARM9
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// WRAM-A
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REG_MI_MBK1_FIELD(
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TRUE, MI_WRAM_OFFSET_192KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_128KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_64KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_0KB/2, MI_WRAM_ARM7
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),
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// WRAM-B
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REG_MI_MBK2_FIELD(
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TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9
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),
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REG_MI_MBK3_FIELD(
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TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9
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),
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// WRAM-C
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REG_MI_MBK4_FIELD(
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TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9
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),
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REG_MI_MBK5_FIELD(
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TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9
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),
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REG_MI_MBK6_FIELD( NULL >> 16,
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MI_WRAM_IMAGE_256KB,
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NULL >> 16
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),
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REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_B_OFS >> 15
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),
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REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_C_OFS >> 15
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),
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// ARM7
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REG_MI_MBK6_FIELD( HW_HYENA_WRAM_A_OFS_END >> 16,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_A_OFS >> 16
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),
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REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_B_OFS >> 15
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),
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REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_C_OFS >> 15
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),
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// WRAM Lock
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(u32)(
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(0x0F << 0) |
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(0x80 << 8) |
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(0x00 << 16) |
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// WRAM-0/1
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(0 << 24) |
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// VRAM-C
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(7 << 26) |
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// VRAM-D
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(7 << 29)
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),
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};
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@ -125,7 +125,8 @@ Property
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# WRAM mapping: [MAP_BB_HYB/MAP_BB_LTD/MAP_TS_HYB/MAP_TS_LTD]
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# don't have to edit
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#
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WramMapping $(MAKEROM_WRAM_MAPPING)
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# WramMapping $(MAKEROM_WRAM_MAPPING)
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WramMappingDirect $(TWL_IPL_RED_ROOT)/build/components/hyena.TWL/wram_regs/wram_regs.rbin
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#
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# Codec mode:
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