diff --git a/build/buildtools/modulerules.sysmenu b/build/buildtools/modulerules.sysmenu index c8844a80..6a51c456 100644 --- a/build/buildtools/modulerules.sysmenu +++ b/build/buildtools/modulerules.sysmenu @@ -27,6 +27,10 @@ include $(NITROSYSTEM_ROOT)/build/buildtools/modulerules %.tad: $(BINDIR)/$(TARGET_BIN) $(MAKETAD) $< $@ +# .rbin +$(BINDIR)/$(TARGET_BIN_BASENAME).rbin: $(OBJS) + objcopy -I elf32-little -O binary $< $@ + #---------------------------------------------------------------------------- TWL_SYSMENU_MODULERULES_ = TRUE endif # TWL_SYSMENU_MODULERULES_ diff --git a/build/components/hyena.TWL/Makefile b/build/components/hyena.TWL/Makefile index 3182d5ff..12fcba36 100644 --- a/build/components/hyena.TWL/Makefile +++ b/build/components/hyena.TWL/Makefile @@ -25,6 +25,8 @@ TWL_CODEGEN ?= ARM #---------------------------------------------------------------------------- +SUBDIRS = wram_regs + SRCS = main.c TARGET_NAME = hyena @@ -50,7 +52,7 @@ endif #MACRO_FLAGS += -DSDK_ARM7COMP_LTD -MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037c0000' \ +MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037b8000' \ -DADDRESS_FLXMAIN='0x02280000' \ -DADDRESS_BOOTCORE='0x0380f000' \ -DCRT0_O='$(CRT0_O)' diff --git a/build/components/hyena.TWL/wram_regs/Makefile b/build/components/hyena.TWL/wram_regs/Makefile new file mode 100644 index 00000000..d8f67eab --- /dev/null +++ b/build/components/hyena.TWL/wram_regs/Makefile @@ -0,0 +1,49 @@ +#! make -f +#---------------------------------------------------------------------------- +# Project: TwlFirm - tools - nandfirm-ds-launcher +# File: Makefile +# +# Copyright 2007 Nintendo. All rights reserved. +# +# These coded instructions, statements, and computer programs contain +# proprietary information of Nintendo of America Inc. and/or Nintendo +# Company Ltd., and are protected by Federal copyright law. They may +# not be disclosed to third parties or copied or duplicated in any form, +# in whole or in part, without the prior written consent of Nintendo. +# +# $Log: $ +# $NoKeywords: $ +#---------------------------------------------------------------------------- + +TWL_PROC = ARM7 + +SUBDIRS = + +LINCLUDES = ../include + +#---------------------------------------------------------------------------- + +TARGET_BIN = wram_regs.rbin + +SRCS = \ + wram_regs.c \ + +#SRCDIR = # using default +#LCFILE = # using default + + +include $(TWL_IPL_RED_ROOT)/build/buildtools/commondefs + +INSTALL_DIR = . +INSTALL_TARGETS = $(BINDIR)/$(TARGET_BIN) + + +#---------------------------------------------------------------------------- + +do-build: $(TARGETS) + + +include $(TWL_IPL_RED_ROOT)/build/buildtools/modulerules + + +#===== End of Makefile ===== diff --git a/build/components/hyena.TWL/wram_regs/wram_regs.c b/build/components/hyena.TWL/wram_regs/wram_regs.c new file mode 100644 index 00000000..3fd8ea2e --- /dev/null +++ b/build/components/hyena.TWL/wram_regs/wram_regs.c @@ -0,0 +1,121 @@ +/*---------------------------------------------------------------------------* + Project: TwlIPL - wram_regs + File: wram_regs.c + + Copyright 2007 Nintendo. All rights reserved. + + These coded instructions, statements, and computer programs contain + proprietary information of Nintendo of America Inc. and/or Nintendo + Company Ltd., and are protected by Federal copyright law. They may + not be disclosed to third parties or copied or duplicated in any form, + in whole or in part, without the prior written consent of Nintendo. + + $Date:: 2007-12-11#$ + $Rev: 2990 $ + $Author: nakasima $ + *---------------------------------------------------------------------------*/ +#include + +#define HW_HYENA_WRAM_A_OFS (HW_WRAM_A_LTD - HW_WRAM_BASE) +#define HW_HYENA_WRAM_A_OFS_END (HW_WRAM_A_LTD_END - HW_WRAM_BASE) +#define HW_HYENA_WRAM_B_OFS (HW_HYENA_WRAM_A_OFS - HW_WRAM_B_SIZE) +#define HW_HYENA_WRAM_B_OFS_END (HW_HYENA_WRAM_A_OFS) +#define HW_HYENA_WRAM_C_OFS (HW_HYENA_WRAM_B_OFS - HW_WRAM_C_SIZE) +#define HW_HYENA_WRAM_C_OFS_END (HW_HYENA_WRAM_B_OFS) + +// MAP_TS_LTD for hyena +// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None +// WRAM-B Lock:ON, Master:ARM7, Enable:Slot7 (32Kbytes), Address(7):0x037b8000-0x037bffff, Address(9):None +// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-6(224Kbytes), Address(7):0x03780000-0x037b7fff, Address(9):0x03780000-0x037bffff +// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03740000-0x0377ffff, Address(9):0x03740000-0x0377ffff +// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff +// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff + +// MAP_TS_LTD original +// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None +// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03900000-0x0393ffff, Address(9):0x03900000-0x0393ffff +// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03940000-0x0397ffff, Address(9):0x03940000-0x0397ffff +// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff +// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff + +u32 REBOOTi_WramRegDS[0x30/sizeof(u32)] = +{ + // ARM9 + + // WRAM-A + REG_MI_MBK1_FIELD( + TRUE, MI_WRAM_OFFSET_192KB/2, MI_WRAM_ARM7, + TRUE, MI_WRAM_OFFSET_128KB/2, MI_WRAM_ARM7, + TRUE, MI_WRAM_OFFSET_64KB/2, MI_WRAM_ARM7, + TRUE, MI_WRAM_OFFSET_0KB/2, MI_WRAM_ARM7 + ), + // WRAM-B + REG_MI_MBK2_FIELD( + TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9 + ), + REG_MI_MBK3_FIELD( + TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7, + TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 + ), + // WRAM-C + REG_MI_MBK4_FIELD( + TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9 + ), + REG_MI_MBK5_FIELD( + TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9, + TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 + ), + + REG_MI_MBK6_FIELD( NULL >> 16, + MI_WRAM_IMAGE_256KB, + NULL >> 16 + ), + REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15, + MI_WRAM_IMAGE_256KB, + HW_HYENA_WRAM_B_OFS >> 15 + ), + REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15, + MI_WRAM_IMAGE_256KB, + HW_HYENA_WRAM_C_OFS >> 15 + ), + + // ARM7 + REG_MI_MBK6_FIELD( HW_HYENA_WRAM_A_OFS_END >> 16, + MI_WRAM_IMAGE_256KB, + HW_HYENA_WRAM_A_OFS >> 16 + ), + REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15, + MI_WRAM_IMAGE_256KB, + HW_HYENA_WRAM_B_OFS >> 15 + ), + REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15, + MI_WRAM_IMAGE_256KB, + HW_HYENA_WRAM_C_OFS >> 15 + ), + + // WRAM Lock + (u32)( + (0x0F << 0) | + (0x80 << 8) | + (0x00 << 16) | + + // WRAM-0/1 + (0 << 24) | + + // VRAM-C + (7 << 26) | + // VRAM-D + (7 << 29) + ), +}; + diff --git a/build/systemMenu_RED/Launcher/ARM9/main.rsf b/build/systemMenu_RED/Launcher/ARM9/main.rsf index 6ea27adc..928b92aa 100644 --- a/build/systemMenu_RED/Launcher/ARM9/main.rsf +++ b/build/systemMenu_RED/Launcher/ARM9/main.rsf @@ -125,7 +125,8 @@ Property # WRAM mapping: [MAP_BB_HYB/MAP_BB_LTD/MAP_TS_HYB/MAP_TS_LTD] # don't have to edit # - WramMapping $(MAKEROM_WRAM_MAPPING) +# WramMapping $(MAKEROM_WRAM_MAPPING) + WramMappingDirect $(TWL_IPL_RED_ROOT)/build/components/hyena.TWL/wram_regs/wram_regs.rbin # # Codec mode: