rvtr/TwlIPL
1
Fork 0
mirror of https://github.com/rvtr/TwlIPL.git synced 2025-10-31 06:01:12 -04:00
Code Issues Actions Packages Projects Releases Wiki Activity

hyenaのWRAMコード位置を0x1000ほど手前へ。docも更新

Browse Source 
git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@659 b08762b0-b915-fc4b-9d8c-17b2551a87ff
This commit is contained in:
yoshida_teruhisa 2008-02-14 08:20:04 +00:00
parent 8755e60c6a
commit cbc4e4fed9
4 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
build/components/hyena.TWL/Makefile
View File

@ -52,7 +52,7 @@ endif
#MACRO_FLAGS += -DSDK_ARM7COMP_LTD #MACRO_FLAGS += -DSDK_ARM7COMP_LTD
MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037b8000' \ MAKELCF_FLAGS += -DADDRESS_LTDWRAM='0x037a8000' \
-DADDRESS_FLXMAIN='0x02280000' \ -DADDRESS_FLXMAIN='0x02280000' \
-DADDRESS_BOOTCORE='0x0380f000' \ -DADDRESS_BOOTCORE='0x0380f000' \
-DCRT0_O='$(CRT0_O)' -DCRT0_O='$(CRT0_O)'

2
build/components/hyena.TWL/hyena.lcf.template
View File

@ -30,7 +30,7 @@ MEMORY
<OVERLAY.NAME> (RWXO): ORIGIN = <OVERLAY.ADDRESS>, LENGTH = 0x0 > <OVERLAY.NAME><PROPERTY.FLXSUFFIX> <OVERLAY.NAME> (RWXO): ORIGIN = <OVERLAY.ADDRESS>, LENGTH = 0x0 > <OVERLAY.NAME><PROPERTY.FLXSUFFIX>
<END.OVERLAYS> <END.OVERLAYS>
check.WORKRAM (RWX) : ORIGIN = 0x037b8000, LENGTH = 0x58000 > workram.check check.WORKRAM (RWX) : ORIGIN = 0x037a8000, LENGTH = 0x58000 > workram.check
binary.LTDAUTOLOAD_TOP (RW) : ORIGIN = 0, LENGTH = 0x0 > <STATIC.NAME><PROPERTY.LTDSUFFIX> binary.LTDAUTOLOAD_TOP (RW) : ORIGIN = 0, LENGTH = 0x0 > <STATIC.NAME><PROPERTY.LTDSUFFIX>
<FOREACH.LTDAUTOLOADS> <FOREACH.LTDAUTOLOADS>

9
build/components/hyena.TWL/wram_regs/wram_regs.c
View File

@ -56,12 +56,21 @@ u32 HYENA_WramReg[0x30/sizeof(u32)] =
TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9, TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9,
TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9 TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9
), ),
#if 0
REG_MI_MBK3_FIELD( REG_MI_MBK3_FIELD(
TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7, TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7,
TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9, TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9,
TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9, TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9,
TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9
), ),
#else
REG_MI_MBK3_FIELD(
TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7,
TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7,
TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7,
TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7
),
#endif
// WRAM-C // WRAM-C
REG_MI_MBK4_FIELD( REG_MI_MBK4_FIELD(
TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9, TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9,

BIN
docs/メモリマップ_ランチャー.vsd
View File

Binary file not shown.