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WRAM_OFFSETの定義値の誤りを修正。

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@5 b08762b0-b915-fc4b-9d8c-17b2551a87ff
This commit is contained in:
yosiokat 2007-09-06 08:27:10 +00:00
parent 69c7cc046f
commit 3da7a04d80
3 changed files with 60 additions and 93 deletions
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51
build/tools/makegcdfirm/wram_regs.c
View File

@ -21,46 +21,35 @@
#include <twl/mi/common/sharedWram.h>
#include <firm/format/wram_regs.h>
// define macro -------------------------------------------
#define MI_WRAM_MAP_NULL HW_WRAM_AREA
#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \
( \
((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \
(REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \
REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \
)
// global variables----------------------------------------
MIHeader_WramRegs wram_regs_init =
{
// ARM9
{
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ),
},
REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ),
MI_WRAM_IMAGE_128KB,

51
build/tools/makenandfirm/wram_regs.c
View File

@ -21,46 +21,35 @@
#include <twl/mi/common/sharedWram.h>
#include <firm/format/wram_regs.h>
// define macro -------------------------------------------
#define MI_WRAM_MAP_NULL HW_WRAM_AREA
#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \
( \
((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \
(REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \
REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \
)
// global variables----------------------------------------
MIHeader_WramRegs wram_regs_init =
{
// ARM9
{
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ),
},
REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ),
MI_WRAM_IMAGE_128KB,

51
build/tools/makenorfirm/wram_regs.c
View File

@ -21,46 +21,35 @@
#include <twl/mi/common/sharedWram.h>
#include <firm/format/wram_regs.h>
// define macro -------------------------------------------
#define MI_WRAM_MAP_NULL HW_WRAM_AREA
#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \
( \
((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \
(REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \
REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \
)
// global variables----------------------------------------
MIHeader_WramRegs wram_regs_init =
{
// ARM9
{
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ),
REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ),
REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ),
},
{
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ),
REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ),
REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ),
},
REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ),
MI_WRAM_IMAGE_128KB,