From 3da7a04d809006481e36e4511af07fdb1a8b54e3 Mon Sep 17 00:00:00 2001 From: yosiokat Date: Thu, 6 Sep 2007 08:27:10 +0000 Subject: [PATCH] =?UTF-8?q?WRAM=5FOFFSET=E3=81=AE=E5=AE=9A=E7=BE=A9?= =?UTF-8?q?=E5=80=A4=E3=81=AE=E8=AA=A4=E3=82=8A=E3=82=92=E4=BF=AE=E6=AD=A3?= =?UTF-8?q?=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@5 b08762b0-b915-fc4b-9d8c-17b2551a87ff --- build/tools/makegcdfirm/wram_regs.c | 51 +++++++++++----------------- build/tools/makenandfirm/wram_regs.c | 51 +++++++++++----------------- build/tools/makenorfirm/wram_regs.c | 51 +++++++++++----------------- 3 files changed, 60 insertions(+), 93 deletions(-) diff --git a/build/tools/makegcdfirm/wram_regs.c b/build/tools/makegcdfirm/wram_regs.c index 40237ac3..fba20ce8 100644 --- a/build/tools/makegcdfirm/wram_regs.c +++ b/build/tools/makegcdfirm/wram_regs.c @@ -21,46 +21,35 @@ #include #include -// define macro ------------------------------------------- -#define MI_WRAM_MAP_NULL HW_WRAM_AREA -#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \ -( \ - ((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \ - (REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \ - REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \ -) - - -// global variables---------------------------------------- MIHeader_WramRegs wram_regs_init = { // ARM9 { - REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_128KB, diff --git a/build/tools/makenandfirm/wram_regs.c b/build/tools/makenandfirm/wram_regs.c index b2f1aa28..5f09a868 100644 --- a/build/tools/makenandfirm/wram_regs.c +++ b/build/tools/makenandfirm/wram_regs.c @@ -21,46 +21,35 @@ #include #include -// define macro ------------------------------------------- -#define MI_WRAM_MAP_NULL HW_WRAM_AREA -#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \ -( \ - ((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \ - (REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \ - REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \ -) - - -// global variables---------------------------------------- MIHeader_WramRegs wram_regs_init = { // ARM9 { - REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_128KB, diff --git a/build/tools/makenorfirm/wram_regs.c b/build/tools/makenorfirm/wram_regs.c index 4d53df26..68ed4689 100644 --- a/build/tools/makenorfirm/wram_regs.c +++ b/build/tools/makenorfirm/wram_regs.c @@ -21,46 +21,35 @@ #include #include -// define macro ------------------------------------------- -#define MI_WRAM_MAP_NULL HW_WRAM_AREA -#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \ -( \ - ((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \ - (REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \ - REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \ -) - - -// global variables---------------------------------------- MIHeader_WramRegs wram_regs_init = { // ARM9 { - REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ), - REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ), + REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), }, { - REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ), + REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_128KB,