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arm9: use instruction TCM
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parent
b7720547c7
commit
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@ -15,32 +15,32 @@ SECTIONS
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*(.text)
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*(.text.*)
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. = ALIGN(32);
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} >arm7_exclusive_internal_work_ram AT>main_memory
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} > arm7_exclusive_internal_work_ram AT> main_memory
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.data ALIGN(4) :
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{
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*(.data)
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*(.data.*)
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} >arm7_exclusive_internal_work_ram AT>main_memory
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} > arm7_exclusive_internal_work_ram AT> main_memory
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.rodata ALIGN(4) :
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{
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*(.rodata)
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*(.rodata.*)
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} >arm7_exclusive_internal_work_ram AT>main_memory
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} > arm7_exclusive_internal_work_ram AT> main_memory
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.ctors ALIGN(4) :
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{
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KEEP(*(.ctors))
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KEEP(*(.ctors.*))
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} >arm7_exclusive_internal_work_ram AT>main_memory
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} > arm7_exclusive_internal_work_ram AT> main_memory
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.bss ALIGN(4) (NOLOAD) :
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{
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*(.bss)
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*(.bss.*)
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*(COMMON)
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} >arm7_exclusive_internal_work_ram
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} > arm7_exclusive_internal_work_ram
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/DISCARD/ :
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{
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@ -2,47 +2,47 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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MEMORY
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{
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ram : ORIGIN = 0x02000000, LENGTH = 4M
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main_memory : ORIGIN = 0x02000000, LENGTH = 4M - 256K
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arm9_instruction_tcm : ORIGIN = 0x01000000, LENGTH = 32K
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arm9_data_tcm : ORIGIN = 0x027e0000, LENGTH = 16K
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}
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SECTIONS
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{
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. = ORIGIN(ram);
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. = ORIGIN(arm9_instruction_tcm);
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.text ALIGN(4) :
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{
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KEEP(*(.text.start))
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*(.text)
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*(.text.*)
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*(.glue_7t)
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*(.glue_7)
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*(.vfp11_veneer)
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*(.v4_bx)
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} > ram
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. = ALIGN(32);
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} > arm9_instruction_tcm AT> main_memory
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. = ORIGIN(main_memory) + SIZEOF(.text);
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.data ALIGN(4) :
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{
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*(.data)
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*(.data.*)
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} > ram
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} > main_memory
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.rodata ALIGN(4) :
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{
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*(.rodata)
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*(.rodata.*)
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} > ram
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.ctors ALIGN(4) :
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{
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KEEP(*(.ctors))
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KEEP(*(.ctors.*))
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} > ram
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} > main_memory
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.bss ALIGN(4) (NOLOAD) :
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{
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*(.bss)
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*(.bss.*)
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*(COMMON)
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} > ram
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} > main_memory
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/DISCARD/ :
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{
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*(.glue_7) *(.glue_7t) *(.vfp11_veneer) *(.v4_bx)
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}
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INCLUDE "../debug.lds"
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}
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@ -50,4 +50,4 @@ SECTIONS
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INCLUDE "../symbols.lds"
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INCLUDE "addresses.lds"
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__stack_end = ORIGIN(ram) + LENGTH(ram) - 4;
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__stack_end = ORIGIN(main_memory) + LENGTH(main_memory) - 4;
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@ -287,8 +287,8 @@ void main()
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io_registers.a.MTX_IDENTITY = 0;
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io_registers.a.MTX_TRANS = 0;
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io_registers.a.MTX_TRANS = (int)(-0.7 * (float)(1 << 12));
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io_registers.a.MTX_TRANS = (int)(-0.1 * (float)(1 << 12));
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io_registers.a.MTX_TRANS = (int)(-1.0 * (float)(1 << 12));
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io_registers.a.MTX_TRANS = (int)(0.15 * (float)(1 << 12));
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// multiply by a y-axis rotation
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27
arm9/start.s
27
arm9/start.s
@ -1,3 +1,16 @@
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/* DDI0201D_arm946es_r1p1_trm.pdf pdf page 40 ; printed page 2-12 */
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.set INSTRUCTION_TCM_LOAD_MODE, (1 << 19)
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.set INSTRUCTION_TCM_ENABLE, (1 << 18)
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.set DATA_TCM_LOAD_MODE, (1 << 17)
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.set DATA_TCM_ENABLE, (1 << 16)
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.set DISABLE_LOADING_TBIT, (1 << 15)
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.set ROUND_ROBIN_REPLACEMENT, (1 << 14)
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.set ALTERNATE_VECTOR_SELET, (1 << 13)
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.set INSTRUCTION_CACHE_ENABLE, (1 << 12)
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.set BIG_ENDIAN, (1 << 7)
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.set DATA_CACHE_ENABLE, (1 << 2)
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.set PROTECTION_UNIT_ENABLE, (1 << 0)
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.macro FILL_ZERO_32_BYTE_ALIGNED
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cmp r1, r10
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beq _fill_break.\@
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@ -25,13 +38,25 @@ _fill_break.\@:
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.section .text.start
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.global _start
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_start:
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/*
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// https://developer.arm.com/documentation/ddi0338/g/system-control-coprocessor/system-control-processor-registers/c9--data-tcm-region-register?lang=en
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// set data tcm address
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ldr r0, =0x027e0000
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mcr p15, 0, r0, c9, c1, 0
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// enable instruction and data TCM
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =INSTRUCTION_TCM_ENABLE | DATA_TCM_ENABLE | INSTRUCTION_CACHE_ENABLE | DATA_CACHE_ENABLE
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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_link_text:
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ldr r0, =__text_load_start
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ldr r1, =__text_link_start
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ldr r10, =__text_link_end
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COPY_32_BYTE_ALIGNED
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/*
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_link_data:
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ldr r0, =__data_load_start
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ldr r1, =__data_link_start
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@ -10,8 +10,5 @@ __rodata_link_start = ADDR(.rodata);
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__rodata_link_end = ADDR(.rodata) + SIZEOF(.rodata);
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__rodata_load_start = LOADADDR(.rodata);
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__ctors_link_start = ADDR(.ctors);
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__ctors_link_end = ADDR(.ctors) + SIZEOF(.ctors);
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__bss_link_start = ADDR(.bss);
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__bss_link_end = ADDR(.bss) + SIZEOF(.bss);
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