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https://github.com/wavemotion-dave/GimliDS.git
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Version 1.1 - See readme.md for details.
This commit is contained in:
Dave Bernazzani
parent
26d89638b1
commit
93b7b75c55
BIN
GimliDS.nds
BIN
GimliDS.nds
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2
Makefile
2
Makefile
@ -9,7 +9,7 @@ include $(DEVKITARM)/ds_rules
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export TARGET := GimliDS
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export TOPDIR := $(CURDIR)
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export VERSION := 1.0a
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export VERSION := 1.1
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ICON := -b $(CURDIR)/C64_icon.bmp "GimliDS $(VERSION);wavemotion-dave;https://github.com/wavemotion-dave/GimliDS"
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@ -147,6 +147,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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```
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## Change Log
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Version 1.1 release 11-May-2025 by wavemotion-dave
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* Fix to CIA vars initialization so games like Chuckie Egg start properly.
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* Fix to TOD clock counters (previous versions would not clock at all... fixes some utilities mostly).
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* Improved REU handling for a bit more speed (gain of 1-2 frames on REU games)
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* Improved VIC handling for a bit more speed (gain of 1-2 frames across the board)
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Version 1.0 release 09-May-2025 by wavemotion-dave
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* Added TOGGLE ZOOM button map to scale screen 1:1 temporarily (to make text games readable)
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* Another proper fix for CPU jump commands not handling the extra cycle it takes.
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Binary file not shown.
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Before Width: | Height: | Size: 40 KiB After Width: | Height: | Size: 40 KiB |
@ -1351,7 +1351,7 @@ void C64::main_loop(void)
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// -----------------------------------------------------------------
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if (ThePrefs.TrueDrive)
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{
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int cycles_1541 = FLOPPY_CYCLES_PER_LINE + CycleDeltas[myConfig.flopCycles];
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int cycles_1541 = FLOPPY_CYCLES_PER_LINE;
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TheCPU1541->CountVIATimers(cycles_1541);
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if (!TheCPU1541->Idle)
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@ -84,7 +84,7 @@ void MOS6526::Reset(void)
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pra = prb = ddra = ddrb = 0;
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ta = tb = 0xffff;
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latcha = latchb = 1;
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latcha = latchb = 0xffff;
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tod_10ths = tod_sec = tod_min = 0; tod_hr = 1;
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alm_10ths = alm_sec = alm_min = alm_hr = 0;
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@ -559,7 +559,6 @@ void MOS6526::CountTOD(void)
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tod_divider--;
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else
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{
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// Reload divider according to 50/60 Hz flag
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if (cra & 0x80)
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tod_divider = 4;
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@ -947,7 +947,7 @@
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case 0x7c:
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case 0xdc:
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case 0xfc:
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#if PRECISE_CPU_CYCLES
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#if PRECISE_CPU_CYCLES_NO // Save the effort and we need the ITCM_CODE space
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read_byte_abs_x();
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#else
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pc+=2;
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@ -51,8 +51,11 @@
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extern u8 myRAM[];
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// We are emulating the REU-1764 (256K) only
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u8 REU_RAM[256 * 1024];
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#define RAM_MASK 0x3FFFF
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/*
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* REU constructor
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*/
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@ -61,7 +64,6 @@ REU::REU(MOS6510 * cpu) : the_cpu(cpu)
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{
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// Allocate expansion RAM
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ram_size = 0x40000; // 256K only
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ram_mask = ram_size - 1;
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ex_ram = REU_RAM;
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@ -208,6 +210,11 @@ void REU::WriteIO2(uint16_t adr, uint8_t byte)
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{
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execute_dma();
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}
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if ((byte & 0x90) == 0x80)
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{
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// This would normally be the 'delayed' write... not fully handled by GimliDS as we can't afford the trigger check on FF00
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execute_dma();
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}
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break;
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default:
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regs[adr & 0xf] = byte;
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@ -236,45 +243,44 @@ void REU::execute_dma()
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// Get transfer length
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uint16_t length = regs[7] | (regs[8] << 8);
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// Calculate address increments
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unsigned c64_inc = (regs[10] & 0x80) ? 0 : 1;
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unsigned reu_inc = (regs[10] & 0x40) ? 0 : 1;
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// We are skipping the memory increment of regs[10] as there
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// are no known practical uses of it... and we need the speed.
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// Do transfer
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bool verify_error = false;
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while (!verify_error)
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if ((regs[1] & 3) == 0)
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{
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switch (regs[1] & 3)
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while (length--)
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{
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case 0: // C64 -> REU
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ex_ram[reu_adr & ram_mask] = the_cpu->REUReadByte(c64_adr);
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break;
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case 1: // C64 <- REU
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the_cpu->REUWriteByte(c64_adr, ex_ram[reu_adr & ram_mask]);
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break;
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case 2: { // C64 <-> REU
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uint8_t tmp = the_cpu->REUReadByte(c64_adr);
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the_cpu->REUWriteByte(c64_adr, ex_ram[reu_adr & ram_mask]);
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ex_ram[reu_adr & ram_mask] = tmp;
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break;
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REU_RAM[reu_adr++ & RAM_MASK] = the_cpu->REUReadByte(c64_adr++);
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}
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case 3: // Compare
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if (ex_ram[reu_adr & ram_mask] != the_cpu->REUReadByte(c64_adr))
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}
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else if ((regs[1] & 3) == 1)
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{
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while (length--)
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{
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the_cpu->REUWriteByte(c64_adr++, REU_RAM[reu_adr++ & RAM_MASK]);
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}
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}
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else if ((regs[1] & 3) == 2)
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{
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while (length--)
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{
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uint8_t tmp = the_cpu->REUReadByte(c64_adr);
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the_cpu->REUWriteByte(c64_adr++, REU_RAM[reu_adr & RAM_MASK]);
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REU_RAM[reu_adr++ & RAM_MASK] = tmp;
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}
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}
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else // Compare
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{
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while (length--)
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{
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if (REU_RAM[reu_adr++ & RAM_MASK] != the_cpu->REUReadByte(c64_adr++))
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{
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regs[0] |= 0x20; // Verify error
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verify_error = true;
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}
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break;
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}
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c64_adr += c64_inc;
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reu_adr += reu_inc;
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if (--length == 0)
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{
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}
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}
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regs[0] |= 0x40; // Transfer finished
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break;
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}
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}
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// Update address and length registers
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if (regs[1] & 0x20)
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@ -289,7 +295,7 @@ void REU::execute_dma()
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}
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else
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{
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reu_adr &= ram_mask;
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reu_adr &= RAM_MASK;
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regs[2] = c64_adr & 0xff;
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regs[3] = c64_adr >> 8;
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regs[4] = reu_adr & 0xff;
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@ -308,7 +314,7 @@ void REU::execute_dma()
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void REU::GetState(REUState *rs)
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{
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rs->ram_size = ram_size;
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rs->ram_mask = ram_mask;
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rs->ram_mask = RAM_MASK;
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rs->autoload_c64_adr_lo = autoload_c64_adr_lo;
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rs->autoload_c64_adr_hi = autoload_c64_adr_hi;
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rs->autoload_reu_adr_lo = autoload_reu_adr_lo;
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@ -327,7 +333,7 @@ void REU::GetState(REUState *rs)
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void REU::SetState(REUState *rs)
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{
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ram_size = rs->ram_size;
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ram_size = rs->ram_mask;
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ram_mask = RAM_MASK;
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autoload_c64_adr_lo = rs->autoload_c64_adr_lo;
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autoload_c64_adr_hi = rs->autoload_c64_adr_hi;
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autoload_reu_adr_lo = rs->autoload_reu_adr_lo;
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@ -1018,7 +1018,7 @@ __attribute__ ((noinline)) ITCM_CODE void MOS6569::el_ecm_text(uint8 *p, uint8
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}
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void MOS6569::el_std_idle(uint8 *p, uint8 *r)
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__attribute__ ((noinline)) ITCM_CODE void MOS6569::el_std_idle(uint8 *p, uint8 *r)
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{
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uint8 data = *get_physical(ctrl1 & 0x40 ? 0x39ff : 0x3fff);
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uint32 *lp = (uint32 *)p;
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@ -1431,7 +1431,7 @@ int MOS6569::EmulateLine(void)
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if (raster >= FIRST_DMA_LINE && raster <= LAST_DMA_LINE && ((raster & 7) == y_scroll) && bad_lines_enabled)
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{
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is_bad_line = true;
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cycles_left = BAD_CYCLES_PER_LINE + CycleDeltas[myConfig.cpuCycles];
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cycles_left = BAD_CYCLES_PER_LINE + CycleDeltas[myConfig.cpuCycles] + CycleDeltas[myConfig.badCycles];
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}
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goto VIC_nop;
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}
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@ -1452,7 +1452,7 @@ int MOS6569::EmulateLine(void)
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{
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// Turn on display
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display_state = is_bad_line = true;
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cycles_left = BAD_CYCLES_PER_LINE + CycleDeltas[myConfig.cpuCycles];
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cycles_left = BAD_CYCLES_PER_LINE + CycleDeltas[myConfig.cpuCycles] + CycleDeltas[myConfig.badCycles];
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rc = 0;
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// Read and latch 40 bytes from video matrix and color RAM
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@ -386,7 +386,7 @@ void SetDefaultGameConfig(void)
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myConfig.reserved7 = 0;
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myConfig.reserved8 = 0xA5; // So it's easy to spot on an "upgrade" and we can re-default it
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myConfig.cpuCycles = 0; // Normal 63 - this is the delta adjustment to that
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myConfig.flopCycles = 0; // Normal 64 - this is the delta adjustment to that
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myConfig.badCycles = 0; // Normal 23 - this is the delta adjustment to that
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myConfig.offsetX = 32; // Push the side border off the main display
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myConfig.offsetY = 19; // Push the top border off the main display
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@ -394,7 +394,7 @@ void SetDefaultGameConfig(void)
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myConfig.scaleY = 200; // Scale the 200 pixels of C64 display to the DS 200 (yes, there is only 192 so this will cut... use PAN UP/DN)
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}
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s16 CycleDeltas[] = {0,1,2,3,4,5,6,7,8,9,-9,-8,-7,-6,-5,-4,-3,-2,-1}; // Used with myConfig.cpuCycles and myConfig.flopCycles
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s16 CycleDeltas[] = {0,1,2,3,4,5,6,7,8,9,-9,-8,-7,-6,-5,-4,-3,-2,-1}; // Used with myConfig.cpuCycles and myConfig.badCycles
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// ----------------------------------------------------------------------
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// Read file twice and ensure we get the same CRC... if not, do it again
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@ -592,7 +592,7 @@ const struct options_t Option_Table[1][20] =
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{"LCD JITTER", {"NONE", "LIGHT", "HEAVY"}, &myConfig.jitter, 3},
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{"DISK SOUND", {"SFX OFF", "SFX ON"}, &myConfig.diskSFX, 2},
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{"CPU CYCLES", {CYCLE_DELTA_STR}, &myConfig.cpuCycles, 19},
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{"1541 CYCLES", {CYCLE_DELTA_STR}, &myConfig.flopCycles, 19},
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{"BAD CYCLES" , {CYCLE_DELTA_STR}, &myConfig.badCycles, 19},
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{"POUND KEY", {"POUND", "LEFT ARROW", "UP ARROW", "C= COMMODORE"}, &myConfig.poundKey, 4},
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{"D-PAD UP", {KEY_MAP_OPTIONS}, &myConfig.key_map[0], 65},
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@ -21,7 +21,7 @@ struct __attribute__((__packed__)) Config_t
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u8 reserved7;
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u8 reserved8;
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u8 cpuCycles;
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u8 flopCycles;
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u8 badCycles;
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s8 offsetX;
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s8 offsetY;
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s16 scaleX;
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