mirror of
https://github.com/wavemotion-dave/A7800DS.git
synced 2025-06-18 21:35:32 -04:00
344 lines
11 KiB
C
344 lines
11 KiB
C
// ----------------------------------------------------------------------------
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// ___ ___ ___ ___ ___ ____ ___ _ _
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// /__/ /__/ / / /__ /__/ /__ / /_ / |/ /
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// / / \ /__/ ___/ ___/ ___/ / /__ / / emulator
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//
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// ----------------------------------------------------------------------------
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// Copyright 2005 Greg Stanton
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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// ----------------------------------------------------------------------------
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// Memory.cpp
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// ----------------------------------------------------------------------------
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#include "ProSystem.h"
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#include "Memory.h"
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#include "Maria.h"
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#include "Database.h"
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byte memory_ram[MEMORY_SIZE] ALIGN(32) = {0};
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u8 *is_memory_writable = (u8*)0x06820000;
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u32 snes_bit_pos = 0;
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u8 bHSC_dirty = 0;
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extern bool write_only_pokey_at_4000;
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// ----------------------------------------------------------------------------
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// Reset
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// ----------------------------------------------------------------------------
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void memory_Reset( )
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{
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uint index;
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for(index = 0; index < MEMORY_SIZE; index++) {
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memory_ram[index] = 0;
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is_memory_writable[index] = 0;
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}
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u16 *ptr = (u16*)is_memory_writable;
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for(index = 0; index < 16384/2; index++) {
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ptr[index] = 0xFFFF;
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}
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bHSC_dirty = 0;
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snes_bit_pos = 0;
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}
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// ----------------------------------------------------------------------------
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// Read
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// ----------------------------------------------------------------------------
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ITCM_CODE byte memory_Read_Slower(word address)
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{
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if (address & 0x8000) return memory_ram[address];
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else if ((address & 0xFFFC) == 0x284)
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{
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if (address & 0x1)
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{
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byte tmp_byte = memory_ram[INTFLG];
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memory_ram[INTFLG] &= 0x7f;
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return tmp_byte;
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}
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else
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{
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memory_ram[INTFLG] &= 0x7f;
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return memory_ram[INTIM];
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}
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}
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else if (myCartInfo.pokeyType)
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{
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if (myCartInfo.pokeyType == POKEY_AT_4000)
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{
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if (((address & 0xFFF0) == 0x4000) && (!write_only_pokey_at_4000)) return pokey_GetRegister(address);
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}
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else
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{
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// Not quite accurate as it will catch anything from 0x440 to 0x4C0 but that's
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// good enough as nothing else should be mapped in this region except POKEY.
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if ((address & 0xFFC0) == 0x440) return pokey_GetRegister(0x4000 | (address & 0xF));
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if ((address & 0xFFF0) == 0x800) return pokey_GetRegister(0x4000 | (address & 0xF));
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}
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}
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return memory_ram[address];
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}
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// ----------------------------------------------------------------------------
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// Write
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// ----------------------------------------------------------------------------
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ITCM_CODE void memory_Write(word address, byte data)
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{
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extern u32 bg32, maria_charbase;
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extern u8 bg8;
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if (myCartInfo.pokeyType)
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{
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if (myCartInfo.pokeyType == POKEY_AT_4000)
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{
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if ((address & 0xFFF0) == 0x4000)
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{
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pokey_SetRegister(address, data);
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return;
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}
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}
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else
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{
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// Not quite accurate as it will catch anything from 0x440 to 0x4C0 but that's
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// good enough as nothing else should be mapped in this region except POKEY.
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if ((address & 0xFFC0) == 0x440)
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{
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pokey_SetRegister(0x4000 | (address & 0x0F), data);
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return;
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}
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if ((address & 0xFFF0) == 0x800) // Pokey @800
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{
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pokey_SetRegister(0x4000 | (address & 0x0F), data);
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return;
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}
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}
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}
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if (((u8*)0x06820000)[address]) // We use 64K of faster VRAM to hold the bits to tell us if this area is writable... speeds up things slightly...
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{
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// ---------------------------------------------------------------------------------------
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// If this write would be in normal (non bankset) memory, we need to keep the bankset
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// memory up to date as well... This speeds up processing in Maria for banksets handling.
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// ---------------------------------------------------------------------------------------
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extern byte banksets_memory[]; extern u16 banksets_mask;
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if (!(address & banksets_mask)) banksets_memory[address] = data;
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if ((address & 0xF800)) // Base RAM is at 0x1800 and HSC SRAM is at 0x1000 so this will find anything that is RAM...
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{
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// For banking RAM we need to keep the shadow up to date.
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if ((address & 0xC000) == 0x4000)
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{
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extern u8 *shadow_ram;
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shadow_ram[address] = data;
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if (myCartInfo.cardtype == CARTRIDGE_TYPE_FRACTALUS)
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{
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// Special EXRAM/A8 handling... mirror ram
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memory_ram[address ^0x0100] = data;
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}
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}
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else if ((address & 0xF800) == 0x1000) // HSC RAM - set the dirty bit so we persist the .hsc file in the main loop
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{
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bHSC_dirty = 1;
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}
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memory_ram[address] = data;
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return;
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}
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if (address >= 0x460 && address < 0x480) return; // XM/Yamaha is mapped into this area... do not respond to it as we are not XM capable (yet)
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switch(address) {
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case INPTCTRL:
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if(data == 22 && cartridge_IsLoaded( )) {
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cartridge_Store( );
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}
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break;
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case INPT0:
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break;
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case INPT1:
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break;
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case INPT2:
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break;
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case INPT3:
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break;
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case INPT4:
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break;
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case INPT5:
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break;
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case BACKGRND:
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memory_ram[BACKGRND] = data;
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bg8 = data;
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bg32 = data | (data<<8) | (data<<16) | (data<<24);
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break;
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case CHARBASE:
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memory_ram[CHARBASE] = data;
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maria_charbase = data;
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break;
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case AUDC0:
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tia_audc[0] = data & 15;
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tia_MemoryChannel(0);
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break;
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case AUDC1:
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tia_audc[1] = data & 15;
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tia_MemoryChannel(1);
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break;
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case AUDF0:
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tia_audf[0] = data & 31;
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tia_MemoryChannel(0);
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break;
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case AUDF1:
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tia_audf[1] = data & 31;
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tia_MemoryChannel(1);
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break;
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case AUDV0:
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tia_audv[0] = (data & 15) << 2;
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tia_MemoryChannel(0);
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break;
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case AUDV1:
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tia_audv[1] = (data & 15) << 2;
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tia_MemoryChannel(1);
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break;
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case WSYNC:
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memory_ram[WSYNC] = true;
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riot_and_wsync |= 0x01;
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break;
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case SWCHB:
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/*gdement: Writing here actually writes to DRB inside the RIOT chip.
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This value only indirectly affects output of SWCHB.*/
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riot_SetDRB(data);
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break;
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case SWCHA:
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if (myCartInfo.cardctrl1 == SNES)
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{
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extern byte riot_dra;
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if ((data & 0x20) != (riot_dra & 0x20)) // Change of Latch state
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{
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snes_bit_pos = 0;
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if (snes_adaptor & (1 << snes_bit_pos)) memory_ram[INPT4] |= 0x80; else memory_ram[INPT4] &= 0x7F;
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}
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if ((data & 0x10) != (riot_dra & 0x10)) // Change of Clock state
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{
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if (data & 0x10) // Clock going High
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{
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snes_bit_pos++;
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}
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else // Clock going low
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{
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if (snes_bit_pos >= 17) snes_bit_pos=0;
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if (snes_adaptor & (1 << snes_bit_pos)) memory_ram[INPT4] |= 0x80; else memory_ram[INPT4] &= 0x7F;
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}
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}
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}
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riot_SetDRA(data);
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break;
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case TIM1T:
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case TIM1T | 0x8:
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riot_SetTimer(TIM1T, data);
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break;
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case TIM8T:
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case TIM8T | 0x8:
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riot_SetTimer(TIM8T, data);
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break;
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case TIM64T:
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case TIM64T | 0x8:
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riot_SetTimer(TIM64T, data);
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break;
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case T1024T:
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case T1024T | 0x8:
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riot_SetTimer(T1024T, data);
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break;
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default:
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memory_ram[address] = data;
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#ifdef RAM_MIRRORS_ENABLED // Technically the RAM mirrors are here but we don't really care... we assume anyone using a mirror will read back from that same mirror location.
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if (address >= 8256)
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{
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// 0x2040 -> 0x20ff (0x2000)
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if(address >= 8256 && address <= 8447)
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{
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memory_ram[address - 8192] = data;
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}
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// 0x2140 -> 0x21ff (0x2000)
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else if(address >= 8512 && address <= 8703)
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{
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memory_ram[address - 8192] = data;
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}
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}
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else if (address <= 511)
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{
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// 0x40 -> 0xff (0x2000)
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if(address >= 64 && address <= 255)
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{
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memory_ram[address + 8192] = data;
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}
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// 0x140 -> 0x1ff (0x2000)
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else if(address >= 320 && address <= 511)
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{
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memory_ram[address + 8192] = data;
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}
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}
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#endif
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break;
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}
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}
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else
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{
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cartridge_Write(address, data);
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}
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}
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// ----------------------------------------------------------------------------
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// WriteROM
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// ----------------------------------------------------------------------------
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ITCM_CODE void memory_WriteROM(word address, u32 size, const byte* data)
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{
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u32* ramPtr = (u32*)&memory_ram[address];
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u32* romPtr = (u32*)&is_memory_writable[address];
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u32* dataPtr = (u32*)data;
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for (u32 i=0; i<(size>>2); i++)
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{
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*ramPtr++ = *dataPtr++;
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*romPtr++ = 0x00000000;
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}
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}
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// ----------------------------------------------------------------------------
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// WriteROMFast (assumes is_memory_writable[] already set properly)
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// size is already in multiples of u32 dwords
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// ----------------------------------------------------------------------------
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ITCM_CODE void memory_WriteROMFast(word address, u32 size, const u32* data)
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{
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u32* ramPtr = (u32*)&memory_ram[address];
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u32* dataPtr = (u32*)data;
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u16 size2 = size;
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do
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{
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*ramPtr++ = *dataPtr++;
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*ramPtr++ = *dataPtr++;
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*ramPtr++ = *dataPtr++;
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*ramPtr++ = *dataPtr++;
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}
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while (--size2);
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}
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// ----------------------------------------------------------------------------
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// ClearROM
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// ----------------------------------------------------------------------------
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void memory_ClearROM(word address, word size)
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{
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memset(&memory_ram[address], 0x00, size);
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memset(&is_memory_writable[address], 0xFF, size);
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}
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