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https://github.com/rvtr/twl_wrapsdk.git
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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@74 4ee2a332-4b2b-5046-8439-1ba90f034370
92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
/*---------------------------------------------------------------------------*
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Project: NitroSDK - include - PXI
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File: regname.h
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Copyright 2003-2005 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Log: regname.h,v $
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Revision 1.3 2005/02/28 05:26:03 yosizaki
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do-indent.
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Revision 1.2 2004/05/14 09:34:00 yasu
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add ARM9/ARM7 sync in PXI_Init
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Revision 1.1 2004/03/04 08:44:26 yasu
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add defines for fifo access
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$NoKeywords: $
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*---------------------------------------------------------------------------*/
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#ifndef NITRO_PXI_COMMON_REGNAME_H_
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#define NITRO_PXI_COMMON_REGNAME_H_
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#include <nitro/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register rename
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typedef enum
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{
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PXI_PROC_ARM9 = 0,
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PXI_PROC_ARM7 = 1
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}
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PXIProc;
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#ifdef SDK_ARM9
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#define PXI_PROC_ARM PXI_PROC_ARM9
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#define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT
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#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK
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#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK
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#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK
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#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK
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#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK
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#define reg_PXI_INTF reg_PXI_SUBPINTF
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#define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK
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#define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK
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#define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A9STATUS_MASK
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#define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT
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#define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A7STATUS_MASK
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#define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A7STATUS_SHIFT
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#else // SDK_ARM7
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#define PXI_PROC_ARM PXI_PROC_ARM7
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#define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT
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#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK
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#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK
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#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK
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#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK
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#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK
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#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK
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#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK
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#define reg_PXI_INTF reg_PXI_MAINPINTF
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#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK
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#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK
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#define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A7STATUS_MASK
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#define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A7STATUS_SHIFT
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#define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A9STATUS_MASK
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#define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT
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#endif
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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/* NITRO_PXI_COMMON_REGNAME_H_ */
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#endif
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