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678 lines
22 KiB
C
678 lines
22 KiB
C
/*---------------------------------------------------------------------------*
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Project: NitroSDK - MI - include
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File: exMemory.h
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Copyright 2003-2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Log: exMemory.h,v $
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Revision 1.35 2007/02/20 00:28:11 kitase_hirotake
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indent source
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Revision 1.34 2006/04/28 11:03:24 yada
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MI_ functions or defines around PhiClock were changed to MIi_
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Revision 1.33 2006/01/18 02:11:19 kitase_hirotake
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do-indent
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Revision 1.32 2005/02/28 05:26:02 yosizaki
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do-indent.
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Revision 1.31 2005/02/09 07:25:29 yada
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change function name CTRDG_SetAgbFastestRomCycle to MI_SetAgbCartridgeFastestRomCycle()
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Revision 1.30 2005/02/04 12:44:02 yada
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add CTRDG_SetAgbFastestRomCycle()
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Revision 1.29 2004/11/12 10:52:42 yada
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fix argument name of MI_SetPhiControl/MI_SetPhiClock
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Revision 1.28 2004/11/04 04:41:20 yada
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fix a little
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Revision 1.27 2004/11/04 04:23:14 yada
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fix a little
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Revision 1.26 2004/07/16 13:53:12 yada
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fix register address MI_GetPhiControl accesses
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Revision 1.25 2004/07/01 07:06:26 yada
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fix MI_Set/GetRomCartridgeCycle1/2 -> 1st/2nd
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Revision 1.24 2004/05/26 01:15:58 yada
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arrange comments
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Revision 1.23 2004/05/25 09:08:33 yada
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change name of function which access cartridge.
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add 'Cartridge'
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Revision 1.22 2004/05/14 10:30:23 takano_makoto
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Change #if SDK_ARM9 -> #ifdef SDK_ARM9
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Revision 1.21 2004/04/07 02:03:17 yada
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fix header comment
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Revision 1.20 2004/03/25 07:26:05 yada
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MIi_SetMainMemoryPriority ‚ð MI_<49>`‚É
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Revision 1.19 2004/03/25 02:38:01 yada
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MI_SetMainMemoryPriority(), MI_SetCardProcessor(),MI_SetCartridgeProcessor()
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‚ð<E2809A>AMI_<49>`‚©‚çMIi_<69>` ‚É•Ï<E280A2>X‚µ“à•”ŠÖ<C5A0>”‚É‚·‚é‚悤‚É‚µ‚½<E2809A>B
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Revision 1.18 2004/03/25 02:19:48 yada
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ARM7 ‚Å‚Í<E2809A>AMI_SetMainMemoryPriority(), MI_SetCardProcessor(),
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MI_SetCartridgeProcessor() Ž©‘Ì‚ð’è‹`‚µ‚È‚¢‚悤‚É‚µ‚½<E2809A>B
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Revision 1.17 2004/03/12 12:11:42 yada
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only arrange spacing
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Revision 1.16 2004/03/10 01:17:41 yada
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ASSERT<52>C<EFBFBD>³
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Revision 1.15 2004/03/09 09:56:05 yada
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ARM7‘¤‚Ì EXMEMCNT_L<5F>AEXMEMCNT_H ‹L<E280B9>q‚É•¹‚¹‚½•Ï<E280A2>X
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Revision 1.14 2004/02/12 13:33:09 yasu
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include nitro/ioreg.h
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Revision 1.13 2004/02/12 10:56:04 yasu
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new location of include files ARM9/ARM7
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Revision 1.12 2004/02/05 12:21:14 yasu
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change SDK prefix iris -> nitro
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Revision 1.11 2004/02/05 07:09:03 yasu
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change SDK prefix iris -> nitro
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Revision 1.10 2004/01/17 02:28:38 nishida_kenji
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convert 'inline' to 'static inline' in header files
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Revision 1.9 2004/01/16 07:28:45 yada
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processor ƒAƒT<C692>[ƒg<C692>C<EFBFBD>³
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Revision 1.8 2004/01/14 01:42:55 yada
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ŠÖ<C5A0>”–¼•Ï<E280A2>X
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OS_IrisCardPriority <20>¨ OS_CardProcessor
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OS_CartridgePriority <20>¨ OS_CartridgeProcessor
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Revision 1.7 2004/01/08 06:01:03 yada
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Phi ‚Í Physical ‚É”ñ‚¸<E2809A>B–¼<E28093>Ì<EFBFBD>C<EFBFBD>³
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Revision 1.6 2003/12/25 09:42:57 yada
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ASSERT‚Ì•s‹ï<E280B9>‡’ù<E28099>³
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Revision 1.5 2003/12/25 07:30:28 yada
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Œ^ƒ‹<C692>[ƒ‹“<E280B9>ˆê‚É‚æ‚é•Ï<E280A2>X
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Revision 1.4 2003/12/18 12:15:15 yada
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assertion’ljÁ
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Revision 1.3 2003/12/18 07:16:40 yada
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red-sdk Žd—l‚©‚ç•Ï<E280A2>X
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Revision 1.2 2003/12/08 12:17:34 yada
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‘å•<C3A5>•Ï<E280A2>X
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Revision 1.1 2003/11/28 01:55:30 yada
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REDSDK‚Ì03-11-27”½‰f
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$NoKeywords: $
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*---------------------------------------------------------------------------*/
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#ifndef NITRO_MI_EXMEMORY_H_
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#define NITRO_MI_EXMEMORY_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <nitro/ioreg.h>
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//----------------------------------------------------------------
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// alias for ARM7
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#ifdef SDK_ARM7
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#define reg_MI_EXMEMCNT reg_MI_EXMEMCNT_L
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#define REG_MI_EXMEMCNT_EP_SHIFT REG_MI_EXMEMCNT_L_EP_SHIFT
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#define REG_MI_EXMEMCNT_EP_SIZE REG_MI_EXMEMCNT_L_EP_SIZE
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#define REG_MI_EXMEMCNT_EP_MASK REG_MI_EXMEMCNT_L_EP_MASK
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#define REG_MI_EXMEMCNT_MP_SHIFT REG_MI_EXMEMCNT_L_MP_SHIFT
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#define REG_MI_EXMEMCNT_MP_SIZE REG_MI_EXMEMCNT_L_MP_SIZE
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#define REG_MI_EXMEMCNT_MP_MASK REG_MI_EXMEMCNT_L_MP_MASK
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#define REG_MI_EXMEMCNT_MP_B_SHIFT REG_MI_EXMEMCNT_L_MP_B_SHIFT
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#define REG_MI_EXMEMCNT_MP_B_SIZE REG_MI_EXMEMCNT_L_MP_B_SIZE
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#define REG_MI_EXMEMCNT_MP_B_MASK REG_MI_EXMEMCNT_L_MP_B_MASK
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#define REG_MI_EXMEMCNT_CP_SHIFT REG_MI_EXMEMCNT_L_CP_SHIFT
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#define REG_MI_EXMEMCNT_CP_SIZE REG_MI_EXMEMCNT_L_CP_SIZE
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#define REG_MI_EXMEMCNT_CP_MASK REG_MI_EXMEMCNT_L_CP_MASK
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#define REG_MI_EXMEMCNT_PHI_SHIFT REG_MI_EXMEMCNT_L_PHI_SHIFT
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#define REG_MI_EXMEMCNT_PHI_SIZE REG_MI_EXMEMCNT_L_PHI_SIZE
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#define REG_MI_EXMEMCNT_PHI_MASK REG_MI_EXMEMCNT_L_PHI_MASK
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#define REG_MI_EXMEMCNT_ROM2nd_SHIFT REG_MI_EXMEMCNT_L_ROM2nd_SHIFT
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#define REG_MI_EXMEMCNT_ROM2nd_SIZE REG_MI_EXMEMCNT_L_ROM2nd_SIZE
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#define REG_MI_EXMEMCNT_ROM2nd_MASK REG_MI_EXMEMCNT_L_ROM2nd_MASK
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#define REG_MI_EXMEMCNT_ROM1st_SHIFT REG_MI_EXMEMCNT_L_ROM1st_SHIFT
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#define REG_MI_EXMEMCNT_ROM1st_SIZE REG_MI_EXMEMCNT_L_ROM1st_SIZE
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#define REG_MI_EXMEMCNT_ROM1st_MASK REG_MI_EXMEMCNT_L_ROM1st_MASK
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#define REG_MI_EXMEMCNT_RAM_SHIFT REG_MI_EXMEMCNT_L_RAM_SHIFT
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#define REG_MI_EXMEMCNT_RAM_SIZE REG_MI_EXMEMCNT_L_RAM_SIZE
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#define REG_MI_EXMEMCNT_RAM_MASK REG_MI_EXMEMCNT_L_RAM_MASK
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#endif // SDK_ARM7
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//----------------------------------------------------------------
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//---- Access priority
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typedef enum
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{
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MI_PROCESSOR_ARM9 = 0, // Main processor
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MI_PROCESSOR_ARM7 = 1 // Sub processor
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}
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MIProcessor;
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//---- PHI output control
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typedef enum
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{
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MIi_PHI_CLOCK_LOW = 0, // Low level
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MIi_PHI_CLOCK_4MHZ = 1, // 4.19 MHz
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MIi_PHI_CLOCK_8MHZ = 2, // 8.38 MHz
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MIi_PHI_CLOCK_16MHZ = 3 // 16.76 MHz
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}
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MIiPhiClock;
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//---- cartridge ROM 1st access cycle
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typedef enum
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{
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MI_CTRDG_ROMCYCLE1_10 = 0, // 10 cycle
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MI_CTRDG_ROMCYCLE1_8 = 1, // 8 cycle
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MI_CTRDG_ROMCYCLE1_6 = 2, // 6 cycle
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MI_CTRDG_ROMCYCLE1_18 = 3 // 18 cycle
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}
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MICartridgeRomCycle1st;
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//---- cartridge ROM 2nd access cycle
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typedef enum
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{
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MI_CTRDG_ROMCYCLE2_6 = 0, // 6 cycle
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MI_CTRDG_ROMCYCLE2_4 = 1 // 4 cycle
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}
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MICartridgeRomCycle2nd;
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//---- cartridge RAM access cycle
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typedef enum
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{
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MI_CTRDG_RAMCYCLE_10 = 0, // 10 cycle
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MI_CTRDG_RAMCYCLE_8 = 1, // 8 cycle
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MI_CTRDG_RAMCYCLE_6 = 2, // 6 cycle
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MI_CTRDG_RAMCYCLE_18 = 3 // 18 cycle
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}
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MICartridgeRamCycle;
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//---- Wireless System (Wait State 0) control 1st wait (for ARM7)
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typedef enum
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{
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MI_WMWAIT0_1_9 = 0, // 9 wait
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MI_WMWAIT0_1_7 = 1, // 7 wait
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MI_WMWAIT0_1_5 = 2, // 5 wait
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MI_WMWAIT0_1_17 = 3 // 17 wait
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}
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MIWMWait0_1;
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//---- Wireless System (Wait State 0) control 2nd wait (for ARM7)
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typedef enum
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{
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MI_WMWAIT0_2_5 = 0, // 5 wait
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MI_WMWAIT0_2_3 = 1 // 3 wait
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}
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MIWMWait0_2;
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//---- Wireless System (Wait State 1) control 1st wait (for ARM7)
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typedef enum
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{
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MI_WMWAIT1_1_9 = 0, // 9 wait
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MI_WMWAIT1_1_7 = 1, // 7 wait
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MI_WMWAIT1_1_5 = 2, // 5 wait
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MI_WMWAIT1_1_17 = 3 // 17 wait
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}
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MIWMWait1_1;
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//---- Wireless System (Wait State 1) control 2nd wait (for ARM7)
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typedef enum
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{
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MI_WMWAIT1_2_9 = 0, // 9 wait
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MI_WMWAIT1_2_3 = 1 // 3 wait
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}
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MIWMWait1_2;
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//---- PHI Control (for ARM7)
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typedef enum
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{
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MI_PHI_CLOCK_CARTRIDGE = 0, // conform to cartridge setting
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MI_PHI_CLOCK_33MHZ = 1 // 33.51 MHz output from PHI (default)
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}
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MIPhiControl;
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//----------------------------------------------------------------
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// assert definition
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//
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#define MI_PROCESSOR_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_PROCESSOR_ARM7 )
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#define MI_PHICLOCK_ASSERT( x ) SDK_ASSERT( (u32)x <= MIi_PHI_CLOCK_16MHZ )
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#define MI_ROMCYCLE1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_ROMCYCLE1_18 )
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#define MI_ROMCYCLE2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_ROMCYCLE2_4 )
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#define MI_RAMCYCLE_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_RAMCYCLE_18 )
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#define MI_WMWAIT0_1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT0_1_17 )
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#define MI_WMWAIT0_2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT0_2_3 )
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#define MI_WMWAIT1_1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT1_1_17 )
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#define MI_WMWAIT1_2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT1_2_3 )
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#define MI_PHICONTROL_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_PHI_CLOCK_33MHZ )
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//================================================================
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// priority setting
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//================================================================
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//----------------
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// set/get of access priority : main memory
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#ifdef SDK_ARM9
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static inline void MI_SetMainMemoryPriority(MIProcessor proc)
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{
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MI_PROCESSOR_ASSERT(proc);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_EP_MASK) | (proc << REG_MI_EXMEMCNT_EP_SHIFT));
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}
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#endif
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static inline MIProcessor MI_GetMainMemoryPriority(void)
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{
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return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_EP_MASK) >> REG_MI_EXMEMCNT_EP_SHIFT);
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}
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//----------------
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// set/get of access priority : NITRO card
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#ifdef SDK_ARM9
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static inline void MIi_SetCardProcessor(MIProcessor proc)
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{
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MI_PROCESSOR_ASSERT(proc);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_MASK) | (proc << REG_MI_EXMEMCNT_MP_SHIFT));
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}
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static inline void MIi_SetExCardProcessor(MIProcessor proc)
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{
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MI_PROCESSOR_ASSERT(proc);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_B_MASK) | (proc << REG_MI_EXMEMCNT_MP_B_SHIFT));
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}
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#endif
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static inline MIProcessor MI_GetCardProcessor(void)
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{
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return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_MP_MASK) >> REG_MI_EXMEMCNT_MP_SHIFT);
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}
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static inline MIProcessor MI_GetExCardProcessor(void)
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{
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return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_MP_B_MASK) >> REG_MI_EXMEMCNT_MP_B_SHIFT);
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}
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//----------------
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// set/get of access priority : Cartridge
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#ifdef SDK_ARM9
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static inline void MIi_SetCartridgeProcessor(MIProcessor proc)
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{
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MI_PROCESSOR_ASSERT(proc);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_CP_MASK) | (proc << REG_MI_EXMEMCNT_CP_SHIFT));
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}
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#endif
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static inline MIProcessor MI_GetCartridgeProcessor(void)
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{
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return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_CP_MASK) >> REG_MI_EXMEMCNT_CP_SHIFT);
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}
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//================================================================
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// speed and control setting
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//================================================================
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/*---------------------------------------------------------------------------*
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Name: MIi_SetPhiClock
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Description: set PHI output clock
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Arguments: clock : Phi clock to set
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Returns: None
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*---------------------------------------------------------------------------*/
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static inline void MIi_SetPhiClock(MIiPhiClock clock)
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{
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MI_PHICLOCK_ASSERT(clock);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_PHI_MASK) | (clock << REG_MI_EXMEMCNT_PHI_SHIFT));
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}
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/*---------------------------------------------------------------------------*
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Name: MIi_GetPhiClock
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Description: get PHI output clock
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Arguments: None
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Returns: Phi clock
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*---------------------------------------------------------------------------*/
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static inline MIiPhiClock MIi_GetPhiClock(void)
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{
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return (MIiPhiClock) ((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_PHI_MASK) >>
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REG_MI_EXMEMCNT_PHI_SHIFT);
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}
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/*---------------------------------------------------------------------------*
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Name: MI_SetCartridgeRomCycle1st
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Description: set Cartridge ROM 1st access cycle
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Arguments: c1 : access cycle to set
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Returns: None
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*---------------------------------------------------------------------------*/
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static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1)
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{
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MI_ROMCYCLE1_ASSERT(c1);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM1st_MASK) |
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(c1 << REG_MI_EXMEMCNT_ROM1st_SHIFT));
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}
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/*---------------------------------------------------------------------------*
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Name: MI_GetCartridgeRomCycle1st
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Description: get Cartridge ROM 1st access cycle
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Arguments: None
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Returns: cartridge ROM 1st access cycle
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*---------------------------------------------------------------------------*/
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static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void)
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{
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return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM1st_MASK) >>
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REG_MI_EXMEMCNT_ROM1st_SHIFT);
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}
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/*---------------------------------------------------------------------------*
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Name: MI_SetCartridgeRomCycle2nd
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Description: set Cartridge ROM 2nd access cycle
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Arguments: c2 : access cycle to set
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Returns: None
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*---------------------------------------------------------------------------*/
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static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2)
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{
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MI_ROMCYCLE2_ASSERT(c2);
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM2nd_MASK) |
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(c2 << REG_MI_EXMEMCNT_ROM2nd_SHIFT));
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}
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/*---------------------------------------------------------------------------*
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Name: MI_GetCartridgeRomCycle2nd
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Description: get Cartridge ROM 2nd access cycle
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Arguments: None
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Returns: cartridge ROM 2nd access cycle
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*---------------------------------------------------------------------------*/
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static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void)
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{
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return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM2nd_MASK) >>
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REG_MI_EXMEMCNT_ROM2nd_SHIFT);
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}
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/*---------------------------------------------------------------------------*
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Name: MI_SetAgbCartridgeFastestRomCycle
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Description: set Cartridge ROM access cycles for AGB. (8-4 cycle)
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Arguments: prev1st : pointer to be store the previous 1st ROM access cycle.
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if NULL, no effect.
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prev2nd : pointer to be store the previous 2nd ROM access cycle.
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if NULL, no effect.
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||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void MI_SetAgbCartridgeFastestRomCycle(MICartridgeRomCycle1st *prev1st,
|
||
MICartridgeRomCycle2nd *prev2nd);
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetCartridgeRamCycle
|
||
|
||
Description: set Cartridge RAM access cycle
|
||
|
||
Arguments: c : access cycle to set
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c)
|
||
{
|
||
MI_RAMCYCLE_ASSERT(c);
|
||
reg_MI_EXMEMCNT =
|
||
(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_RAM_MASK) | (c << REG_MI_EXMEMCNT_RAM_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetCartridgeRamCycle
|
||
|
||
Description: get Cartridge RAM access cycle
|
||
|
||
Arguments: None
|
||
|
||
Returns: cartridge RAM access cycle
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void)
|
||
{
|
||
return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_RAM_MASK) >>
|
||
REG_MI_EXMEMCNT_RAM_SHIFT);
|
||
}
|
||
|
||
|
||
//================================================================
|
||
// speed and control setting (for ARM7)
|
||
//================================================================
|
||
#ifdef SDK_ARM7
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetWM0Wait1st
|
||
|
||
Description: set 1st wait to Wireless system area at wait state 0
|
||
(this function is for ARM7)
|
||
|
||
Arguments: wait : 1st wait to set
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetWM0Wait1st(MIWMWait0_1 wait)
|
||
{
|
||
MI_WMWAIT0_1_ASSERT(wait);
|
||
reg_MI_EXMEMCNT_H =
|
||
(u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_1st_MASK) |
|
||
(wait << REG_MI_EXMEMCNT_H_WW0_1st_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetWM0Wait1st
|
||
|
||
Description: get 1st wait to Wireless system area at wait state 0
|
||
(this function is for ARM7)
|
||
|
||
Arguments: None
|
||
|
||
Returns: 1st wait to wireless system area at wait state 0
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MIWMWait0_1 MI_GetWM0Wait1st(void)
|
||
{
|
||
return (MIWMWait0_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_1st_MASK) >>
|
||
REG_MI_EXMEMCNT_H_WW0_1st_SHIFT);
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetWM0Wait2nd
|
||
|
||
Description: set 2nd wait to Wireless system area at wait state 0
|
||
(this function is for ARM7)
|
||
|
||
Arguments: wait : 2nd wait to set
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetWM0Wait2nd(MIWMWait0_2 wait)
|
||
{
|
||
MI_WMWAIT0_2_ASSERT(wait);
|
||
reg_MI_EXMEMCNT_H =
|
||
(u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_2nd_MASK) |
|
||
(wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetWM0Wait2nd
|
||
|
||
Description: get 2nd wait to Wireless system area at wait state 0
|
||
(this function is for ARM7)
|
||
|
||
Arguments: None
|
||
|
||
Returns: 2nd wait to wireless system area at wait state 0
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MIWMWait0_2 MI_GetWM0Wait2nd(void)
|
||
{
|
||
return (MIWMWait0_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_2nd_MASK) >>
|
||
REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT);
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetWM1Wait1st
|
||
|
||
Description: set 1st wait to Wireless system area at wait state 1
|
||
(this function is for ARM7)
|
||
|
||
Arguments: wait : 1st wait to set
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetWM1Wait1st(MIWMWait1_1 wait)
|
||
{
|
||
MI_WMWAIT1_1_ASSERT(wait);
|
||
reg_MI_EXMEMCNT_H =
|
||
(u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_1st_MASK) |
|
||
(wait << REG_MI_EXMEMCNT_H_WW1_1st_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetWM1Wait1st
|
||
|
||
Description: get 1st wait to Wireless system area at wait state 1
|
||
(this function is for ARM7)
|
||
|
||
Arguments: None
|
||
|
||
Returns: 1st wait to wireless system area at wait state 1
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MIWMWait1_1 MI_GetWM1Wait1st(void)
|
||
{
|
||
return (MIWMWait1_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_1st_MASK) >>
|
||
REG_MI_EXMEMCNT_H_WW1_1st_SHIFT);
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetWM1Wait2nd
|
||
|
||
Description: set 2nd wait to Wireless system area at wait state 1
|
||
(this function is for ARM7)
|
||
|
||
Arguments: wait : 2nd wait to set
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetWM1Wait2nd(MIWMWait1_2 wait)
|
||
{
|
||
MI_WMWAIT1_2_ASSERT(wait);
|
||
reg_MI_EXMEMCNT_H =
|
||
(u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_2nd_MASK) |
|
||
(wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetWM1Wait2nd
|
||
|
||
Description: get 2nd wait to Wireless system area at wait state 1
|
||
(this function is for ARM7)
|
||
|
||
Arguments: None
|
||
|
||
Returns: 2nd wait to wireless system area at wait state 1
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MIWMWait1_2 MI_GetWM1Wait2nd(void)
|
||
{
|
||
return (MIWMWait1_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_2nd_MASK) >>
|
||
REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT);
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_SetPhiControl
|
||
|
||
Description: set PHI control
|
||
(this function is for ARM7)
|
||
|
||
Arguments: control : PHI setting
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
static inline void MI_SetPhiControl(MIPhiControl control)
|
||
{
|
||
MI_PHICONTROL_ASSERT(control);
|
||
reg_MI_EXMEMCNT_H =
|
||
(u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_PHI33M_MASK) |
|
||
(control << REG_MI_EXMEMCNT_H_PHI33M_SHIFT));
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: MI_GetPhiControl
|
||
|
||
Description: get PHI control
|
||
(this function is for ARM7)
|
||
|
||
Arguments: None
|
||
|
||
Returns: PHI control setting
|
||
*---------------------------------------------------------------------------*/
|
||
static inline MIPhiControl MI_GetPhiControl(void)
|
||
{
|
||
return (MIPhiControl)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_PHI33M_MASK) >>
|
||
REG_MI_EXMEMCNT_H_PHI33M_SHIFT);
|
||
}
|
||
|
||
#endif // ifdef SDK_ARM7
|
||
|
||
|
||
|
||
#ifdef __cplusplus
|
||
} /* extern "C" */
|
||
#endif
|
||
|
||
/* NITRO_MI_EXMEMORY_H_ */
|
||
#endif
|