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063cbd2c62
git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@47 4ee2a332-4b2b-5046-8439-1ba90f034370
183 lines
6.1 KiB
C
183 lines
6.1 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlSDK - MI - include
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File: wram_abc.h
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Log: $
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$NoKeywords: $
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*---------------------------------------------------------------------------*/
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#ifndef TWL_MI_WRAM_ABC_H_
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#define TWL_MI_WRAM_ABC_H_
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#include <twl/ioreg.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//----------------------------------------------------------------
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// enum definition
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//
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typedef enum
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{
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MI_WRAM_A_ARM9 = 0 << REG_MI_WRAM_A0_MST_SHIFT,
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MI_WRAM_A_ARM7 = 1 << REG_MI_WRAM_A0_MST_SHIFT
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}
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MIWramA;
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typedef enum
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{
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MI_WRAM_B_ARM9 = 0 << REG_MI_WRAM_B0_MST_SHIFT,
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MI_WRAM_B_ARM7 = 1 << REG_MI_WRAM_B0_MST_SHIFT,
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MI_WRAM_B_DSP_I = 2 << REG_MI_WRAM_B0_MST_SHIFT
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}
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MIWramB;
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typedef enum
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{
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MI_WRAM_C_ARM9 = 0 << REG_MI_WRAM_C0_MST_SHIFT,
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MI_WRAM_C_ARM7 = 1 << REG_MI_WRAM_C0_MST_SHIFT,
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MI_WRAM_C_DSP_D = 2 << REG_MI_WRAM_C0_MST_SHIFT
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}
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MIWramC;
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typedef enum
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{
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MI_WRAM_A_OFS_0KB = 0 << REG_MI_WRAM_A0_OFS_SHIFT,
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MI_WRAM_A_OFS_64KB = 1 << REG_MI_WRAM_A0_OFS_SHIFT,
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MI_WRAM_A_OFS_128KB = 2 << REG_MI_WRAM_A0_OFS_SHIFT,
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MI_WRAM_A_OFS_192KB = 1 << REG_MI_WRAM_A0_OFS_SHIFT
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}
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MIOfsWramA;
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typedef enum
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{
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MI_WRAM_B_OFS_0KB = 0 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_32KB = 1 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_64KB = 2 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_96KB = 3 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_128KB = 4 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_160KB = 5 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_192KB = 6 << REG_MI_WRAM_B0_OFS_SHIFT,
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MI_WRAM_B_OFS_224KB = 7 << REG_MI_WRAM_B0_OFS_SHIFT
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}
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MIOfsWramB;
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typedef enum
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{
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MI_WRAM_C_OFS_0KB = 0 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_32KB = 1 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_64KB = 2 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_96KB = 3 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_128KB = 4 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_160KB = 5 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_192KB = 6 << REG_MI_WRAM_C0_OFS_SHIFT,
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MI_WRAM_C_OFS_224KB = 7 << REG_MI_WRAM_C0_OFS_SHIFT
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}
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MIOfsWramC;
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typedef enum
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{
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MI_WRAM_A_IMG_64KB = 0 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
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MI_WRAM_A_IMG_128KB = 1 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
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MI_WRAM_A_IMG_256KB = 2 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
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MI_WRAM_A_IMG_MIN = MI_WRAM_A_IMG_64KB,
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#ifdef BROM_PLATFORM_BB
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MI_WRAM_A_IMG_MAX = MI_WRAM_A_IMG_128KB
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#else // BROM_PLATFORM_TS
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MI_WRAM_A_IMG_MAX = MI_WRAM_A_IMG_256KB
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#endif // BROM_PLATFORM_TS
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}
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MIImageWramA;
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typedef enum
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{
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MI_WRAM_B_IMG_32KB = 0 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
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MI_WRAM_B_IMG_64KB = 1 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
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MI_WRAM_B_IMG_128KB = 2 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
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MI_WRAM_B_IMG_256KB = 3 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
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MI_WRAM_B_IMG_MIN = MI_WRAM_B_IMG_32KB,
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#ifdef BROM_PLATFORM_BB
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MI_WRAM_B_IMG_MAX = MI_WRAM_B_IMG_128KB
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#else // BROM_PLATFORM_TS
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MI_WRAM_B_IMG_MAX = MI_WRAM_B_IMG_256KB
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#endif // BROM_PLATFORM_TS
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}
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MIImageWramB;
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typedef enum
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{
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MI_WRAM_C_IMG_32KB = 0 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
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MI_WRAM_C_IMG_64KB = 1 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
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MI_WRAM_C_IMG_128KB = 2 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
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MI_WRAM_C_IMG_256KB = 3 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
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MI_WRAM_C_IMG_MIN = MI_WRAM_C_IMG_32KB,
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#ifdef BROM_PLATFORM_BB
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MI_WRAM_C_IMG_MAX = MI_WRAM_C_IMG_128KB
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#else // BROM_PLATFORM_TS
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MI_WRAM_C_IMG_MAX = MI_WRAM_C_IMG_256KB
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#endif // BROM_PLATFORM_TS
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}
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MIImageWramC;
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#define MI_WRAM_A_BLOCK_SIZE 0x00010000 // 64KB
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#define MI_WRAM_B_BLOCK_SIZE 0x00008000 // 32KB
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#define MI_WRAM_C_BLOCK_SIZE 0x00008000 // 32KB
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#ifdef BROM_PLATFORM_BB
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#define MI_WRAM_A_BLOCK_NUM 2
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#define MI_WRAM_B_BLOCK_NUM 4
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#define MI_WRAM_C_BLOCK_NUM 4
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#else // BROM_PLATFORM_TS
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#define MI_WRAM_A_BLOCK_NUM 4
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#define MI_WRAM_B_BLOCK_NUM 8
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#define MI_WRAM_C_BLOCK_NUM 8
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#endif // BROM_PLATFORM_TS
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#define MI_WRAM_A_BLOCK_SIZE_MAX (MI_WRAM_A_BLOCK_SIZE * MI_WRAM_A_BLOCK_NUM)
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#define MI_WRAM_B_BLOCK_SIZE_MAX (MI_WRAM_B_BLOCK_SIZE * MI_WRAM_B_BLOCK_NUM)
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#define MI_WRAM_C_BLOCK_SIZE_MAX (MI_WRAM_C_BLOCK_SIZE * MI_WRAM_C_BLOCK_NUM)
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#define MI_WRAM_MAP_NULL (HW_WRAM_AREA + HW_WRAM_AREA_SIZE/4)
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#define REG_WRAM_A_MAP_PACK( start, end, img_size ) REG_WRAM_MAP_PACK( A, (start), (end), (img_size) )
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#define REG_WRAM_B_MAP_PACK( start, end, img_size ) REG_WRAM_MAP_PACK( B, (start), (end), (img_size) )
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#define REG_WRAM_C_MAP_PACK( start, end, img_size ) REG_WRAM_MAP_PACK( C, (start), (end), (img_size) )
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#define REG_WRAM_MAP_PACK( abc, start, end, img_size ) \
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( \
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(((((start) - HW_WRAM_AREA) / MI_WRAM_##abc##_BLOCK_SIZE) << REG_MI_WRAM_##abc##_MAP_START_SHIFT) & REG_MI_WRAM_##abc##_MAP_START_MASK) \
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| (((((end) - HW_WRAM_AREA) / MI_WRAM_##abc##_BLOCK_SIZE) << REG_MI_WRAM_##abc##_MAP_END_SHIFT) & REG_MI_WRAM_##abc##_MAP_END_MASK) \
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| (img_size) \
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)
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#define REG_WRAM_A_MAP_OFS_PACK( start_ofs, end_ofs ) REG_WRAM_MAP_OFS_PACK( A, (start_ofs), (end_ofs) )
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#define REG_WRAM_B_MAP_OFS_PACK( start_ofs, end_ofs ) REG_WRAM_MAP_OFS_PACK( B, (start_ofs), (end_ofs) )
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#define REG_WRAM_C_MAP_OFS_PACK( start_ofs, end_ofs ) REG_WRAM_MAP_OFS_PACK( C, (start_ofs), (end_ofs) )
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#define REG_WRAM_MAP_OFS_PACK( abc, start_ofs, end_ofs ) \
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( \
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((((start_ofs) / MI_WRAM_##abc##_BLOCK_SIZE) << REG_MI_WRAM_##abc##_MAP_START_SHIFT) & REG_MI_WRAM_##abc##_MAP_START_MASK) \
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| ((((end_ofs) / MI_WRAM_##abc##_BLOCK_SIZE) << REG_MI_WRAM_##abc##_MAP_END_SHIFT) & REG_MI_WRAM_##abc##_MAP_END_MASK) \
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)
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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/* TWL_MI_WRAM_ABC_H_ */
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#endif
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