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757 lines
25 KiB
C
757 lines
25 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlSDK - libraties - CDC_
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File: CDC__api.c
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Copyright 2006 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Log: $
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$NoKeywords: $
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*---------------------------------------------------------------------------*/
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#include <twl.h>
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#include <twl/cdc.h>
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#include "pm_pmic.h"
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BOOL isADCOn = FALSE;
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BOOL isDACOn = FALSE;
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#define CDC_PLL_STABLE_WAIT_TIME 18
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#define CDC_SCAN_MODE_TIMER_CLOCK_DIVIDER_VALUE 24
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static void CDCi_PowerUpPLL( void );
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static void CDCi_PowerDownPLL( void );
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//================================================================================
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// INIT APIs
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//================================================================================
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/*---------------------------------------------------------------------------*
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Name: CDC_Init
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Description: initialize codec
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_Init( void )
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{
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reg_CFG_CLK |= REG_CFG_CLK_SND_MASK;
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CDC_Reset();
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cdcRevisionID = CDC_GetRevisionId();
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CDCi_PowerUpPLL();
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CDC_InitSound();
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CDC_SetScanModeTimerClockDivider( CDC_SCAN_MODE_TIMER_CLOCK_DIVIDER_VALUE );
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_Reset
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Description: codec SW reset
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_Reset( void )
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{
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CDC_ChangePage( 0 );
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CDC_WriteI2cRegister( REG_CDC0_RST_ADDR, CDC0_RST_E );
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CDC_SetInputPinControl( TRUE, TRUE, TRUE ); // enable VCNT5,SP#HP,PMOFF pin
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OS_Sleep(1);
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_InitSound
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Description: initialize output sound(speaker/headphone) logic
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_InitSound( void )
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{
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#if 1 // <20><><EFBFBD>̃R<CC83>[<5B>h<EFBFBD>͖{<7B><><EFBFBD>AcdcInitSound<6E>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>[<5B>`<60><><EFBFBD><EFBFBD><EFBFBD>L<EFBFBD>q<EFBFBD><71><EFBFBD>ׂ<EFBFBD><D782>R<EFBFBD>[<5B>h<EFBFBD>B
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// Enable I2S
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reg_SND_I2SCNT |= REG_SND_I2SCNT_E_MASK;
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#endif
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// setup High Pass Filter of 9.26Hz cutoff freq.
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CDC_Init1stOrderFilter( cdc1stCoef_HPF_9_26Hz,
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CDC_FILTER_1ST_IIR_LDAC | CDC_FILTER_1ST_IIR_RDAC );
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// default, DACs are muted.
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// CDC_MuteDAC();
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// Setup DAC, Speaker Driver, Headphone Driver
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CDC_PowerUpDAC();
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CDC_SetupDAC( CDC_HP_DRV_PWON_TM_DEFAULT,
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CDC_HP_DRV_RAMPUP_TM_DEFAULT,
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CDC_HPSP_DRV_RAMPDWN_TM_DEFAULT );
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CDC_EnableHeadphoneDriver(); // enable headphone driver
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CDC_EnableSpeakerDriver(); // enable speaker driver
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CDC_UnmuteDAC();
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_InitMic
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Description: initialize microphone logic
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_InitMic( void )
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{
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// setup Mic Bias
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CDC_ChangePage( 1 );
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CDC_WriteI2cRegister( REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_2_5V );
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#if 1 // <20><><EFBFBD>̃R<CC83>[<5B>h<EFBFBD>͖{<7B><><EFBFBD>AcdcInitSound<6E>Ăяo<D18F><6F><EFBFBD><EFBFBD><EFBFBD>[<5B>`<60><><EFBFBD><EFBFBD><EFBFBD>L<EFBFBD>q<EFBFBD><71><EFBFBD>ׂ<EFBFBD><D782>R<EFBFBD>[<5B>h<EFBFBD>B
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// Enable I2S
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reg_SND_I2SCNT |= REG_SND_I2SCNT_E_MASK;
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#endif
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// setup High Pass Filter of 9.26Hz cutoff freq.
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CDC_Init1stOrderFilter( cdc1stCoef_HPF_9_26Hz, CDC_FILTER_1ST_IIR_ADC );
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// Setup ADC
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CDC_PowerUpADC();
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CDC_UnmuteADC();
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CDC_EnableAGC( CDC0_AGC_CTL1_DEFAULT_GAIN );
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}
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//================================================================================
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// Query APIs
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//================================================================================
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/*---------------------------------------------------------------------------*
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Name: CDC_IsTwlMode
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Description: check CTR-mode (True) or DS-mode (False)
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Arguments: None
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Returns: TRUE : CTR-mode, FALSE : DS-mode
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*---------------------------------------------------------------------------*/
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BOOL CDC_IsTwlMode( void )
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{
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return cdcIsTwlMode;
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_GetVendorId
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Description: get Vendor ID
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Arguments: None
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Returns: u8 Vendor ID
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*---------------------------------------------------------------------------*/
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u8 CDC_GetVendorId( void )
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{
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CDC_ChangePage( 0 );
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return CDC_ReadI2cRegister( REG_CDC0_VEND_ID_ADDR );
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_GetRevisionId
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Description: get Revision ID
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Arguments: None
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Returns: u8 Revision ID (3-bit value)
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*---------------------------------------------------------------------------*/
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u8 CDC_GetRevisionId( void )
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{
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CDC_ChangePage( 0 );
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return (u8)(( CDC_ReadI2cRegister( REG_CDC0_REV_ID_ADDR ) & CDC0_REV_ID_MASK ) >> CDC0_REV_ID_SHIFT);
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}
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//================================================================================
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// State Transition APIs
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//================================================================================
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/*---------------------------------------------------------------------------*
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Name: CDC_GoDsMode
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Description: transit from CTR-mode to DS-mode
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(never come back to CTR-mode without HW Reset)
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_GoDsMode( void )
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{
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CDC_ChangePage( 0 );
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//#ifdef CDC_REVISION_A
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// CODEC-IC bug workaround
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CDC_PowerUpADC();
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CDC_UnmuteADC();
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//#endif // CDC_REVISION_A
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///////////////// <20><><EFBFBD>N<D68C>̗v<CC97>]<5D>ɂ<EFBFBD><C982><EFBFBD>+7dB<64>ݒ<EFBFBD><DD92><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>i<EFBFBD>]<5D><><EFBFBD><EFBFBD>2.5<EFBFBD>{<7B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>j
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CDC_WriteI2cRegister( REG_CDC0_DIG_VOL_L_ADDR, 14 );
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CDC_WriteI2cRegister( REG_CDC0_DIG_VOL_R_ADDR, 14 );
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/////////////////
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// <20>}<7D>C<EFBFBD>N<EFBFBD>o<EFBFBD>C<EFBFBD>A<EFBFBD>X<EFBFBD><58><EFBFBD>ݒ肵<DD92>Ă<EFBFBD><C482><EFBFBD><EFBFBD>K<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BDS<44><53><EFBFBD>[<5B>h<EFBFBD>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD>
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// <20><><EFBFBD>̐ݒ<CC90><DD92><EFBFBD><EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>i<EFBFBD><69><EFBFBD>Ȃ<EFBFBD><C882>B
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CDC_ChangePage( 1 );
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CDC_WriteI2cRegister( REG_CDC1_MIC_BIAS_ADDR, CDC1_MIC_BIAS_2_5V );
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// PGA <20>ݒ<EFBFBD><DD92><EFBFBD><EFBFBD><EFBFBD><EFBFBD>l<EFBFBD>i18.8k <20>ݒ<EFBFBD><DD92><EFBFBD>DS<44>Ɠ<EFBFBD><C693><EFBFBD><EFBFBD>̃Q<CC83>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>j
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CDC_WriteI2cRegister( REG_CDC1_MIC_PGA_P_ADDR, 1 << CDC1_MIC_PGA_P_I_SHIFT);
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CDC_WriteI2cRegister( REG_CDC1_MIC_PGA_M_ADDR, 1 << CDC1_MIC_PGA_M_I_SHIFT);
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// PLL <20>ݒ<EFBFBD><DD92><EFBFBD> DS <20>p<EFBFBD>ɕύX
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CDC_WriteI2cRegister( REG_CDC0_PLL_J_ADDR, 21 );
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CDC_WriteI2cRegister( REG_CDC0_NDAC_DIV_ADDR, CDC0_NDAC_DIV_PWR | 7 );
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CDC_WriteI2cRegister( REG_CDC0_NADC_DIV_ADDR, CDC0_NADC_DIV_PWR | 7 );
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CDC_ChangePage( 3 );
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// READREADY <20>[<5B>q<EFBFBD><71><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TSC2046-PENINTERRUPT <20>ɕύX
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CDC_WriteI2cRegister( REG_CDC3_TP_CONV_MODE_ADDR, 0 );
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CDC_ChangePage( 255 );
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// enable DS-Mode (via reg5 : current page=255)
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//
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// DS-mode default
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// Master Sound Power OFF, MicBias OFF, MicPGA x40 times
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CDC_WriteI2cRegister( REG_CDC255_BKCMPT_MODE_ADDR, CDC255_BKCMPT_MODE_DS );
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//-------------------------------------------------------------------------
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// !! from now on, I2C cannot be used. Only DS-type PCSN,TCSN SPI can work.
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//-------------------------------------------------------------------------
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{
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// MicBias powered up
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// In Rev-A, MicBias must be powered up before enabling Master Sound Power
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CDC_DsmodeSetSpiFlags( REG_CDC255_DS_MIC_CTL_ADDR, CDC255_DS_MIC_CTL_BIAS_PWR );
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// enable Master Sound Power (via reg0 : current page=255)
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//
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// note: In Rev-A, if Master Sound Power is off, touch-panel logic does
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// not work.
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//
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// CODEC PCSN is connected to IO-board Analog Key CS.
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// CODEC PCSN is associated with TouchPanel now (for revision A).
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//
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CDC_DsmodeSetSpiFlags( REG_CDC255_AUD_CTL_ADDR, CDC255_AUD_CTL_PWR );
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}
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// change CODEC status variable
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cdcIsTwlMode = FALSE;
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_SetInputPinControl
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Description: set if input pin control enabled or not.
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Usually, PMOFF should not be disabled.
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Arguments: BOOL enable_vcnt5 : set TRUE to enable VCNT5(LCD backlight) pin
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BOOL enable_sphp : set TRUE to enable SP#HP switching pin
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BOOL enable_pmoff : set TRUE to enable PMOFF pin
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_SetInputPinControl( BOOL enable_vcnt5, BOOL enable_sphp, BOOL enable_pmoff )
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{
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u8 work = 0;
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CDC_ChangePage( 0 );
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if (enable_vcnt5) work = CDC0_PIN_CTL1_VCNT5_E;
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if (enable_sphp) work |= CDC0_PIN_CTL1_SPHP_E;
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CDC_WriteI2cRegister( REG_CDC0_PIN_CTL1_ADDR, work );
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work = 0;
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if (enable_pmoff) work = CDC0_PIN_CTL2_PMOFF_E;
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CDC_WriteI2cRegister( REG_CDC0_PIN_CTL2_ADDR, work );
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_GetInputPinControl
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Description: get if input pin control enabled or not.
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Arguments: BOOL *enable_vcnt5 : get TRUE if VCNT5(LCD backlight) pin is enabled
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BOOL *enable_sphp : get TRUE if SP#HP switching pin is enabled
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BOOL *enable_pmoff : get TRUE if PMOFF pin is enabled
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_GetInputPinControl( BOOL *enable_vcnt5, BOOL *enable_sphp, BOOL *enable_pmoff )
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{
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u8 work;
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*enable_vcnt5 = FALSE;
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*enable_sphp = FALSE;
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*enable_pmoff = FALSE;
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CDC_ChangePage( 0 );
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work = CDC_ReadI2cRegister( REG_CDC0_PIN_CTL1_ADDR );
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if ((work & CDC0_PIN_CTL1_VCNT5_MASK) == CDC0_PIN_CTL1_VCNT5_E)
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*enable_vcnt5 = TRUE;
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if ((work & CDC0_PIN_CTL1_SPHP_MASK) == CDC0_PIN_CTL1_SPHP_E)
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*enable_sphp = TRUE;
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work = CDC_ReadI2cRegister( REG_CDC0_PIN_CTL2_ADDR );
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if ((work & CDC0_PIN_CTL2_PMOFF_MASK) == CDC0_PIN_CTL2_PMOFF_E)
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*enable_pmoff = TRUE;
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}
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/*---------------------------------------------------------------------------*
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Name: CDCi_PowerUpPLL
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Description: power up Internal PLL of the CODEC
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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static void CDCi_PowerUpPLL( void )
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{
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// page 0, reg 5 <20><> P=2,R=1,PLL on <20>ݒ<EFBFBD>
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CDC_ChangePage( 0 );
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CDC_WriteI2cRegister( REG_CDC0_PLL_P_R_ADDR,
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CDC0_PLL_P_R_PWR |
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(2 << CDC0_PLL_P_R_DIV_SHIFT) |
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(1 << CDC0_PLL_P_R_MUL_SHIFT) );
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}
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/*---------------------------------------------------------------------------*
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Name: CDCi_PowerDownPLL
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Description: power down Internal PLL of the CODEC
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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static void CDCi_PowerDownPLL( void )
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{
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// page 0, reg 5 <20><> PLL off <20>ݒ<EFBFBD>
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CDC_ChangePage( 0 );
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CDC_WriteI2cRegister( REG_CDC0_PLL_P_R_ADDR, 0 );
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_SetParamPLL
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Description: setup PLL parameter of the CODEC
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Arguments: is48kHz : set 48 kHz if TRUE. set 32kHz if FALSE.
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Returns: None
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*---------------------------------------------------------------------------*/
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// <20>p<EFBFBD><70><EFBFBD><EFBFBD><EFBFBD>[<5B>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>ύX<CF8D><58><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882><EFBFBD><EFBFBD>v<EFBFBD>m<EFBFBD>F
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// Codec Off<66><66><EFBFBD>ԂŕύX<CF8D><58><EFBFBD>ׂ<EFBFBD><D782>H
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void CDC_SetParamPLL( BOOL is48kHz )
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{
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if (is48kHz)
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{
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CDC_WriteI2cRegister( REG_CDC0_PLL_J_ADDR, 15 );
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CDC_WriteI2cRegister( REG_CDC0_NDAC_DIV_ADDR, CDC0_NDAC_DIV_PWR | 5 );
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CDC_WriteI2cRegister( REG_CDC0_NADC_DIV_ADDR, CDC0_NADC_DIV_PWR | 5 );
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}
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else
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{
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CDC_WriteI2cRegister( REG_CDC0_PLL_J_ADDR, 21 );
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CDC_WriteI2cRegister( REG_CDC0_NDAC_DIV_ADDR, CDC0_NDAC_DIV_PWR | 7 );
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CDC_WriteI2cRegister( REG_CDC0_NADC_DIV_ADDR, CDC0_NADC_DIV_PWR | 7 );
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}
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_PowerUpDAC
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Description: power up (both Left,Right channel of the) DAC of the CODEC
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_PowerUpDAC( void )
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{
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// page 0, reg 63 <20><> Left/Right DAC On, datapath is straght-forward setting.
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CDC_ChangePage( 0 );
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CDC_WriteI2cRegister( REG_CDC0_DIG_PATH_ADDR,
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CDC0_DIG_PATH_CH_PWR_L | (1 << CDC0_DIG_PATH_L_SHIFT) |
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CDC0_DIG_PATH_CH_PWR_R | (1 << CDC0_DIG_PATH_R_SHIFT) );
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// PLL <20><> ADC, DAC <20><><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>炵<EFBFBD><E782B5><EFBFBD>̂ŁA<C581><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL <20><><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD><CC82>߂̃E<CC83>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>K<EFBFBD>v
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if ((!isADCOn) && (!isDACOn))
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OS_Sleep( CDC_PLL_STABLE_WAIT_TIME );
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isDACOn = TRUE;
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_PowerDownDAC
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Description: power down (both Left,Right channel of the) DAC of the CODEC
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Arguments: None
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_PowerDownDAC( void )
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{
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// page 0, reg 63 <20><> Left/Right DAC Off
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CDC_ChangePage( 0 );
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CDC_WriteI2cRegister( REG_CDC0_DIG_PATH_ADDR, 0 );
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isDACOn = FALSE;
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}
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/*---------------------------------------------------------------------------*
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Name: CDC_SetupDAC
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Description: setup DAC depop value of the CODEC
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Arguments: int hp_pwon_tm : Headphone Power-on time
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int hp_rmpup_tm : Headphone Ramp-up step time
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int sphp_rmpdn_tm : Speaker/Headphonw Ramp-down step time
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Returns: None
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*---------------------------------------------------------------------------*/
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void CDC_SetupDAC( int hp_pwon_tm, int hp_rmpup_tm, int sphp_rmpdn_tm )
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{
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// page 1, reg 33--35
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CDC_ChangePage( 1 );
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CDC_WriteI2cRegister( REG_CDC1_HP_DRV_TM_ADDR, (u8)(hp_pwon_tm | hp_rmpup_tm) );
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CDC_WriteI2cRegister( REG_CDC1_HPSP_RAMPDWN_ADDR, (u8)sphp_rmpdn_tm );
|
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CDC_WriteI2cRegister( REG_CDC1_DAC_OUTPUT_ADDR, CDC1_DAC_OUTPUT_E_R | CDC1_DAC_OUTPUT_E_L );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_EnableHeadphoneDriver
|
||
|
||
Description: enable Headphone Driver (HP Driver On)
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_EnableHeadphoneDriver( void )
|
||
{
|
||
// page 1, reg 36--41
|
||
CDC_ChangePage( 1 );
|
||
|
||
// Mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
|
||
// Power Up Headphone Driver, with short-circuit protection
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_DRV_ADDR, CDC1_HP_DRV_PWR_L | CDC1_HP_DRV_PWR_R |
|
||
CDC1_HP_CMN_MODE_VOL_1_65V | CDC1_HP_DRV_SHTC_PROTECT_E );
|
||
|
||
// Un-mute Headphone
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_DRV_L_ADDR, CDC1_HP_DRV_PDN_TRISTATE | CDC1_HP_DRV_MUTEN );
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_DRV_R_ADDR, CDC1_HP_DRV_PDN_TRISTATE | CDC1_HP_DRV_MUTEN );
|
||
|
||
// Un-mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MAX );
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MAX );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_DisableHeadphoneDriver
|
||
|
||
Description: disable Headphone Driver (HP Driver Off)
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_DisableHeadphoneDriver( void )
|
||
{
|
||
// page 1, reg 36--37,31
|
||
CDC_ChangePage( 1 );
|
||
|
||
// Mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
|
||
// Power Down Headphone Driver, with short-circuit protection
|
||
CDC_WriteI2cRegister( REG_CDC1_HP_DRV_ADDR, CDC1_HP_DRV_SHTC_PROTECT_E );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_EnableSpeakerDriver
|
||
|
||
Description: enable Speaker Driver (SP Driver On)
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_EnableSpeakerDriver( void )
|
||
{
|
||
// page 1, reg 38-39,32,42-43
|
||
CDC_ChangePage( 1 );
|
||
|
||
// Mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
|
||
// Power Up Speaker Driver, with short-circuit protection
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_DRV_ADDR, CDC1_SP_DRV_PWR_L | CDC1_SP_DRV_PWR_R |
|
||
CDC1_SP_DRV_SHTC_PROTECT_E );
|
||
|
||
// Un-mute Speaker
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_DRV_L_ADDR, CDC1_SP_DRV_MUTEN | CDC1_SP_DRV_GAIN_0DB );
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_DRV_R_ADDR, CDC1_SP_DRV_MUTEN | CDC1_SP_DRV_GAIN_0DB );
|
||
|
||
// Un-mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MAX );
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MAX );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_DisableSpeakerDriver
|
||
|
||
Description: disable Speaker Driver (SP Driver Off)
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_DisableSpeakerDriver( void )
|
||
{
|
||
// page 1, reg 38-39,32
|
||
CDC_ChangePage( 1 );
|
||
|
||
// Mute Analog Volume
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_L_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_ANGVOL_R_ADDR, CDC1_ANGVOL_E | CDC1_ANGVOL_GAIN_MUTE );
|
||
|
||
// Power Down Speaker Driver, with short-circuit protection
|
||
CDC_WriteI2cRegister( REG_CDC1_SP_DRV_ADDR, CDC1_SP_DRV_SHTC_PROTECT_E );
|
||
}
|
||
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_UnmuteDAC
|
||
|
||
Description: Un-mute DAC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_UnmuteDAC( void )
|
||
{
|
||
// page 0, reg 64 <20><> Un-mute
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_DIG_VOL_M_ADDR, 0 );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_MuteDAC
|
||
|
||
Description: Mute DAC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_MuteDAC( void )
|
||
{
|
||
// page 0, reg 64 <20><> Mute
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_DIG_VOL_M_ADDR, CDC0_DIG_VOL_M_MUTE_L | CDC0_DIG_VOL_M_MUTE_R );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_PowerUpADC
|
||
|
||
Description: power up ADC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_PowerUpADC( void )
|
||
{
|
||
// page 0, reg 81 <20><> Power Up
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_ADC_PWR_STEP_ADDR, CDC0_ADC_PWR_STEP_PWRUP );
|
||
|
||
// PLL <20><> ADC, DAC <20><><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƃ<EFBFBD><C682>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>炵<EFBFBD><E782B5><EFBFBD>̂ŁA<C581><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL <20><><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD><CC82>߂̃E<CC83>F<EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>K<EFBFBD>v
|
||
if ((!isADCOn) && (!isDACOn))
|
||
OS_Sleep( CDC_PLL_STABLE_WAIT_TIME );
|
||
|
||
isADCOn = TRUE;
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_PowerDownADC
|
||
|
||
Description: power down ADC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_PowerDownADC( void )
|
||
{
|
||
// page 0, reg 81 <20><> Power Down
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_ADC_PWR_STEP_ADDR, CDC0_ADC_PWR_STEP_PWRDN );
|
||
|
||
isADCOn = FALSE;
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_UnmuteADC
|
||
|
||
Description: Un-mute ADC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_UnmuteADC( void )
|
||
{
|
||
// page 0, reg 82 <20><> Un-mute
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_ADC_MUTE_ADDR, CDC0_ADC_MUTE_D );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_MuteADC
|
||
|
||
Description: Mute ADC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_MuteADC( void )
|
||
{
|
||
// page 0, reg 82 <20><> Mute
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_ADC_MUTE_ADDR, CDC0_ADC_MUTE_E );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_EnableAGC
|
||
|
||
Description: Enable AGC of the CODEC
|
||
|
||
Arguments: int target_gain : AGC Target Gain
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_EnableAGC( int target_gain )
|
||
{
|
||
// page 0, reg 86 <20><> Enable
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_AGC_CTL1_ADDR, (u8)(CDC0_AGC_CTL1_E | target_gain) );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_DisableAGC
|
||
|
||
Description: Disable AGC of the CODEC
|
||
|
||
Arguments: None
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_DisableAGC( void )
|
||
{
|
||
// page 0, reg 86 <20><> Disable
|
||
CDC_ChangePage( 0 );
|
||
CDC_WriteI2cRegister( REG_CDC0_AGC_CTL1_ADDR, CDC0_AGC_CTL1_D );
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_Init1stOrderFilter
|
||
|
||
Description: initialize 1st order filter coeffient
|
||
|
||
Arguments: u8 *coef : 1st order coefficient (6 bytes)
|
||
int filter_target : target filter to be setup
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_Init1stOrderFilter( u8 *coef, int filter_target )
|
||
{
|
||
if (filter_target & CDC_FILTER_1ST_IIR_ADC)
|
||
{
|
||
CDC_ChangePage( 4 );
|
||
CDC_WriteI2cRegisters( REG_CDC4_ADC_C4_MSB_ADDR, coef, 6 );
|
||
}
|
||
if (filter_target & CDC_FILTER_1ST_IIR_LDAC)
|
||
{
|
||
CDC_ChangePage( 9 );
|
||
CDC_WriteI2cRegisters( REG_CDC9_DAC_C65_MSB_ADDR, coef, 6 );
|
||
}
|
||
if (filter_target & CDC_FILTER_1ST_IIR_RDAC)
|
||
{
|
||
CDC_ChangePage( 9 );
|
||
CDC_WriteI2cRegisters( REG_CDC9_DAC_C68_MSB_ADDR, coef, 6 );
|
||
}
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*
|
||
Name: CDC_SetScanModeTimerClockDivider
|
||
|
||
Description: <20>X<EFBFBD>L<EFBFBD><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>[<5B>h<EFBFBD>̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD>f<EFBFBD>B<EFBFBD>o<EFBFBD>C<EFBFBD>_<EFBFBD>[<5B><><EFBFBD>ݒ肵<DD92>܂<EFBFBD><DC82>B
|
||
ARM7<4D><37><EFBFBD>狟<EFBFBD><E78B9F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCLK<4C>i12.19MHz<EFBFBD>j<EFBFBD>̓f<EFBFBD>B<EFBFBD>o<EFBFBD>C<EFBFBD>_<EFBFBD>[<5B>̒l<CC92><6C>
|
||
<EFBFBD>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40><><EFBFBD><EFBFBD><EFBFBD>ĕ<EFBFBD><C495><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
|
||
<EFBFBD>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40><><EFBFBD>ʂƂ<CA82><C682>āA<C481>f<EFBFBD>B<EFBFBD>o<EFBFBD>C<EFBFBD>_<EFBFBD>[<5B>̒l<CC92>ɔ<EFBFBD><C994>Ⴕ<EFBFBD><E182B5>
|
||
<EFBFBD>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40>E<EFBFBD>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F><EFBFBD>^<5E>C<EFBFBD>}<7D>[
|
||
<EFBFBD>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40>E<EFBFBD>f<EFBFBD>o<EFBFBD>E<EFBFBD><45><EFBFBD>X<EFBFBD>^<5E>C<EFBFBD>}<7D>[
|
||
<EFBFBD>@<40>@<40>@<40>@<40>@<40>@<40>@<40>@<40>̎<EFBFBD><CC8E>Ԃ<EFBFBD><D482>X<EFBFBD>P<EFBFBD>[<5B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
|
||
<20><><EFBFBD>{<7B>I<EFBFBD>ɂ<EFBFBD> 24 <20>Œ<EFBFBD><C592>Ƃ<EFBFBD><C682>܂<EFBFBD><DC82>B
|
||
|
||
MCLK = 12.19MHz
|
||
divider = 24
|
||
interval time = 16ms 2ms 4ms 6ms 8ms 10ms 12ms 14ms
|
||
de-bounce time = 0us 16us 32us 64us 128us 256us 512us 1024us
|
||
|
||
Arguments: value :
|
||
|
||
Returns: None
|
||
*---------------------------------------------------------------------------*/
|
||
void CDC_SetScanModeTimerClockDivider( u8 value )
|
||
{
|
||
SDK_ASSERT( value < 128);
|
||
CDC_ChangePage( 3 );
|
||
CDC_WriteI2cRegister( REG_CDC3_TP_DELAY_CLK_ADDR, value );
|
||
}
|
||
|