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fix wram_abc.h.

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/twl_wrapsdk/trunk@19 4ee2a332-4b2b-5046-8439-1ba90f034370
This commit is contained in:
nakasima 2007-04-12 05:39:53 +00:00
parent 530f09338d
commit a692b4669c
1 changed files with 44 additions and 9 deletions
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45
include/twl/mi/wram_abc.h
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@ -38,7 +38,7 @@ typedef enum
{ {
MI_WRAM_B_ARM9 = 0 << REG_MI_WRAM_B0_MST_SHIFT, MI_WRAM_B_ARM9 = 0 << REG_MI_WRAM_B0_MST_SHIFT,
MI_WRAM_B_ARM7 = 1 << REG_MI_WRAM_B0_MST_SHIFT, MI_WRAM_B_ARM7 = 1 << REG_MI_WRAM_B0_MST_SHIFT,
MI_WRAM_B_DSP = 2 << REG_MI_WRAM_B0_MST_SHIFT MI_WRAM_B_DSP_I = 2 << REG_MI_WRAM_B0_MST_SHIFT
} }
MIWramB; MIWramB;
@ -46,7 +46,7 @@ typedef enum
{ {
MI_WRAM_C_ARM9 = 0 << REG_MI_WRAM_C0_MST_SHIFT, MI_WRAM_C_ARM9 = 0 << REG_MI_WRAM_C0_MST_SHIFT,
MI_WRAM_C_ARM7 = 1 << REG_MI_WRAM_C0_MST_SHIFT, MI_WRAM_C_ARM7 = 1 << REG_MI_WRAM_C0_MST_SHIFT,
MI_WRAM_C_DSP = 2 << REG_MI_WRAM_C0_MST_SHIFT MI_WRAM_C_DSP_D = 2 << REG_MI_WRAM_C0_MST_SHIFT
} }
MIWramC; MIWramC;
@ -89,7 +89,14 @@ typedef enum
{ {
MI_WRAM_A_IMG_64KB = 0 << REG_MI_WRAM_A_MAP_IMG_SHIFT, MI_WRAM_A_IMG_64KB = 0 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
MI_WRAM_A_IMG_128KB = 1 << REG_MI_WRAM_A_MAP_IMG_SHIFT, MI_WRAM_A_IMG_128KB = 1 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
MI_WRAM_A_IMG_256KB = 2 << REG_MI_WRAM_A_MAP_IMG_SHIFT MI_WRAM_A_IMG_256KB = 2 << REG_MI_WRAM_A_MAP_IMG_SHIFT,
MI_WRAM_A_IMG_MIN = MI_WRAM_A_IMG_64KB,
#ifdef BROM_PLATFORM_BB
MI_WRAM_A_IMG_MAX = MI_WRAM_A_IMG_128KB
#else // BROM_PLATFORM_TS
MI_WRAM_A_IMG_MAX = MI_WRAM_A_IMG_256KB
#endif // BROM_PLATFORM_TS
} }
MIImageWramA; MIImageWramA;
@ -98,7 +105,14 @@ typedef enum
MI_WRAM_B_IMG_32KB = 0 << REG_MI_WRAM_B_MAP_IMG_SHIFT, MI_WRAM_B_IMG_32KB = 0 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
MI_WRAM_B_IMG_64KB = 1 << REG_MI_WRAM_B_MAP_IMG_SHIFT, MI_WRAM_B_IMG_64KB = 1 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
MI_WRAM_B_IMG_128KB = 2 << REG_MI_WRAM_B_MAP_IMG_SHIFT, MI_WRAM_B_IMG_128KB = 2 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
MI_WRAM_B_IMG_256KB = 3 << REG_MI_WRAM_B_MAP_IMG_SHIFT MI_WRAM_B_IMG_256KB = 3 << REG_MI_WRAM_B_MAP_IMG_SHIFT,
MI_WRAM_B_IMG_MIN = MI_WRAM_B_IMG_32KB,
#ifdef BROM_PLATFORM_BB
MI_WRAM_B_IMG_MAX = MI_WRAM_B_IMG_128KB
#else // BROM_PLATFORM_TS
MI_WRAM_B_IMG_MAX = MI_WRAM_B_IMG_256KB
#endif // BROM_PLATFORM_TS
} }
MIImageWramB; MIImageWramB;
@ -107,7 +121,14 @@ typedef enum
MI_WRAM_C_IMG_32KB = 0 << REG_MI_WRAM_C_MAP_IMG_SHIFT, MI_WRAM_C_IMG_32KB = 0 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
MI_WRAM_C_IMG_64KB = 1 << REG_MI_WRAM_C_MAP_IMG_SHIFT, MI_WRAM_C_IMG_64KB = 1 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
MI_WRAM_C_IMG_128KB = 2 << REG_MI_WRAM_C_MAP_IMG_SHIFT, MI_WRAM_C_IMG_128KB = 2 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
MI_WRAM_C_IMG_256KB = 3 << REG_MI_WRAM_C_MAP_IMG_SHIFT MI_WRAM_C_IMG_256KB = 3 << REG_MI_WRAM_C_MAP_IMG_SHIFT,
MI_WRAM_C_IMG_MIN = MI_WRAM_C_IMG_32KB,
#ifdef BROM_PLATFORM_BB
MI_WRAM_C_IMG_MAX = MI_WRAM_C_IMG_128KB
#else // BROM_PLATFORM_TS
MI_WRAM_C_IMG_MAX = MI_WRAM_C_IMG_256KB
#endif // BROM_PLATFORM_TS
} }
MIImageWramC; MIImageWramC;
@ -116,6 +137,20 @@ MIImageWramC;
#define MI_WRAM_B_BLOCK_SIZE 0x00008000 // 32KB #define MI_WRAM_B_BLOCK_SIZE 0x00008000 // 32KB
#define MI_WRAM_C_BLOCK_SIZE 0x00008000 // 32KB #define MI_WRAM_C_BLOCK_SIZE 0x00008000 // 32KB
#ifdef BROM_PLATFORM_BB
#define MI_WRAM_A_BLOCK_NUM 2
#define MI_WRAM_B_BLOCK_NUM 4
#define MI_WRAM_C_BLOCK_NUM 4
#else // BROM_PLATFORM_TS
#define MI_WRAM_A_BLOCK_NUM 4
#define MI_WRAM_B_BLOCK_NUM 8
#define MI_WRAM_C_BLOCK_NUM 8
#endif // BROM_PLATFORM_TS
#define MI_WRAM_A_BLOCK_SIZE_MAX (MI_WRAM_A_BLOCK_SIZE * MI_WRAM_A_BLOCK_NUM)
#define MI_WRAM_B_BLOCK_SIZE_MAX (MI_WRAM_B_BLOCK_SIZE * MI_WRAM_B_BLOCK_NUM)
#define MI_WRAM_C_BLOCK_SIZE_MAX (MI_WRAM_C_BLOCK_SIZE * MI_WRAM_C_BLOCK_NUM)
#ifdef __cplusplus #ifdef __cplusplus
} /* extern "C" */ } /* extern "C" */