mirror of
https://github.com/rvtr/twl_mcu.git
synced 2025-06-18 14:45:41 -04:00
141 lines
5.8 KiB
C
141 lines
5.8 KiB
C
#ifndef _MDSYSTEM_
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#define _MDSYSTEM_
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/*
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*******************************************************************************
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** Register bit define
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*******************************************************************************
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*/
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/*
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Clock Operation Mode Select Register (OSCCTL)
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*/
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/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */
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#define CG_HISYSTEM_EXTCLK 0x80 /* external clock bit */
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#define CG_HISYSTEM_OSCSEL 0x40 /* clock/port bit */
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#define CG_HISYSTEM_PIN 0xc0
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#define CG_HISYSTEM_PORT 0x00 /* X1, X2 as I/O port */
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#define CG_HISYSTEM_OSC 0x40 /* X1, X2 as crystal/ceramic resonator connection */
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#define CG_HISYSTEM_PORT1 0x80 /* X1, X2 as I/O port */
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#define CG_HISYSTEM_EXT 0xc0 /* X1 as External clock input, X2 as I/O port */
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/* Subsystem clock pin operation mode (EXCLKS, OSCSELS) */
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/** Note: valid when PCC.XTSTART = 0 **/
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#define CG_SUBCLOCK_OSCSELS 0x10 /* sub clock/port bit */
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#define CG_SUBCLOCK 0x30
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#define CG_SUBCLOCK_PORT 0x00 /* XT1, XT2 as I/O port */
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#define CG_SUBCLOCK_OSC 0x10 /* XT1, XT2 as crystal resonator connection */
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#define CG_SUBCLOCK_PORT1 0x20 /* XT1, XT2 as I/O port mode */
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#define CG_SUBCLOCK_EXT 0x30 /* XT1 as External clock input, X2 as I/O port */
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/* Operating frequency control (AMPH) */
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#define CG_OPERATING_FREQ 0x01
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#define CG_OPERATING_UNDER10M 0x00 /* 1 MHz <=fxh <= 10 MHz */
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#define CG_OPERATING_OVER10M 0x01 /* 10 MHz < fxh <= 20 MHz */
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/*
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Processor Clock Control Register (PCC)
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*/
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/* Subsystem clock pin operation mode (XTSTART) */
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#define CG_XTSTART 0x40
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#define CG_XTSTART_OTHER 0x00 /* sub clock pin mode set by OSCCTL */
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#define CG_XTSTART_OSC 0x40 /* XT1, XT2 as crystal resonator connection */
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/* System clock status *read only (CLS) */
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#define CG_CPUCLOCK_STATUS 0x20
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#define CG_CPUCLOCK_MAINSTATUS 0x00 /* main system clock status */
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#define CG_CPUCLOCK_SUBSTATUS 0x20 /* sub system clock status */
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/* CPU clock (fcpu) selection source (CSS) */
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#define CG_CPUCLOCK_SOURCE 0x10
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#define CG_CPUCLOCK_MAIN 0x00 /* main system clock */
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#define CG_CPUCLOCK_SUB 0x10 /* sub system clock */
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/* CPU clock (fcpu) selection (PCC0, PCC1, PCC2) */
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/** Note: valid when PCC.CSS = 0 **/
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#define CG_CPUCLOCK 0x07
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#define CG_CPUCLOCK_FXP 0x00 /* fcpu = fxp */
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#define CG_CPUCLOCK_FXP2 0x01 /* fcpu = fxp/2 (default) */
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#define CG_CPUCLOCK_FXP4 0x02 /* fcpu = fxp/4 */
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#define CG_CPUCLOCK_FXP8 0x03 /* fcpu = fxp/8 */
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#define CG_CPUCLOCK_FXP16 0x04 /* fcpu = fxp/16 */
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/*
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Internal Oscillation Mode Register (RCM)
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*/
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/* Status of internal high-speed oscillator *read only (RSTS) */
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#define CG_HIGHINTERNAL_STATUS 0x80
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#define CG_HIGHINTERNAL_WAIT 0x00 /* wait for ready */
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#define CG_HIGHINTERNAL_READY 0x80 /* ready for operation */
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/* Internal low-speed oscillator oscillating/stopped (LSRSTOP) */
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#define CG_LOWINTERNAL 0x02
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#define CG_LOWINTERNAL_RUN 0x00 /* internal low-speed oscillator oscillating */
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#define CG_LOWINTERNAL_STOP 0x02 /* internal low-speed oscillator stopped */
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/* Internal high-speed oscillator oscillating/stopped (RSTOP) */
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#define CG_HIGHINTERNAL 0x01
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#define CG_HIGHINTERNAL_RUN 0x00 /* internal high-speed oscillator oscillating */
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#define CG_HIGHINTERNAL_STOP 0x01 /* internal high-speed oscillator stopped */
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/*
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Main OSC control register (MOC)
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/* Control of high-speed system clock operation (MSTOP) */
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#define CG_HISYSTEM 0x80
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#define CG_HISYSTEM_RUN 0x00 /* X1 oscillator/external clock enable */
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#define CG_HISYSTEM_STOP 0x80 /* X1 oscillator/external clock disable */
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/*
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Main Clock Mode Register (MCM)
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*/
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/* Selection of clock supplied to main system clock and peripheral hardware (XSEL, MCM0) */
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#define CG_MAINPERI_CLOCK 0x05
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#define CG_MAINPERI_INTER 0x00 /* fxp = frh,fprs = frh */
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#define CG_MAINPERI_INTER1 0x01 /* fxp = frh,fprs = frh */
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#define CG_MAINPERI_INTER_SYS 0x04 /* fxp = frh,fprs = fxh */
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#define CG_MAINPERI_SYS 0x05 /* fxp = fxh,fprs = fxh */
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/* Main system clock status *read only (MCS) */
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#define CG_MAINSYSTEM_STATUS 0x02
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#define CG_MAINSYSTEM_INTER 0x00 /* Operates with internal high-speed oscillation clock */
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#define CG_MAINSYSTEM_SYS 0x02 /* Operates with high-speed system clock */
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/*
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Oscillation Stabilization Time Counter Status Register (OSTC)
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*/
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/* Oscillation stabilization time status ( MOST11-16) */
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#define CG_OSCSTAB_STATUS 0x1f
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#define CG_OSCSTAB_STATUS11 0x10 /* 2^11/fx */
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#define CG_OSCSTAB_STATUS13 0x18 /* 2^13/fx */
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#define CG_OSCSTAB_STATUS14 0x1c /* 2^14/fx */
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#define CG_OSCSTAB_STATUS15 0x1e /* 2^15/fx */
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#define CG_OSCSTAB_STATUS16 0x1f /* 2^16/fx */
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/*
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Oscillation Stabilization Time Select Register (OSTS)
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*/
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/* Oscillation stabilization time selection (OSTS2-0) */
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#define CG_OSCSTAB_SELECT 0x07
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#define CG_OSCSTAB_SELECT11 0x01 /* 2^11/fx */
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#define CG_OSCSTAB_SELECT13 0x02 /* 2^13/fx */
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#define CG_OSCSTAB_SELECT14 0x03 /* 2^14/fx */
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#define CG_OSCSTAB_SELECT15 0x04 /* 2^15/fx */
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#define CG_OSCSTAB_SELECT16 0x05 /* 2^16/fx */
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/*
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*******************************************************************************
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** Macro define
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*******************************************************************************
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*/
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#define CG_FRHWAITTIME 40
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enum ClockMode { HIOCLK, SYSX1CLK, SYSEXTCLK, HIOSYSCLK };
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enum CPUClock { SYSTEMCLOCK, SYSONEHALF, SYSONEFOURTH, SYSONEEIGHTH, SYSONESIXTEENTH };
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enum PSLevel { PSSTOP, PSHALT };
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enum StabTime { STLEVEL0, STLEVEL1, STLEVEL2, STLEVEL3, STLEVEL4 };
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/*
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*******************************************************************************
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** Function define
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*******************************************************************************
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*/
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void Clock_Init( void );
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void CG_ReadResetSource( void );
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/* Start user code for definition. Do not edit comment generated here */
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void hdwinit( void );
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/* End user code for definition. Do not edit comment generated here */
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#endif
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