mirror of
https://github.com/rvtr/twl_mcu.git
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84 lines
3.0 KiB
PHP
84 lines
3.0 KiB
PHP
;/*
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;******************************************************************************
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;*
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;* This device driver was created by Applilet2 for the Applilet2 for 78K0/Kx2
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;* 8-Bit Single-Chip Microcontrollers
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;*
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;* Copyright(C) NEC Electronics Corporation 2002 - 2007
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;* All rights reserved by NEC Electronics Corporation.
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;*
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;* This program should be used on your own responsibility.
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;* NEC Electronics Corporation assumes no responsibility for any losses
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;* incurred by customers or third parties arising from the use of this file.
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;*
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;* Filename : option.inc
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;* Abstract : This file implements OPTION-BYTES/SECURITY-ID setting.
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;* APIlib : Applilet2 for 78K0/Kx2 V2.10 [6 Mar. 2007]
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;*
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;* Device : uPD78F0500_30
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;*
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;* Compiler : CC78K0
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;*
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;* Creation date: 2007/07/11
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;*
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;******************************************************************************
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;*/
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;/*
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;******************************************************************************
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;* Macro define
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;******************************************************************************
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;*/
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;/*
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;******************************************************************************
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;* Register bit define
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;******************************************************************************
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;*/
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;*** OPTION-BYTES bit define ***
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; Option at 80H
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; Watchdog timer window open period (WINDOW1-0)
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WDT_WINDOW_OPEN EQU 60H
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WDT_WINDOW_OPEN_PERIOD0 EQU 00H ;25%
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WDT_WINDOW_OPEN_PERIOD1 EQU 20H ;50%
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WDT_WINDOW_OPEN_PERIOD2 EQU 40H ;75%
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WDT_WINDOW_OPEN_PERIOD3 EQU 60H ;100%
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; Watchdog timer counter control (WDTON)
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WDT_OPERATION EQU 10H
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WDT_OPERATION_ENABLE EQU 10H ;Counter operation enabled
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WDT_OPERATION_DISABLE EQU 00H ;Counter operation disabled
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; Watchdog timer overflow time (WDCS2-0)
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WDT_OVERFLOW EQU 0EH
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WDT_OVERFLOW_TIME0 EQU 00H ;2^10/fRL (3.88 ms)
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WDT_OVERFLOW_TIME1 EQU 02H ;2^11/fRL (7.76 ms)
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WDT_OVERFLOW_TIME2 EQU 04H ;2^12/fRL (15.52 ms)
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WDT_OVERFLOW_TIME3 EQU 06H ;2^13/fRL (31.03 ms)
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WDT_OVERFLOW_TIME4 EQU 08H ;2^14/fRL (62.06 ms)
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WDT_OVERFLOW_TIME5 EQU 0AH ;2^15/fRL (124.12 ms)
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WDT_OVERFLOW_TIME6 EQU 0CH ;2^16/fRL (248.24 ms)
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WDT_OVERFLOW_TIME7 EQU 0EH ;2^17/fRL (496.48 ms)
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; Internal low-speed oscillator operation (RINGOSC)
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CG_LOWINTERNAL EQU 01H
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CG_LOWINTERNAL_CANSTOP EQU 00H ;can be stopped by software
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CG_LOWINTERNAL_CANNOT EQU 01H ;cannot be stopped
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; Option at 81H
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; POC mode selection (POCMODE)
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CG_POCMODE EQU 01H
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CG_POCMODE_1DOT59V EQU 00H ;1.59 V POC mode (default)
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CG_POCMODE_2DOT7V EQU 01H ;2.7 V/1.59 V POC mode
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; Option at 84H
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; On-chip debug operation control (OCDEN1-0)
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CG_FLASH EQU 02H ;when security ID code authenticaiton fails
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CG_FLASH_NOTERASE EQU 02H ;data is not deleted
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CG_FLASH_ERASE EQU 01H ;data is deleted
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;*** OPTION-BYTES/SECURITY-ID define ***
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OPTION_BYTE EQU WDT_WINDOW_OPEN_PERIOD3 OR WDT_OPERATION_ENABLE OR WDT_OVERFLOW_TIME7 OR CG_LOWINTERNAL_CANSTOP
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POC81 EQU 00H
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POC82 EQU 00H
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POC83 EQU 00H
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;CG_ONCHIP EQU CG_FLASH_NOTERASE
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CG_ONCHIP EQU 00
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