#ifndef _MDSERIAL_ #define _MDSERIAL_ /* IIC operation enable (IICE0) */ #define IIC0_OPERATION 0x80 #define IIC0_OPERATION_DISABLE 0x00 /* stop operation */ #define IIC0_OPERATION_ENABLE 0x80 /* enable operation */ /* Exit from communications (LREL0) */ #define IIC0_COMMUNICATION 0x40 #define IIC0_COMMUNICATION_NORMAL 0x00 /* normal operation */ #define IIC0_COMMUNICATION_EXIT 0x40 /* exit from current communication */ /* Wait cancellation (WREL0) */ #define IIC0_WAITCANCEL 0x20 #define IIC0_WAIT_NOTCANCEL 0x00 /* do not cancel wait */ #define IIC0_WAIT_CANCEL 0x20 /* cancel wait */ /* Generation of interrupt when stop condition (SPIE0) */ #define IIC0_STOPINT 0x10 #define IIC0_STOPINT_DISABLE 0x00 /* disable */ #define IIC0_STOPINT_ENABLE 0x10 /* enable */ /* Wait and interrupt generation (WTIM0) */ #define IIC0_WAITINT 0x08 #define IIC0_WAITINT_CLK8FALLING 0x00 /* generate at the eighth clocks falling edge */ #define IIC0_WAITINT_CLK9FALLING 0x08 /* generated at the ninth clocks falling edge */ /* Acknowledgement control (ACKE0) */ #define IIC0_ACK 0x04 #define IIC0_ACK_DISABLE 0x00 /* enable acknowledgement */ #define IIC0_ACK_ENABLE 0x04 /* disable acknowledgement */ /* Start condition trigger (STT0) */ #define IIC0_STARTCONDITION 0x02 #define IIC0_START_NOTGENERATE 0x00 /* do not generate start condition */ #define IIC0_START_GENERATE 0x02 /* generate start condition */ /* Stop condition trigger (SPT0) */ #define IIC0_STOPCONDITION 0x01 #define IIC0_STOP_NOTGENERATE 0x00 /* do not generate stop condition */ #define IIC0_STOP_GENERATE 0x01 /* generate stop condition */ /* IIC Status Register 0 (IICS0) */ /* Master device status (MSTS0) */ #define IIC0_MASTERSTATUS 0x80 #define IIC0_STATUS_NOTMASTER 0x00 /* slave device status or communication standby status */ #define IIC0_STATUS_MASTER 0x80 /* master device communication status */ /* Detection of arbitration loss (ALD0) */ #define IIC0_ARBITRATION 0x40 #define IIC0_ARBITRATION_NO 0x00 /* arbitration win or no arbitration */ #define IIC0_ARBITRATION_LOSS 0x40 /* arbitration loss */ /* Detection of extension code reception (EXC0) */ #define IIC0_EXTENSIONCODE 0x20 #define IIC0_EXTCODE_NOT 0x00 /* extension code not received */ #define IIC0_EXTCODE_RECEIVED 0x20 /* extension code received */ /* Detection of matching addresses (COI0) */ #define IIC0_ADDRESSMATCH 0x10 #define IIC0_ADDRESS_NOTMATCH 0x00 /* addresses do not match */ #define IIC0_ADDRESS_MATCH 0x10 /* addresses match */ /* Detection of transmit/receive status (TRC0) */ #define IIC0_STATUS 0x08 #define IIC0_STATUS_RECEIVE 0x00 /* receive status */ #define IIC0_STATUS_TRANSMIT 0x08 /* transmit status */ /* Detection of acknowledge signal (ACKD0) */ #define IIC0_ACKDETECTION 0x04 #define IIC0_ACK_NOTDETECTED 0x00 /* ACK signal was not detected */ #define IIC0_ACK_DETECTED 0x04 /* ACK signal was detected */ /* Detection of start condition (STD0) */ #define IIC0_STARTDETECTION 0x02 #define IIC0_START_NOTDETECTED 0x00 /* start condition not detected */ #define IIC0_START_DETECTED 0x02 /* start condition detected */ /* Detection of stop condition (SPD0) */ #define IIC0_STOPDETECTION 0x01 #define IIC0_STOP_NOTDETECTED 0x00 /* stop condition not detected */ #define IIC0_STOP_DETECTED 0x01 /* stop condition detected */ /* IIC Flag Register 0 (IICF0) */ /* STT0 clear flag (STCF) */ #define IIC0_STARTFLAG 0x80 #define IIC0_STARTFLAG_GENERATE 0x00 /* generate start condition */ #define IIC0_STARTFLAG_UNSUCCESSFUL 0x80 /* start condition generation unsuccessful */ /* IIC bus status flag (IICBSY) */ #define IIC0_BUSSTATUS 0x40 #define IIC0_BUS_RELEASE 0x00 /* bus release status */ #define IIC0_BUS_COMMUNICATION 0x40 /* bus communication status */ /* Initial start enable trigger (STCEN) */ #define IIC0_STARTWITHSTOP 0x02 #define IIC0_START_WITHSTOP 0x00 /* generation of a start condition without detecting a stop condition */ #define IIC0_START_WITHOUTSTOP 0x02 /* generation of a start condition upon detection of a stop condition */ /* Communication reservation function disable bit (IICRSV) */ #define IIC0_RESERVATION 0x01 #define IIC0_RESERVATION_ENABLE 0x00 /* enable communication reservation */ #define IIC0_RESERVATION_DISABLE 0x01 /* disable communication reservation */ /* IIC clock selection register 0 (IICCL0) */ #define IICCL0_INITIALVALUE 0x00 /* Detection of SCL0 pin level (CLD0) */ #define IIC0_SCLLEVEL 0x20 #define IIC0_SCL_LOW 0x00 /* clock line at low level */ #define IIC0_SCL_HIGH 0x20 /* clock line at high level */ /* Detection of SDA0 pin level (DAD0) */ #define IIC0_SDALEVEL 0x10 #define IIC0_SDA_LOW 0x00 /* data line at low level */ #define IIC0_SDA_HIGH 0x10 /* data line at high level */ /* Operation mode switching (SMC0) */ #define IIC0_OPERATIONMODE 0x08 #define IIC0_MODE_STANDARD 0x00 /* operates in standard mode */ #define IIC0_MODE_HIGHSPEED 0x08 /* operates in high-speed mode */ /* Digital filter operation control (DFC0) */ #define IIC0_DIGITALFILTER 0x04 #define IIC0_FILTER_OFF 0x00 /* digital filter off */ #define IIC0_FILTER_ON 0x04 /* digital filter on */ /* Operation mode switching (CL01, CL00) */ #define IIC0_CLOCKSELECTION 0x03 /* Combine of (SMC0, CL01, CL00)*/ #define IIC0_CLOCK0 0x00 #define IIC0_CLOCK1 0x01 #define IIC0_CLOCK2 0x02 #define IIC0_CLOCK3 0x03 #define IIC0_CLOCK4 0x08 #define IIC0_CLOCK5 0x09 #define IIC0_CLOCK6 0x0a #define IIC0_CLOCK7 0x0b /* IIC function expansion register 0 (IICX0) */ /* IIC clock expension (CLX0) */ #define IIC0_CLOCKEXPENSION 0x01 #define IIC0_EXPENSION0 0x00 #define IIC0_EXPENSION1 0x01 /* Operation clock (CLX0, SMC0, CL01, CL00) | IIC0_EXPENSION0 | IIC0_EXPENSION1 | ------------|-------------------|-------------------|---------------------- IIC0_CLOCK0 | fprs/2 | prohibited | selection clock(fw) | fprs/88 | | transfer clock | normal | | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK1 | fprs/2 | prohibited | selection clock(fw) | fprs/172 | | transfer clock | normal | | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK2 | fprs/2 | prohibited | selection clock(fw) | fprs/344 | | transfer clock | normal | | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK3 |prohibited/fexscl0 | prohibited | selection clock(fw) | fw/66 | | transfer clock | normal | | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK4 | fprs/2 | fprs/2 | selection clock(fw) | fprs/48 | fprs/24 | transfer clock | high speed | high speed | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK5 | fprs/2 | fprs/2 | selection clock(fw) | fprs/48 | fprs/24 | transfer clock | high speed | high speed | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK6 | fprs/4 | fprs/4 | selection clock(fw) | fprs/96 | fprs/48 | transfer clock | high speed | high speed | mode ------------|-------------------|-------------------|---------------------- IIC0_CLOCK7 |prohibited/fexscl0 | prohibited | selection clock(fw) | fw/18 | | transfer clock | high speed | | mode ------------|-------------------|-------------------|---------------------- */ #define ADDRESS_COMPLETE 0x80 #define IIC0_MASTER_FLAG_CLEAR 0x00 /****************************************************************************** * Macro define ******************************************************************************/ #define IIC0_SLAVEADDRESS 0x4A /****************************************************************************** * Function define ******************************************************************************/ void IIC0_Init( void ); void IIC0_SlaveSendStart( UCHAR* , UINT ); void IIC0_SlaveReceiveStart(); void IIC0_Stop( void ); static void IIC0_getStCond( void ); static void IIC0_Contents_Send( void ); static void IIC0_Contents_Rcv( void ); static void IIC0_parseContents( void ); #endif