mirror of
https://github.com/rvtr/ntr_bootrom.git
synced 2025-10-31 07:11:11 -04:00
425 lines
13 KiB
ArmAsm
425 lines
13 KiB
ArmAsm
;********************************************************************
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; IRISモニタプログラム スタートアップルーチン
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;********************************************************************
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AREA Init, CODE, READONLY
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INCLUDE IrisDefineArm.s
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INCLUDE IrisMemoryMapArm.s
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INCLUDE IrisCardDefineArm.s
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INCLUDE IrisMonDefineArm.s
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INCLUDE IrisMonMempryMapArm.s
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ENTRY
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;====================================================================
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; 割り込み領域
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;====================================================================
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CODE32
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start_v b start_handler
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undef_v b fiq_v
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swi_v b swi_handler
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code_abort_v b fiq_v
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data_abort_v b fiq_v
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reserve_v b fiq_v
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irq_v b irq_handler
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fiq_v b fiq_handler
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;====================================================================
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; NINTENDOロゴデータ
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;====================================================================
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ALIGN
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GLOBAL Nin_Char_Diff_Huff
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Nin_Char_Diff_Huff
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DCB 0x24,0xff,0xae,0x51,0x69,0x9a,0xa2,0x21,0x3d,0x84,0x82,0x0a,0x84,0xe4,0x09,0xad
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DCB 0x11,0x24,0x8b,0x98,0xc0,0x81,0x7f,0x21,0xa3,0x52,0xbe,0x19,0x93,0x09,0xce,0x20
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DCB 0x10,0x46,0x4a,0x4a,0xf8,0x27,0x31,0xec,0x58,0xc7,0xe8,0x33,0x82,0xe3,0xce,0xbf
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DCB 0x85,0xf4,0xdf,0x94,0xce,0x4b,0x09,0xc1,0x94,0x56,0x8a,0xc0,0x13,0x72,0xa7,0xfc
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DCB 0x9f,0x84,0x4d,0x73,0xa3,0xca,0x9a,0x61,0x58,0x97,0xa3,0x27,0xfc,0x03,0x98,0x76
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DCB 0x23,0x1d,0xc7,0x61,0x03,0x04,0xae,0x56,0xbf,0x38,0x84,0x00,0x40,0xa7,0x0e,0xfd
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DCB 0xff,0x52,0xfe,0x03,0x6f,0x95,0x30,0xf1,0x97,0xfb,0xc0,0x85,0x60,0xd6,0x80,0x25
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DCB 0xa9,0x63,0xbe,0x03,0x01,0x4e,0x38,0xe2,0xf9,0xa2,0x34,0xff,0xbb,0x3e,0x03,0x44
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DCB 0x78,0x00,0x90,0xcb,0x88,0x11,0x3a,0x94,0x65,0xc0,0x7c,0x63,0x87,0xf0,0x3c,0xaf
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DCB 0xd6,0x25,0xe4,0x8b,0x38,0x0a,0xac,0x72,0x21,0xd4,0xf8,0x07,0x56,0xcf,0x00,0x00
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ALIGN
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;====================================================================
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; サブルーチン群
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;====================================================================
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;--------------------------------------------------------------------
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; デバッガモニタへジャンプ
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;--------------------------------------------------------------------
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CODE32
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fiq_handler
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mrs sp, cpsr ; IRQ/FIQ不許可
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orr sp, sp, #PSR_IRQ_DISABLE | PSR_FIQ_DISABLE
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msr cpsr_cxsf, sp
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ldr sp, fiq_sp ; SP のｾｯﾄ
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add sp, sp, #1
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fiq_m stmfd sp!, {r12, lr} ; ﾚｼﾞｽﾀ の退避（合計4ﾜｰﾄﾞ）
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mrs lr, spsr
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mrc p15, 0, r12, c1, c0, 0 ; ｺﾌﾟﾛｾｯｻ･ﾏｽﾀ 退避
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stmfd sp!, {r12, lr}
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bic r12, r12, #C1_PROTECT_UNIT_ENABLE ; ﾌﾟﾛﾃｸｼｮﾝﾕﾆｯﾄ ﾃﾞｨｾｰﾌﾞﾙ
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mcr p15, 0, r12, c1, c0, 0
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bic r12, sp, #1 ; ﾃﾞﾊﾞｯｶﾞ処理へｼﾞｬﾝﾌﾟ
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ldr r12, [r12, #16]
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cmp r12, #0
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blxne r12
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;--------------------------------------------------------------------
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; デバッガモニタからの復帰
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;--------------------------------------------------------------------
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CODE32
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fiq_return
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ldmfd sp!, {r12, lr} ; ﾚｼﾞｽﾀ の復帰
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mcr p15, 0, r12, c1, c0, 0 ; ｺﾌﾟﾛｾｯｻ･ﾏｽﾀ 復帰
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msr spsr_sxcf, lr
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ldmfd sp!, {r12, lr}
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subs pc, lr, #4
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;--------------------------------------------------------------------
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; 初期化
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;--------------------------------------------------------------------
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EXTERN init_cp15
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EXTERN reset_cp15
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EXTERN IrisMonMain
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EXTERN intr_main
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CODE32
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start_handler
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cmp lr, #0 ; fiq_return => pc = -4 対策
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moveq lr, #4
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mov r12, #REG_BASE ; ﾓﾆﾀ/ﾕｰｻﾞ ﾁｪｯｸ
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ldrb r12, [r12, #OFFSET_REG_PAUSE]
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teq r12, #1
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mrseq r12, cpsr ; IRQ/FIQ不許可
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orreq r12, r12, #PSR_IRQ_DISABLE | PSR_FIQ_DISABLE
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msreq cpsr_cxsf,r12
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ldreq sp, fiq_sp ; SP のｾｯﾄ
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beq fiq_m ; ﾃﾞﾊﾞｯｶﾞﾓﾆﾀへｼﾞｬﾝﾌﾟ
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mov r4, #REG_BASE ; カードリセットLow信号 1us以上出力
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mov r0, #CARD_RESET_LO
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mov r1, #CARDMST_SEL_ROM | CARDMST_ENABLE
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str r0, [r4, #REG_CARDCNT - REG_BASE]
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str r1, [r4, #REG_CARD_MASTER_CNT - REG_BASE] ; データレジスタも同時にクリア
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; （実際はリードオンリーフラグへ書き込んでしまっている
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; ＜シャープさんからの指摘＞）
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restart_v mov r0, #0xc0 | PSR_SYS_MODE ; ｼｽﾃﾑﾓｰﾄﾞへ切り換え & IRQ/FIQ不許可
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msr cpsr_cxsf, r0
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mov r0, #0x8000/4 ; メインメモリLow期間 0.97ms
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bl WaitByLoop
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mainmem_change_burst ; メインメモリ バーストモード遷移
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ldr r4, =0x04000204 ; REG_EXMEMCNT
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mov r1, #MMEM_CE2_OUT
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strh r1, [r4]
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mov r0, #0x8000/4 ; メインメモリHigh期間 0.97ms
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bl WaitByLoop
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ldr r3, =MAIN_MEM_EX_END - 2
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ldr r1, =MMEMD4_BURST_MODE | MMEMD4_BURST_CONTINUOUS \
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| MMEMD4_PARTIAL_REFRESH_NONE | MMEMD4_SB1
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ldr r2, =MMEMD5_1ST_R4_W3 | MMEMD5_BURST_WRITE | MMEMD5_BURST_LINER \
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| MMEMD5_CLOCK_TRIGGER_UP | MMEMD5_SB1
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ldr r12, =MAIN_MEM | MMEMP_CLOCK_TRIGGER_UP \
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| MMEMP_BURST_MODE | MMEMP_BURST_CONTINUOUS \
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| MMEMP_1ST_R4_W3 | MMEMP_BURST_WRITE | MMEMP_BURST_LINER \
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| MMEMP_PARTIAL_REFRESH_NONE | MMEMP_SB1
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ldrh r0, [r3]
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strh r0, [r3]
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strh r0, [r3]
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strh r1, [r3]
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strh r2, [r3]
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ldrh r0, [r12]
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ldr r4, =0x04000204 ; REG_EXMEMCNT
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mov r1, #MMEM_INTF_SYNC | MMEM_CE2_OUT
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strh r1, [r4]
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bl init_cp15 ; システム制御コプロセッサ 初期化
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mov r4, #REG_BASE ; IME ﾘｾｯﾄ
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strb r4, [r4, #OFFSET_REG_IME]
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bl bankreg_init_stack_clear ; ﾊﾞﾝｸﾚｼﾞｽﾀ ﾘｾｯﾄ & ｽﾀｯｸ領域 ｸﾘｱ
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; adr r0, intr_main ; 割り込みｱﾄﾞﾚｽのｾｯﾄ
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; str r0, [sp, #0x100-4]
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ldr r0, =IrisMonMain ; Cﾙｰﾁﾝ処理
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blx r0
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main_return
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bl terminate_mon ; ﾓﾆﾀ終了処理
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ldr r12, =MAIN_MEM_EX_END ; ﾕｰｻﾞ･ｴﾝﾄﾘﾎﾟｲﾝﾄ 獲得
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IF :DEF: DISABLE_ENTRY_OF_ROM_HEADER
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ldr lr, [r12, #-(0x200 - 0x28)] ; rmhp->arm9->ramAddr
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ELSE
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ldr lr, [r12, #-(0x200 - 0x24)] ; rmhp->arm9->entryAddr
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ENDIF
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IF :DEF: DISABLE_BOOT_IPL2
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ldrh r0, [r12, #-4] ; ROMﾍｯﾀﾞ ﾁｪｯｸ
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cmp r0, #1
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0 beq %b0 ; ROMﾍｯﾀﾞ不整合時
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sub r12, r12, #0x800
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ldrh r0, [r12, #0x14] ; ﾃﾞﾊﾞｯｶﾞﾁｪｯｸ
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add r12, r12, #0x800
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cmp r0, #1 ; if (!shwp->isOnDebugger)
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mov r0, #0
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ldreq r12, [r12, #-(0x200 - 0x168)]; ﾃﾞﾊﾞｯｶﾞｴﾝﾄﾘﾎﾟｲﾝﾄ 獲得
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; cmpeq r12, #0 ; rmhp->dbgArm9RamAddr
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; cmpeq r12, #-1
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bxeq r12
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IF :DEF: BB_MON
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0 b %b0 ; ﾌﾞﾚｯﾄﾞﾎﾞｰﾄﾞ開発用
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ENDIF
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mov r0, #0
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bx lr
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ELSE
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sub r12, r12, #0x800
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ldrh r0, [r12, #0x2c] ; IPL2･CRCチェック
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cmp r0, #0 ; if (!shwp->flashCrcError)
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0 bne %b0
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ldr r12, [r12, #0x20] ; IPL2･ｴﾝﾄﾘﾎﾟｲﾝﾄ 獲得
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cmp r12, #0 ; shwp->flashArm9RamAddr
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0 beq %b0
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bx r12
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ENDIF
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;--------------------------------------------------------------------
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; ソフトリセット
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;--------------------------------------------------------------------
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CODE32
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soft_reset
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bl terminate_mon ; 終了処理
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ldr r12, =MAIN_MEM_EX_END ; ﾕｰｻﾞ･ｴﾝﾄﾘﾎﾟｲﾝﾄ 獲得
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ldr lr, [r12, #-(0x200 - 0x24)]
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mov r12, #0
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bx lr
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;--------------------------------------------------------------------
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; モニタプログラム終了処理
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;--------------------------------------------------------------------
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CODE32
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terminate_mon
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mov r12, lr
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mov r0, #PSR_SYS_MODE ; IRQ/FIQ許可
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msr cpsr_cxsf, r0
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ldr r0, =C1_DTCM_ENABLE | C1_EXCEPT_VEC_UPPER \
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| C1_SB1_BITSET
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bl reset_cp15 ; プロテクションユニットディセーブル
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bl bankreg_init_stack_clear ; ﾊﾞﾝｸﾚｼﾞｽﾀ ﾘｾｯﾄ & ｽﾀｯｸ領域 ｸﾘｱ
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ldmea r4, {r0-r11} ; 汎用ﾚｼﾞｽﾀ ｸﾘｱ
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bx r12
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;--------------------------------------------------------------------
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; バンクレジスタ リセット ＆ スタック領域 クリア
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;--------------------------------------------------------------------
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CODE32
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bankreg_init_stack_clear
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mov r0, #0xc0 | PSR_SVC_MODE ; SVCﾓｰﾄﾞへ切り換え & IRQ/FIQ不許可
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msr cpsr_cxsf, r0
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ldr sp, svc_sp ; SP のｾｯﾄ
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mov lr, #0
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msr spsr_csxf, lr
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mov r0, #0xc0 | PSR_IRQ_MODE ; IRQﾓｰﾄﾞへ切り換え & IRQ/FIQ不許可
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msr cpsr_cxsf, r0
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ldr sp, irq_sp ; SP のｾｯﾄ
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mov lr, #0
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msr spsr_cxsf, lr
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mov r0, #0x40 | PSR_SYS_MODE ; ｼｽﾃﾑﾓｰﾄﾞへ切り換え & IRQ許可/FIQ不許可
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msr cpsr_cxsf, r0
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ldr sp, usr_sp ; SP のｾｯﾄ
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stack_clear
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IF :DEF: BB_MON
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ldr r4, =CPU_WRAM_END
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ELSE
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mrc p15, 0, r4, c9, c1, 0 ; DTCMｱﾄﾞﾚｽ獲得
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; bic r4, r4, lsr #0xff
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mov r4, r4, lsr #C9_TCMR_BASE_SHIFT
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mov r4, r4, lsl #C9_TCMR_BASE_SHIFT
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add r4, r4, #DTCM_SIZE
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ENDIF ; BB_MON
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adr r0, stack_clear_10 + 1
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bx r0
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CODE16
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stack_clear_10 mov r0, #0
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ldr r1, =-4*128
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1 str r0, [r4, r1]
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add r1, #4
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blt %b1
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bx lr
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;--------------------------------------------------------------------
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; ＩＲＱ処理へジャンプ
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;--------------------------------------------------------------------
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ALIGN
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CODE32
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irq_handler
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stmfd sp!, {r0-r3,r12,lr} ; ﾚｼﾞｽﾀ の退避（6ﾜｰﾄﾞ）
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mrc p15, 0, r0, c9, c1, 0 ; DTCMｱﾄﾞﾚｽ獲得
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; bic r0, r0, lsr #0xff
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mov r0, r0, lsr #C9_TCMR_BASE_SHIFT
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mov r0, r0, lsl #C9_TCMR_BASE_SHIFT
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add r0, r0, #DTCM_SIZE
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adr lr, irq_return
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ldr pc, [r0, #-4] ; 32bitｺｰﾄﾞでｼﾞｬﾝﾌﾟ
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;--------------------------------------------------------------------
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; ＩＲＱからの復帰
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;--------------------------------------------------------------------
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CODE32
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irq_return ldmfd sp!, {r0-r3,r12,lr} ; ﾚｼﾞｽﾀ の復帰
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subs pc, lr, #4
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;--------------------------------------------------------------------
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; システムコールへジャンプ
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;--------------------------------------------------------------------
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CODE32
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swi_handler
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stmfd sp!, {r11, r12, lr} ; SVCﾓｰﾄﾞ ﾚｼﾞｽﾀ退避
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ldrh r12, [lr, #-2] ; ｼｽﾃﾑｺｰﾙNo 取得（ﾊｰﾌﾜｰﾄﾞｱｸｾｽ対応）
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and r12, r12, #0xff
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adr r11, sys_table ; ｼｽﾃﾑｺｰﾙ･ｱﾄﾞﾚｽ 取得
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ldr r12, [r11, r12, lsl #2]
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mrs r11, spsr ; SVCﾓｰﾄﾞ SPSR退避（合計4ﾜｰﾄﾞ）
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stmfd sp!, {r11}
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and r11, r11, #PSR_IRQ_DISABLE ; IRQ許可状態 ｺﾋﾟｰ
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orr r11, r11, #PSR_SYS_MODE ; ｼｽﾃﾑﾓｰﾄﾞへ切り換え & FIQ許可
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msr cpsr_cxsf,r11
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stmfd sp!, {r2, lr} ; ｼｽﾃﾑﾓｰﾄﾞ ﾚｼﾞｽﾀ退避（2ﾜｰﾄﾞ）
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blx r12 ; ｺｰﾄﾞの切換とｼﾞｬﾝﾌﾟ
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;--------------------------------------------------------------------
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; システムコールからの復帰
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;--------------------------------------------------------------------
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GLOBAL swi_return
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CODE32
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swi_return ldmfd sp!, {r2, lr} ; ｼｽﾃﾑﾓｰﾄﾞ ﾚｼﾞｽﾀ復帰
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mov r12, #0xc0 | PSR_SVC_MODE ; SVCﾓｰﾄﾞへ切り換え
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msr cpsr_cxsf, r12 ; & IRQ/FIQ不許可
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ldmfd sp!, {r11} ; SVCﾓｰﾄﾞ ﾚｼﾞｽﾀ復帰
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msr spsr_cxsf, r11
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ldmfd sp!, {r11, r12, lr}
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movs pc, lr
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;--------------------------------------------------------------------
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; PAUSEレジスタ セット
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;--------------------------------------------------------------------
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GLOBAL SetPauseReg
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CODE16
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SetPauseReg
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ldr r2, =REG_PAUSE
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str r0, [r2, #0]
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bx lr
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;====================================================================
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; アドレステーブル
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;====================================================================
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ALIGN
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usr_sp DCD MON_DTCM_END - 0x140
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irq_sp DCD MON_DTCM_END - 0x60
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svc_sp DCD MON_DTCM_END - 0x40
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fiq_sp DCD ROM_HEADER_BUF - 0x64
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;fiq_sp DCD MON_DTCM_END - 0x24
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EXTERN AccessCard
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EXTERN WaitByLoop
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EXTERN WaitIntr
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EXTERN WaitVBlankIntr
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EXTERN Halt
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EXTERN IsMmem8MB
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EXTERN GetCRC16
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EXTERN DivS32
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EXTERN SqrtU32
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EXTERN CpuSet16_32
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EXTERN CpuSetFast32
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EXTERN UnPackBits32
|
||
EXTERN UnCompLZ77Byte
|
||
EXTERN UnCompLZ77Short
|
||
EXTERN UnCompHuffman32
|
||
EXTERN UnCompRLByte
|
||
EXTERN UnCompRLShort
|
||
EXTERN UnDiffByte2Byte
|
||
EXTERN UnDiffShort2Short
|
||
sys_table
|
||
DCD soft_reset ; 0
|
||
DCD 0 ; 1
|
||
|
||
DCD 0 ; 2
|
||
DCD WaitByLoop ; 3
|
||
DCD WaitIntr ; 4
|
||
DCD WaitVBlankIntr ; 5
|
||
DCD Halt ; 6
|
||
DCD 0 ; 7
|
||
DCD 0 ; 8
|
||
DCD DivS32 ; 9
|
||
DCD 0 ; 10
|
||
DCD CpuSet16_32 ; 11
|
||
DCD CpuSetFast32 ; 12
|
||
DCD SqrtU32 ; 13
|
||
DCD GetCRC16 ; 14
|
||
DCD IsMmem8MB ; 15
|
||
DCD UnPackBits32 ; 16
|
||
DCD UnCompLZ77Byte ; 17
|
||
DCD UnCompLZ77Short ; 18
|
||
DCD UnCompHuffman32 ; 19
|
||
DCD UnCompRLByte ; 20
|
||
DCD UnCompRLShort ; 21
|
||
DCD UnDiffByte2Byte ; 22
|
||
DCD 0 ; 23
|
||
DCD UnDiffShort2Short ; 24
|
||
DCD 0 ; 25
|
||
DCD 0 ; 26
|
||
DCD 0 ; 27
|
||
DCD 0 ; 28
|
||
DCD 0 ; 29
|
||
DCD 0 ; 30
|
||
DCD SetPauseReg ; 31
|
||
|
||
END
|
||
|
||
|