;======================================================================= ; IrisMemoryMapArm.s ; IRIS ƒƒ‚ƒŠƒ}ƒbƒv’è”iARMASM—pj ; ; Copyright (C) 2002-2003 NINTENDO Co.,Ltd. ;======================================================================= IF :DEF: _IRIS_MEMORY_MAP_H ELSE _IRIS_MEMORY_MAP_H * 1 INCLUDE IrisTargetArm.s INCLUDE IrisDefineArm.s ;----------------------------------------------------------------------- ; ƒƒ‚ƒŠEƒ}ƒbƒv ;----------------------------------------------------------------------- SHARED_WORK * 0x027ff000 ; ‚b‚o‚tŠÔ‹¤—Lƒ[ƒN—̈æ SHARED_WORK_END * 0x02800000 IF :DEF: NDEBUG SUBP_PRV * 0x02380000 ; ƒTƒuƒvƒƒZƒbƒTê—L—̈æiƒŠƒŠ[ƒXƒo[ƒWƒ‡ƒ“j ELSE IF :DEF: MMEM_4M SUBP_PRV * 0x02300000 ; iƒfƒoƒbƒOƒo[ƒWƒ‡ƒ“ƒƒƒCƒ“ƒƒ‚ƒŠ‚S‚l–{‘Ì„j ELSE SUBP_PRV * 0x02600000 ; iƒfƒoƒbƒOƒo[ƒWƒ‡ƒ“ƒƒƒCƒ“ƒƒ‚ƒŠ‚W‚l–{‘Ì„j ENDIF ENDIF SUBP_PRV_END * SHARED_WORK IF :DEF: IRIS_TEG :LOR: :DEF: IRIS_TS ITCM * 0x01ff8000 ; –½—ß‚s‚b‚l ITCM_END * (ITCM + 0x8000) DTCM * SUBP_PRV ; ƒf[ƒ^‚s‚b‚li‚s‚d‚fƒ{[ƒhˆÈ~j ELSE DTCM * 0x8000 ; iƒuƒŒƒbƒhƒ{[ƒhê—pj ENDIF DTCM_END * (DTCM + 0x4000) INTR_VECTOR_BUF * (DTCM_END - 0x4) ; Š„‚èž‚Ý•ªŠòƒAƒhƒŒƒX INTR_CHECK_BUF * (DTCM_END - 0x8) ; Š„‚螂݃`ƒFƒbƒN SEND_FIFO_LOCK_BUF * (DTCM_END - 0x10) ; ‚b‚o‚tŠÔ‘—M‚e‚h‚e‚nEƒƒbƒNƒoƒbƒtƒ@ TIMER3_LOCK_BUF * (DTCM_END - 0x12) ; ƒ^ƒCƒ}[‚REƒƒbƒNƒoƒbƒtƒ@ TIMER2_LOCK_BUF * (DTCM_END - 0x14) ; ƒ^ƒCƒ}[‚Q TIMER1_LOCK_BUF * (DTCM_END - 0x16) ; ƒ^ƒCƒ}[‚P TIMER0_LOCK_BUF * (DTCM_END - 0x18) ; ƒ^ƒCƒ}[‚O DMA3_LOCK_BUF * (DTCM_END - 0x1a) ; ‚c‚l‚`‚REƒƒbƒNƒoƒbƒtƒ@ DMA2_LOCK_BUF * (DTCM_END - 0x1c) ; ‚c‚l‚`‚Q DMA1_LOCK_BUF * (DTCM_END - 0x1e) ; ‚c‚l‚`‚P DMA0_LOCK_BUF * (DTCM_END - 0x20) ; ‚c‚l‚`‚O MAIN_MEM * 0x02000000 ; ƒƒCƒ“ƒƒ‚ƒŠ MAIN_MEM_END * (MAIN_MEM + 0x400000) MAIN_MEM_EX_END * (MAIN_MEM + 0x800000) ;iŠg’£Žž‚ÌÅIƒAƒhƒŒƒXj MAIN_MEM_CMD_AREA * (MAIN_MEM_EX_END - 0x2) ; ƒƒCƒ“ƒƒ‚ƒŠƒRƒ}ƒ“ƒh”­sƒGƒŠƒAiŽg—p‹ÖŽ~ƒGƒŠƒAj SHARED_LOCK_BUF * (MAIN_MEM_EX_END - 0x40) ; ‹¤—LƒŠƒ\[ƒXEƒƒbƒNƒoƒbƒtƒ@ SHARED_LOCK_BUF_END * (MAIN_MEM_EX_END - 0x10) INIT_LOCK_BUF * (MAIN_MEM_EX_END - 0x10) ; ‰Šú‰»ƒƒbƒNƒoƒbƒtƒ@ CARTRIDGE_LOCK_BUF * (MAIN_MEM_EX_END - 0x18) ; ƒJ[ƒgƒŠƒbƒWEƒƒbƒNƒoƒbƒtƒ@ CARD_LOCK_BUF * (MAIN_MEM_EX_END - 0x20) ; ƒJ[ƒhEƒƒbƒNƒoƒbƒtƒ@ WRAM_BLOCK1_LOCK_BUF * (MAIN_MEM_EX_END - 0x28) ; ‚b‚o‚t“à•”ƒ[ƒN‚q‚`‚lEƒuƒƒbƒN‚PEƒƒbƒNƒoƒbƒtƒ@ WRAM_BLOCK0_LOCK_BUF * (MAIN_MEM_EX_END - 0x30) ; ƒuƒƒbƒN‚OEƒƒbƒNƒoƒbƒtƒ@ VRAM_D_LOCK_BUF * (MAIN_MEM_EX_END - 0x38) ; ‚u‚q‚`‚l|‚cEƒƒbƒNƒoƒbƒtƒ@ VRAM_C_LOCK_BUF * (MAIN_MEM_EX_END - 0x40) ; ‚bEƒƒbƒNƒoƒbƒtƒ@ FROM_SUBP_IF_BUF * (MAIN_MEM_EX_END - 0x50) ; ƒTƒu¨ƒƒCƒ“ƒvƒƒZƒbƒTŠ„‚èž‚Ý—v‹ƒtƒ‰ƒOi‚Q‚a‚™‚”‚…~‚Wj WM_FROM_SUBP_IF_BUF * (MAIN_MEM_EX_END - 0x50) ; ƒƒCƒ„ƒŒƒXƒ}ƒl[ƒWƒƒ—\–ñ TO_SUBP_IF_BUF * (MAIN_MEM_EX_END - 0x60) ; ƒƒCƒ“¨ƒTƒuƒvƒƒZƒbƒTŠ„‚èž‚Ý—v‹ƒtƒ‰ƒOi‚Q‚a‚™‚”‚…~‚Wj WM_TO_SUBP_IF_BUF * (MAIN_MEM_EX_END - 0x60) ; ƒƒCƒ„ƒŒƒXƒ}ƒl[ƒWƒƒ—\–ñ ROM_HEADER_BUF * (MAIN_MEM_EX_END - 0x200); ‚q‚n‚l“à“o˜^ƒGƒŠƒAƒf[ƒ^Eƒoƒbƒtƒ@ DMA_CLEAR_DATA_BUF * (MAIN_MEM_EX_END - 0x210); ‚c‚l‚`ƒNƒŠƒAƒf[ƒ^Eƒoƒbƒtƒ@iŽb’è‘ΉžA”pŽ~—\’èj CPU_WRAM * 0x037f8000 ; ‚b‚o‚t“à•”ƒ[ƒN‚q‚`‚l CPU_WRAM_END * (CPU_WRAM + 0x8000) CPU_WRAM_BLOCK0 * 0x037f8000 ; ƒuƒƒbƒN‚O CPU_WRAM_BLOCK0_END * (CPU_WRAM_BLOCK0 + 0x4000) CPU_WRAM_BLOCK1 * 0x037fc000 ; ƒuƒƒbƒN‚P CPU_WRAM_BLOCK1_END * (CPU_WRAM_BLOCK1 + 0x4000) REG_BASE * 0x04000000 ; ƒŒƒWƒXƒ^ŒQ PLTT * 0x05000000 ; ƒpƒŒƒbƒg‚q‚`‚l PLTT_END * (PLTT + 0x400) BG_PLTT * (PLTT + 0x0) ; ‚a‚fƒpƒŒƒbƒg‚q‚`‚l BG_PLTT_END * (PLTT + 0x200) OBJ_PLTT * (PLTT + 0x200) ; ‚n‚a‚iƒpƒŒƒbƒg‚q‚`‚l OBJ_PLTT_END * (PLTT + 0x400) VRAM * 0x06000000 ; ‚u‚q‚`‚l BG_VRAM * (VRAM + 0x0) ; ‚a‚fƒLƒƒƒ‰ƒNƒ^/ƒXƒNƒŠ[ƒ“‚q‚`‚l BG_VRAM_END * (VRAM + 0x80000) OBJ_VRAM * (VRAM + 0x400000) ; ‚n‚a‚iƒLƒƒƒ‰ƒNƒ^‚q‚`‚l OBJ_VRAM_END * (VRAM + 0x440000) LCDC_VRAM * (VRAM + 0x800000) ; ‚k‚b‚c‚b|‚u‚q‚`‚l LCDC_VRAM_A * (VRAM + 0x800000) LCDC_VRAM_B * (VRAM + 0x820000) LCDC_VRAM_C * (VRAM + 0x840000) LCDC_VRAM_D * (VRAM + 0x860000) LCDC_VRAM_E * (VRAM + 0x880000) LCDC_VRAM_F * (VRAM + 0x890000) LCDC_VRAM_G * (VRAM + 0x894000) LCDC_VRAM_END * (VRAM + 0x898000) OAM * 0x07000000 ; ‚n‚`‚l OAM_END * (OAM + 0x400) CARTRIDGE * 0x08000000 ; ƒJ[ƒgƒŠƒbƒW CTRDG_AD16_BANK0 * 0x08000000 ; ƒJ[ƒgƒŠƒbƒW ‚`‚c‚P‚UƒoƒX ƒoƒ“ƒN‚O CTRDG_AD16_BANK0_END * 0x0a000000 CTRDG_AD16_BANK1 * 0x0a000000 ; ƒoƒ“ƒN‚P CTRDG_AD16_BANK1_END * 0x0c000000 CTRDG_AD16_BANK2 * 0x0c000000 ; ƒoƒ“ƒN‚Q CTRDG_AD16_BANK2_END * 0x0e000000 CTRDG_DT8 * 0x0e000000 ; ƒJ[ƒgƒŠƒbƒW ‚W‚‚‚‰‚”ƒf[ƒ^ƒoƒX CTRDG_DT8_END * 0x10000000 BIOS * 0xffff0000 ; ‚a‚h‚n‚r BIOS_END * (BIOS + 0x8000) ;----------------------------------------------------------------------- ; ƒƒ‚ƒŠEƒTƒCƒY ;----------------------------------------------------------------------- SHARED_WORK_SIZE * (SHARED_WORK_END - SHARED_WORK) ; ‚b‚o‚tŠÔ‹¤—Lƒ[ƒN—̈æi‚S‚j‚aˆÈãA‚Q‚ׂ̂«æƒTƒCƒYj SUBP_PRV_SIZE * (SUBP_PRV_END - SUBP_PRV) ; ƒTƒuƒvƒƒZƒbƒTê—L—̈æi‚R‚Q‚j‚aˆÈãA‚Q‚ׂ̂«æƒTƒCƒYj SHARED_LOCK_BUF_SIZE * (SHARED_LOCK_BUF_END - SHARED_LOCK_BUF) ; ‹¤—LƒŠƒ\[ƒXEƒƒbƒNƒoƒbƒtƒ@ ITCM_SIZE * 0x8000 ; –½—ß‚s‚b‚l DTCM_SIZE * 0x4000 ; ƒf[ƒ^‚s‚b‚l ICACHE_SIZE * 0x2000 ; –½—߃LƒƒƒbƒVƒ… DCACHE_SIZE * 0x1000 ; ƒf[ƒ^ƒLƒƒƒbƒVƒ… CACHE_LINE_SIZE * 32 ; ƒLƒƒƒbƒVƒ…ƒ‰ƒCƒ“ MAIN_MEM_SIZE * 0x400000 ; ƒƒCƒ“ƒƒ‚ƒŠ MAIN_MEM_EX_SIZE * 0x800000 ; iŠg’£Žžj CPU_WRAM_SIZE * 0x8000 ; ‚b‚o‚t“à•”ƒ[ƒN‚q‚`‚l ‡Œv CPU_WRAM_BLOCK0_SIZE * 0x4000 ; ƒuƒƒbƒN‚O CPU_WRAM_BLOCK1_SIZE * 0x4000 ; ƒuƒƒbƒN‚P MROM_PAGE_SIZE * 512 ; ƒ}ƒXƒN‚q‚n‚lEƒy[ƒW PLTT_SIZE * (2*256*2) ; ƒpƒŒƒbƒg‚q‚`‚l BG_PLTT_SIZE * (2*256) ; ‚a‚fƒpƒŒƒbƒg‚q‚`‚l OBJ_PLTT_SIZE * (2*256) ; ‚n‚a‚iƒpƒŒƒbƒg‚q‚`‚l BG_VRAM_SIZE * 0x80000 ; ‚a‚f|‚u‚q‚`‚l OBJ_VRAM_SIZE * 0x40000 ; ‚n‚a‚i|‚u‚q‚`‚l LCDC_VRAM_SIZE * 0x98000 ; ‚k‚b‚c‚b|‚u‚q‚`‚l VRAM_A_SIZE * 0x20000 ; ‚u‚q‚`‚l|‚` VRAM_B_SIZE * 0x20000 ; ‚a VRAM_C_SIZE * 0x20000 ; ‚b VRAM_D_SIZE * 0x20000 ; ‚c VRAM_E_SIZE * 0x10000 ; ‚d VRAM_F_SIZE * 0x4000 ; ‚e VRAM_G_SIZE * 0x4000 ; ‚f OAM_SIZE * (8*128) ; ‚n‚`‚l CARTRIDGE_SIZE * 0x02000000 ; ƒJ[ƒgƒŠƒbƒW CTRDG_AD16_BANK_SIZE * 0x02000000 ; ƒJ[ƒgƒŠƒbƒW ‚`‚c‚P‚UƒoƒX ƒoƒ“ƒN CTRDG_AD16_BANK0_SIZE * 0x02000000 ; ƒoƒ“ƒN‚O CTRDG_AD16_BANK1_SIZE * 0x02000000 ; ƒoƒ“ƒN‚P CTRDG_AD16_BANK2_SIZE * 0x02000000 ; ƒoƒ“ƒN‚Q CTRDG_DT8_SIZE * 0x02000000 ; ƒJ[ƒgƒŠƒbƒW ‚W‚‚‚‰‚”ƒf[ƒ^ƒoƒX BIOS_SIZE * 0x8000 ; ‚a‚h‚n‚r ;----------------------------------------------------------------------- ; ƒŒƒWƒXƒ^EƒAƒhƒŒƒX ;----------------------------------------------------------------------- REG_IME * (REG_BASE + 0x208) ; Š„‚螂݃}ƒXƒ^ƒCƒl[ƒuƒ‹ REG_IE * (REG_BASE + 0x210) ; Š„‚èž‚Ý‹–‰Â REG_IF * (REG_BASE + 0x214) ; Š„‚èž‚Ý—v‹ REG_SUBPINTF * (REG_BASE + 0x180) ; ƒTƒuƒvƒƒZƒbƒTƒCƒ“ƒ^ƒtƒF[ƒX REG_SUBP_FIFO_CNT * (REG_BASE + 0x184) ; ‚b‚o‚tŠÔ‚e‚h‚e‚nƒRƒ“ƒgƒ[ƒ‹ REG_SEND_FIFO * (REG_BASE + 0x188) ; ‘—M‚e‚h‚e‚n REG_RECV_FIFO * (REG_BASE + 0x100000) ; ŽóM‚e‚h‚e‚n REG_EXMEMCNT * (REG_BASE + 0x204) ; ŠO•”ƒƒ‚ƒŠƒRƒ“ƒgƒ[ƒ‹ REG_POWCNT * (REG_BASE + 0x304) ; ƒpƒ[ƒRƒ“ƒgƒ[ƒ‹ REG_DIVCNT * (REG_BASE + 0x280) ; œŽZŠí ƒRƒ“ƒgƒ[ƒ‹ REG_DIV_NUMER * (REG_BASE + 0x290) ; ”휔 REG_DIV_DENOM * (REG_BASE + 0x298) ; œ” REG_DIV_RESULT * (REG_BASE + 0x2a0) ; ¤ REG_DIVREM_RESULT * (REG_BASE + 0x2a8) ; —]‚è REG_SQRTCNT * (REG_BASE + 0x2b0) ; •½•ûª‰‰ŽZŠí ƒRƒ“ƒgƒ[ƒ‹ REG_SQRT_RESULT * (REG_BASE + 0x2b4) ; Œ‹‰Ê REG_SQRT_PARAM * (REG_BASE + 0x2b8) ; ƒpƒ‰ƒ[ƒ^ REG_DISPCNT * (REG_BASE + 0x0) ; •\Ž¦ƒRƒ“ƒgƒ[ƒ‹ REG_DISPCNT_L * (REG_BASE + 0x0) REG_DISPCNT_H * (REG_BASE + 0x2) REG_DISP2DCNT * (REG_BASE + 0x0) ; ‚Q‚c•\Ž¦ƒRƒ“ƒgƒ[ƒ‹ REG_DISP3DCNT * (REG_BASE + 0x60) ; ‚R‚c•\Ž¦ƒRƒ“ƒgƒ[ƒ‹ REG_DISPSTAT * (REG_BASE + 0x4) ; •\Ž¦ƒXƒe[ƒ^ƒX REG_VCOUNT * (REG_BASE + 0x6) ; ‚uƒJƒEƒ“ƒ^ REG_GXSTAT * (REG_BASE + 0x600) ; ƒWƒIƒƒgƒŠƒGƒ“ƒWƒ“ƒXƒe[ƒ^ƒX REG_VRAMCNT * (REG_BASE + 0x240) ; ‚u‚q‚`‚lƒRƒ“ƒgƒ[ƒ‹ REG_WRAMCNT * (REG_BASE + 0x247) ; “à•”ƒ[ƒN‚q‚`‚lƒRƒ“ƒgƒ[ƒ‹ REG_WVRAMCNT * (REG_BASE + 0x244) ; ‚u‚q‚`‚l ‚d`‚f { “à•”ƒ[ƒN‚q‚`‚l ƒRƒ“ƒgƒ[ƒ‹ REG_VRAM_A_CNT * (REG_BASE + 0x240) ; ‚u‚q‚`‚l ‚` REG_VRAM_B_CNT * (REG_BASE + 0x241) ; ‚u‚q‚`‚l ‚a REG_VRAM_C_CNT * (REG_BASE + 0x242) ; ‚u‚q‚`‚l ‚b REG_VRAM_D_CNT * (REG_BASE + 0x243) ; ‚u‚q‚`‚l ‚c REG_VRAM_E_CNT * (REG_BASE + 0x244) ; ‚u‚q‚`‚l ‚d REG_VRAM_F_CNT * (REG_BASE + 0x245) ; ‚u‚q‚`‚l ‚e REG_VRAM_G_CNT * (REG_BASE + 0x246) ; ‚u‚q‚`‚l ‚f REG_VRAM_H_CNT * (REG_BASE + 0x248) ; ‚u‚q‚`‚l ‚g REG_VRAM_I_CNT * (REG_BASE + 0x249) ; ‚u‚q‚`‚l ‚h REG_VRAM_AB_CNT * (REG_BASE + 0x240) ; ‚u‚q‚`‚l ‚`‚a REG_VRAM_CD_CNT * (REG_BASE + 0x242) ; ‚u‚q‚`‚l ‚b‚c REG_VRAM_EF_CNT * (REG_BASE + 0x244) ; ‚u‚q‚`‚l ‚d‚e REG_VRAM_G_W_CNT * (REG_BASE + 0x246) ; ‚u‚q‚`‚l ‚f { “à•”ƒ[ƒN‚q‚`‚l REG_VRAM_ABCD_CNT * (REG_BASE + 0x240) ; ‚u‚q‚`‚l ‚``‚c REG_VRAM_EFG_W_CNT * (REG_BASE + 0x244) ; ‚u‚q‚`‚l ‚d`‚f { “à•”ƒ[ƒN‚q‚`‚l REG_VRAM_HI_CNT * (REG_BASE + 0x248) ; ‚u‚q‚`‚l ‚g‚h REG_MASTER_BRIGHT * (REG_BASE + 0x6c) ; ƒ}ƒXƒ^[‹P“x ƒRƒ“ƒgƒ[ƒ‹ REG_DISPCAPCNT * (REG_BASE + 0x64) ; •\Ž¦ƒLƒƒƒvƒ`ƒƒ ƒRƒ“ƒgƒ[ƒ‹ REG_DISP_MMEM_FIFO * (REG_BASE + 0x68) ; ƒƒCƒ“ƒƒ‚ƒŠ•\Ž¦‚e‚h‚e‚n REG_MOSAIC * (REG_BASE + 0x4c) ; ƒ‚ƒUƒCƒN ƒTƒCƒY REG_BLDCNT * (REG_BASE + 0x50) ; ƒuƒŒƒ“ƒhƒ‚[ƒh ƒRƒ“ƒgƒ[ƒ‹ REG_BLDALPHA * (REG_BASE + 0x52) ; ”¼“§–¾ ƒpƒ‰ƒ[ƒ^ REG_BLDY * (REG_BASE + 0x54) ; ‹P“x•ÏX ƒpƒ‰ƒ[ƒ^ REG_WINCNT * (REG_BASE + 0x40) ; ƒEƒCƒ“ƒhƒE ƒRƒ“ƒgƒ[ƒ‹ REG_WIN0H * (REG_BASE + 0x40) ; ƒEƒCƒ“ƒhƒE‚O…•½—̈æ REG_WIN1H * (REG_BASE + 0x42) ; ƒEƒCƒ“ƒhƒE‚P…•½—̈æ REG_WIN0V * (REG_BASE + 0x44) ; ƒEƒCƒ“ƒhƒE‚O‚’¼—̈æ REG_WIN1V * (REG_BASE + 0x46) ; ƒEƒCƒ“ƒhƒE‚P‚’¼—̈æ REG_WININ * (REG_BASE + 0x48) ; ƒEƒCƒ“ƒhƒE“àƒRƒ“ƒgƒ[ƒ‹ REG_WIN0 * (REG_BASE + 0x48) ; ƒEƒCƒ“ƒhƒE‚OƒRƒ“ƒgƒ[ƒ‹ REG_WIN1 * (REG_BASE + 0x49) ; ƒEƒCƒ“ƒhƒE‚PƒRƒ“ƒgƒ[ƒ‹ REG_WIN01 * (REG_BASE + 0x48) ; ƒEƒCƒ“ƒhƒE‚OE‚PƒRƒ“ƒgƒ[ƒ‹ REG_WINOUT * (REG_BASE + 0x4a) ; ƒEƒCƒ“ƒhƒEŠOƒRƒ“ƒgƒ[ƒ‹ REG_OBJWIN * (REG_BASE + 0x4b) ; ‚n‚a‚iƒEƒCƒ“ƒhƒEƒRƒ“ƒgƒ[ƒ‹ REG_WINOUTOBJ * (REG_BASE + 0x4a) ; ƒEƒCƒ“ƒhƒEŠOE‚n‚a‚iƒEƒCƒ“ƒhƒEƒRƒ“ƒgƒ[ƒ‹ REG_BGCNT * (REG_BASE + 0x8) ; ‚a‚fƒRƒ“ƒgƒ[ƒ‹ REG_BG0CNT * (REG_BASE + 0x8) ; ‚a‚f‚OƒRƒ“ƒgƒ[ƒ‹ REG_BG1CNT * (REG_BASE + 0xa) ; ‚a‚f‚PƒRƒ“ƒgƒ[ƒ‹ REG_BG2CNT * (REG_BASE + 0xc) ; ‚a‚f‚QƒRƒ“ƒgƒ[ƒ‹ REG_BG3CNT * (REG_BASE + 0xe) ; ‚a‚f‚RƒRƒ“ƒgƒ[ƒ‹ REG_BGOFS * (REG_BASE + 0x10) ; ‚a‚fƒIƒtƒZƒbƒg REG_BG0HOFS * (REG_BASE + 0x10) ; ‚a‚f‚O‚gƒIƒtƒZƒbƒg REG_BG0VOFS * (REG_BASE + 0x12) ; ‚a‚f‚O‚uƒIƒtƒZƒbƒg REG_BG1HOFS * (REG_BASE + 0x14) ; ‚a‚f‚P‚gƒIƒtƒZƒbƒg REG_BG1VOFS * (REG_BASE + 0x16) ; ‚a‚f‚P‚uƒIƒtƒZƒbƒg REG_BG2HOFS * (REG_BASE + 0x18) ; ‚a‚f‚Q‚gƒIƒtƒZƒbƒg REG_BG2VOFS * (REG_BASE + 0x1a) ; ‚a‚f‚Q‚uƒIƒtƒZƒbƒg REG_BG3HOFS * (REG_BASE + 0x1c) ; ‚a‚f‚R‚gƒIƒtƒZƒbƒg REG_BG3VOFS * (REG_BASE + 0x1e) ; ‚a‚f‚R‚uƒIƒtƒZƒbƒg REG_BG2AFFINE * (REG_BASE + 0x20) ; ‚a‚f‚QƒAƒtƒBƒ“•ÏŠ·ƒpƒ‰ƒ[ƒ^ŒQ REG_BG2PA * (REG_BASE + 0x20) ; ‚a‚f‚Qƒ‰ƒCƒ“•ûŒü‚wÀ•W·•ª REG_BG2PB * (REG_BASE + 0x22) ; ‚a‚f‚Q ‚’¼•ûŒü‚wÀ•W·•ª REG_BG2PC * (REG_BASE + 0x24) ; ‚a‚f‚Qƒ‰ƒCƒ“•ûŒü‚xÀ•W·•ª REG_BG2PD * (REG_BASE + 0x26) ; ‚a‚f‚Q ‚’¼•ûŒü‚xÀ•W·•ª REG_BG2X * (REG_BASE + 0x28) ; ‚a‚f‚QƒXƒ^[ƒg‚wÀ•W REG_BG2Y * (REG_BASE + 0x2c) ; ‚a‚f‚QƒXƒ^[ƒg‚xÀ•W REG_BG3AFFINE * (REG_BASE + 0x30) ; ‚a‚f‚RƒAƒtƒBƒ“•ÏŠ·ƒpƒ‰ƒ[ƒ^ŒQ REG_BG3PA * (REG_BASE + 0x30) ; ‚a‚f‚Rƒ‰ƒCƒ“•ûŒü‚wÀ•W·•ª REG_BG3PB * (REG_BASE + 0x32) ; ‚a‚f‚R ‚’¼•ûŒü‚wÀ•W·•ª REG_BG3PC * (REG_BASE + 0x34) ; ‚a‚f‚Rƒ‰ƒCƒ“•ûŒü‚xÀ•W·•ª REG_BG3PD * (REG_BASE + 0x36) ; ‚a‚f‚R ‚’¼•ûŒü‚xÀ•W·•ª REG_BG3X * (REG_BASE + 0x38) ; ‚a‚f‚RƒXƒ^[ƒg‚wÀ•W REG_BG3Y * (REG_BASE + 0x3c) ; ‚a‚f‚RƒXƒ^[ƒg‚xÀ•W REG_GXFIFO * (REG_BASE + 0x400) ; ƒWƒIƒƒgƒŠ‚e‚h‚e‚n REG_LISTRAM_COUNT * (REG_BASE + 0x604) ; ƒ|ƒŠƒSƒ“ƒŠƒXƒg‚q‚`‚lƒJƒEƒ“ƒ^ REG_VTXRAM_COUNT * (REG_BASE + 0x606) ; ’¸“_‚q‚`‚lƒJƒEƒ“ƒ^ REG_RDLINES_COUNT * (REG_BASE + 0x320) ; ƒŒƒ“ƒ_ƒŠƒ“ƒOς݃‰ƒCƒ“”ƒJƒEƒ“ƒ^ REG_SWAP_BUFFERS * (REG_BASE + 0x540) ; ƒŒƒ“ƒ_ƒŠƒ“ƒOƒGƒ“ƒWƒ“ŽQƃf[ƒ^ŒQ‚̃Xƒƒbƒv REG_VIEWPORT * (REG_BASE + 0x580) ; Ž‹ŠE REG_MTX_MODE * (REG_BASE + 0x440) ; s—ñƒ‚[ƒh REG_MTX_PUSH * (REG_BASE + 0x444) ; s—ñƒvƒbƒVƒ… REG_MTX_POP * (REG_BASE + 0x448) ; s—ñƒ|ƒbƒv REG_MTX_STORE * (REG_BASE + 0x44c) ; s—ñƒXƒgƒA REG_MTX_RESTORE * (REG_BASE + 0x450) ; s—ñƒŠƒXƒgƒA REG_MTX_IDENTITY * (REG_BASE + 0x454) ; ’PˆÊs—ñ ‰Šú‰» REG_MTX_LOAD_4x4 * (REG_BASE + 0x458) ; s—ñƒ[ƒhi‚S‚˜‚Sj REG_MTX_LOAD_4x3 * (REG_BASE + 0x45c) ; i‚S‚˜‚Rj REG_MTX_MULT_4x4 * (REG_BASE + 0x460) ; s—ñæŽZ i‚S‚˜‚Sj REG_MTX_MULT_4x3 * (REG_BASE + 0x464) ; i‚S‚˜‚Rj REG_MTX_MULT_3x3 * (REG_BASE + 0x468) ; i‚R‚˜‚Rj REG_MTX_SCALE * (REG_BASE + 0x46c) ; ƒXƒP[ƒ‹s—ñæŽZi‚P‚˜‚Rj REG_MTX_TRANS * (REG_BASE + 0x470) ; ˆÚ“®s—ñæŽZi‚P‚˜‚Rj REG_CLIPMTX_RESULT * (REG_BASE + 0x640) ; ƒJƒŒƒ“ƒgƒNƒŠƒbƒvÀ•Ws—ñ “Ç‚Ýž‚Ý REG_VECMTX_RESULT * (REG_BASE + 0x680) ; ƒJƒŒƒ“ƒgƒxƒNƒgƒ‹s—ñ “Ç‚Ýž‚Ý REG_LIGHT_VECTOR * (REG_BASE + 0x4c8) ; ƒ‰ƒCƒgƒxƒNƒgƒ‹ REG_LIGHT_COLOR * (REG_BASE + 0x4cc) ; ƒ‰ƒCƒgƒJƒ‰[ REG_MATERIAL_COLOR * (REG_BASE + 0x4c0) ; ƒ}ƒeƒŠƒAƒ‹ƒJƒ‰[ REG_DIF_AMB * (REG_BASE + 0x4c0) ; ŠgŽUŒõ • ŠÂ‹«Œõ¬•ª REG_SPE_EMI * (REG_BASE + 0x4c4) ; ”½ŽËŒõ • •úŽËŒõ¬•ª REG_SHININESS * (REG_BASE + 0x4d0) ; ‹¾–Ê”½ŽË‹P“x REG_POLYGON_ATTR * (REG_BASE + 0x4a4) ; ƒ|ƒŠƒSƒ“‘®« REG_TEX_PARAM * (REG_BASE + 0x4a8) ; ƒeƒNƒXƒ`ƒƒƒpƒ‰ƒ[ƒ^ REG_TEXIMAGE_PARAM * (REG_BASE + 0x4a8) REG_TEXPLTT_BASE * (REG_BASE + 0x4ac) REG_BEGIN_VTXS * (REG_BASE + 0x500) ; ’¸“_ƒŠƒXƒg ƒXƒ^[ƒg REG_END_VTXS * (REG_BASE + 0x504) ; ’¸“_ƒŠƒXƒg ƒGƒ“ƒh REG_COLOR * (REG_BASE + 0x480) ; ’¸“_ƒJƒ‰[ REG_NORMAL * (REG_BASE + 0x484) ; ’¸“_–@ü REG_TEXCOORD * (REG_BASE + 0x488) ; ’¸“_ƒeƒNƒXƒ`ƒƒÀ•W REG_VTX_16 * (REG_BASE + 0x48c) ; ’¸“_16bitÀ•W REG_VTX_10 * (REG_BASE + 0x490) ; ’¸“_10bitÀ•W REG_VTX_XY * (REG_BASE + 0x494) ; ’¸“_16bitXYÀ•W REG_VTX_XZ * (REG_BASE + 0x498) ; ’¸“_16bitXZÀ•W REG_VTX_YZ * (REG_BASE + 0x49c) ; ’¸“_16bitYZÀ•W REG_VTX_DIFF * (REG_BASE + 0x4a0) ; ’¸“_16bitÀ•W·•ª’l REG_BOX_TEST * (REG_BASE + 0x5c0) ; ƒ{ƒbƒNƒXƒeƒXƒg REG_POS_TEST * (REG_BASE + 0x5c4) ; ˆÊ’uƒeƒXƒg REG_VEC_TEST * (REG_BASE + 0x5c8) ; ƒxƒNƒgƒ‹ƒeƒXƒg REG_POS_RESULT * (REG_BASE + 0x620) ; ˆÊ’uƒeƒXƒgŒ‹‰Ê REG_VEC_RESULT * (REG_BASE + 0x630) ; ƒxƒNƒgƒ‹ƒeƒXƒgŒ‹‰Ê REG_CLEAR_COLOR_ATTR * (REG_BASE + 0x350) ; ƒJƒ‰[•‘®«ƒoƒbƒtƒ@ ƒNƒŠƒA’l REG_CLEAR_DEPTH * (REG_BASE + 0x354) ; ‚yƒoƒbƒtƒ@ ƒNƒŠƒA’l REG_CLRIMAGE_OFFSET * (REG_BASE + 0x356) ; ƒNƒŠƒAƒCƒ[ƒW ƒIƒtƒZƒbƒg REG_EDGE_COLOR * (REG_BASE + 0x330) ; ƒGƒbƒWƒJƒ‰[ REG_FOG_COLOR * (REG_BASE + 0x358) ; ƒtƒHƒO ƒJƒ‰[ REG_FOG_OFFSET * (REG_BASE + 0x35c) ; ƒtƒHƒO ƒIƒtƒZƒbƒg REG_FOG_TABLE * (REG_BASE + 0x360) ; ƒtƒHƒO”Z“xƒe[ƒuƒ‹ REG_TOON_TABLE * (REG_BASE + 0x380) ; ƒgƒD[ƒ“ƒVƒF[ƒfƒBƒ“ƒOEƒe[ƒuƒ‹ REG_ALPHA_TEST_REF * (REG_BASE + 0x340) ; ƒAƒ‹ƒtƒ@ƒeƒXƒgŽQÆ’l REG_DISP_1DOT_DEPTH * (REG_BASE + 0x610) ; ‚Pƒhƒbƒgƒ|ƒŠƒSƒ“•`‰æŠJŽn‚y’l REG_DMA0 * (REG_BASE + 0xb0) ; ‚c‚l‚`‚O REG_DMA0SAD * (REG_BASE + 0xb0) REG_DMA0DAD * (REG_BASE + 0xb4) REG_DMA0CNT * (REG_BASE + 0xb8) REG_DMA0CNT_L * (REG_BASE + 0xb8) REG_DMA0CNT_H * (REG_BASE + 0xba) REG_DMA1 * (REG_BASE + 0xbc) ; ‚c‚l‚`‚P REG_DMA1SAD * (REG_BASE + 0xbc) REG_DMA1DAD * (REG_BASE + 0xc0) REG_DMA1CNT * (REG_BASE + 0xc4) REG_DMA1CNT_L * (REG_BASE + 0xc4) REG_DMA1CNT_H * (REG_BASE + 0xc6) REG_DMA2 * (REG_BASE + 0xc8) ; ‚c‚l‚`‚Q REG_DMA2SAD * (REG_BASE + 0xc8) REG_DMA2DAD * (REG_BASE + 0xcc) REG_DMA2CNT * (REG_BASE + 0xd0) REG_DMA2CNT_L * (REG_BASE + 0xd0) REG_DMA2CNT_H * (REG_BASE + 0xd2) REG_DMA3 * (REG_BASE + 0xd4) ; ‚c‚l‚`‚R REG_DMA3SAD * (REG_BASE + 0xd4) REG_DMA3DAD * (REG_BASE + 0xd8) REG_DMA3CNT * (REG_BASE + 0xdc) REG_DMA3CNT_L * (REG_BASE + 0xdc) REG_DMA3CNT_H * (REG_BASE + 0xde) IF :DEF: IRIS_TS REG_DMA0_CLR_DATA * (REG_BASE + 0xe0) ; ‚c‚l‚` ƒNƒŠƒAƒf[ƒ^ REG_DMA1_CLR_DATA * (REG_BASE + 0xe4) REG_DMA2_CLR_DATA * (REG_BASE + 0xe8) REG_DMA3_CLR_DATA * (REG_BASE + 0xec) ELSE REG_DMA0_CLR_DATA * (DMA_CLEAR_DATA_BUF + 0x0) REG_DMA1_CLR_DATA * (DMA_CLEAR_DATA_BUF + 0x4) REG_DMA2_CLR_DATA * (DMA_CLEAR_DATA_BUF + 0x8) REG_DMA3_CLR_DATA * (DMA_CLEAR_DATA_BUF + 0xc) ENDIF REG_TM0CNT * (REG_BASE + 0x100) ; ƒ^ƒCƒ}[‚O REG_TM0CNT_L * (REG_BASE + 0x100) REG_TM0CNT_H * (REG_BASE + 0x102) REG_TM1CNT * (REG_BASE + 0x104) ; ƒ^ƒCƒ}[‚P REG_TM1CNT_L * (REG_BASE + 0x104) REG_TM1CNT_H * (REG_BASE + 0x106) REG_TM2CNT * (REG_BASE + 0x108) ; ƒ^ƒCƒ}[‚Q REG_TM2CNT_L * (REG_BASE + 0x108) REG_TM2CNT_H * (REG_BASE + 0x10a) REG_TM3CNT * (REG_BASE + 0x10c) ; ƒ^ƒCƒ}[‚R REG_TM3CNT_L * (REG_BASE + 0x10c) REG_TM3CNT_H * (REG_BASE + 0x10e) REG_KEYINPUT * (REG_BASE + 0x130) ; ƒL[“ü—Í REG_KEYCNT * (REG_BASE + 0x132) ; ƒL[ƒRƒ“ƒgƒ[ƒ‹ REG_R0CNT * (REG_BASE + 0x134) ; ”Ä—pƒ|[ƒg‚O REG_R1CNT * (REG_BASE + 0x138) ; ‚P ;----------------------------------------------------------------------- ; ƒŒƒWƒXƒ^EƒIƒtƒZƒbƒg ;----------------------------------------------------------------------- OFFSET_REG_IME * 0x208 ; Š„‚螂݃}ƒXƒ^ƒCƒl[ƒuƒ‹ OFFSET_REG_IE * 0x210 ; Š„‚èž‚Ý‹–‰Â OFFSET_REG_IF * 0x214 ; Š„‚èž‚Ý—v‹ OFFSET_REG_SUBPINTF * 0x180 ; ƒTƒuƒvƒƒZƒbƒTƒCƒ“ƒ^ƒtƒF[ƒX OFFSET_REG_SUBP_FIFO_CNT * 0x184 ; ‚b‚o‚tŠÔ‚e‚h‚e‚nƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_SEND_FIFO * 0x188 ; ‘—M‚e‚h‚e‚n OFFSET_REG_RECV_FIFO * 0x100000 ; ŽóM‚e‚h‚e‚n OFFSET_REG_EXMEMCNT * 0x204 ; ŠO•”ƒƒ‚ƒŠƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_POWCNT * 0x304 ; ƒpƒ[ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DIVCNT * 0x280 ; œŽZŠí ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DIV_NUMER * 0x290 ; ”휔 OFFSET_REG_DIV_DENOM * 0x298 ; œ” OFFSET_REG_DIV_RESULT * 0x2a0 ; ¤ OFFSET_REG_DIVREM_RESULT * 0x2a8 ; —]‚è OFFSET_REG_SQRTCNT * 0x2b0 ; •½•ûª‰‰ŽZŠí ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_SQRT_RESULT * 0x2b4 ; Œ‹‰Ê OFFSET_REG_SQRT_PARAM * 0x2b8 ; ƒpƒ‰ƒ[ƒ^ OFFSET_REG_DISPCNT * 0x0 ; •\Ž¦ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DISPCNT_L * 0x0 OFFSET_REG_DISPCNT_H * 0x2 OFFSET_REG_DISP2DCNT * 0x0 ; ‚Q‚c•\Ž¦ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DISP3DCNT * 0x60 ; ‚R‚c•\Ž¦ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DISPSTAT * 0x4 ; •\Ž¦ƒXƒe[ƒ^ƒX OFFSET_REG_VCOUNT * 0x6 ; ‚uƒJƒEƒ“ƒ^ OFFSET_REG_GXSTAT * 0x600 ; ƒWƒIƒƒgƒŠƒGƒ“ƒWƒ“ƒXƒe[ƒ^ƒX OFFSET_REG_VRAMCNT * 0x240 ; ‚u‚q‚`‚lƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WRAMCNT * 0x247 ; “à•”ƒ[ƒN‚q‚`‚lƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WVRAMCNT * 0x244 ; ‚u‚q‚`‚l ‚d`‚f { “à•”ƒ[ƒN‚q‚`‚l ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_VRAM_A_CNT * 0x240 ; ‚u‚q‚`‚l ‚` OFFSET_REG_VRAM_B_CNT * 0x241 ; ‚u‚q‚`‚l ‚a OFFSET_REG_VRAM_C_CNT * 0x242 ; ‚u‚q‚`‚l ‚b OFFSET_REG_VRAM_D_CNT * 0x243 ; ‚u‚q‚`‚l ‚c OFFSET_REG_VRAM_E_CNT * 0x244 ; ‚u‚q‚`‚l ‚d OFFSET_REG_VRAM_F_CNT * 0x245 ; ‚u‚q‚`‚l ‚e OFFSET_REG_VRAM_G_CNT * 0x246 ; ‚u‚q‚`‚l ‚f OFFSET_REG_VRAM_H_CNT * 0x248 ; ‚u‚q‚`‚l ‚g OFFSET_REG_VRAM_I_CNT * 0x249 ; ‚u‚q‚`‚l ‚h OFFSET_REG_VRAM_AB_CNT * 0x240 ; ‚u‚q‚`‚l ‚`‚a OFFSET_REG_VRAM_CD_CNT * 0x242 ; ‚u‚q‚`‚l ‚b‚c OFFSET_REG_VRAM_EF_CNT * 0x244 ; ‚u‚q‚`‚l ‚d‚e OFFSET_REG_VRAM_G_W_CNT * 0x246 ; ‚u‚q‚`‚l ‚f { “à•”ƒ[ƒN‚q‚`‚l OFFSET_REG_VRAM_ABCD_CNT * 0x240 ; ‚u‚q‚`‚l ‚``‚c OFFSET_REG_VRAM_EFG_W_CNT * 0x244 ; ‚u‚q‚`‚l ‚d`‚f { “à•”ƒ[ƒN‚q‚`‚l OFFSET_REG_VRAM_HI_CNT * 0x248 ; ‚u‚q‚`‚l ‚g‚h OFFSET_REG_MASTER_BRIGHT * 0x6c ; ƒ}ƒXƒ^[‹P“x ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DISPCAPCNT * 0x64 ; •\Ž¦ƒLƒƒƒvƒ`ƒƒ ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_DISP_MMEM_FIFO * 0x68 ; ƒƒCƒ“ƒƒ‚ƒŠ•\Ž¦‚e‚h‚e‚n OFFSET_REG_TVOUTCNT * 0x70 ; ƒeƒŒƒro—̓Rƒ“ƒgƒ[ƒ‹ OFFSET_REG_MOSAIC * 0x4c ; ƒ‚ƒUƒCƒN ƒTƒCƒY OFFSET_REG_BLDCNT * 0x50 ; ƒuƒŒƒ“ƒhƒ‚[ƒh ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BLDALPHA * 0x52 ; ”¼“§–¾ ƒpƒ‰ƒ[ƒ^ OFFSET_REG_BLDY * 0x54 ; ‹P“x•ÏX ƒpƒ‰ƒ[ƒ^ OFFSET_REG_WINCNT * 0x40 ; ƒEƒCƒ“ƒhƒE ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WIN0H * 0x40 ; ƒEƒCƒ“ƒhƒE‚O…•½—̈æ OFFSET_REG_WIN1H * 0x42 ; ƒEƒCƒ“ƒhƒE‚P…•½—̈æ OFFSET_REG_WIN0V * 0x44 ; ƒEƒCƒ“ƒhƒE‚O‚’¼—̈æ OFFSET_REG_WIN1V * 0x46 ; ƒEƒCƒ“ƒhƒE‚P‚’¼—̈æ OFFSET_REG_WININ * 0x48 ; ƒEƒCƒ“ƒhƒE“àƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WIN0 * 0x48 ; ƒEƒCƒ“ƒhƒE‚OƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WIN1 * 0x49 ; ƒEƒCƒ“ƒhƒE‚PƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WIN01 * 0x48 ; ƒEƒCƒ“ƒhƒE‚OE‚PƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WINOUT * 0x4a ; ƒEƒCƒ“ƒhƒEŠOƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_OBJWIN * 0x4b ; ‚n‚a‚iƒEƒCƒ“ƒhƒEƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_WINOUTOBJ * 0x4a ; ƒEƒCƒ“ƒhƒEŠOE‚n‚a‚iƒEƒCƒ“ƒhƒEƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BGCNT * 0x8 ; ‚a‚fƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BG0CNT * 0x8 ; ‚a‚f‚OƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BG1CNT * 0xa ; ‚a‚f‚PƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BG2CNT * 0xc ; ‚a‚f‚QƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BG3CNT * 0xe ; ‚a‚f‚RƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_BGOFS * 0x10 ; ‚a‚fƒIƒtƒZƒbƒg OFFSET_REG_BG0HOFS * 0x10 ; ‚a‚f‚O‚gƒIƒtƒZƒbƒg OFFSET_REG_BG0VOFS * 0x12 ; ‚a‚f‚O‚uƒIƒtƒZƒbƒg OFFSET_REG_BG1HOFS * 0x14 ; ‚a‚f‚P‚gƒIƒtƒZƒbƒg OFFSET_REG_BG1VOFS * 0x16 ; ‚a‚f‚P‚uƒIƒtƒZƒbƒg OFFSET_REG_BG2HOFS * 0x18 ; ‚a‚f‚Q‚gƒIƒtƒZƒbƒg OFFSET_REG_BG2VOFS * 0x1a ; ‚a‚f‚Q‚uƒIƒtƒZƒbƒg OFFSET_REG_BG3HOFS * 0x1c ; ‚a‚f‚R‚gƒIƒtƒZƒbƒg OFFSET_REG_BG3VOFS * 0x1e ; ‚a‚f‚R‚uƒIƒtƒZƒbƒg OFFSET_REG_BG2AFFINE * 0x20 ; ‚a‚f‚QƒAƒtƒBƒ“•ÏŠ·ƒpƒ‰ƒ[ƒ^ŒQ OFFSET_REG_BG2PA * 0x20 ; ‚a‚f‚Qƒ‰ƒCƒ“•ûŒü‚wÀ•W·•ª OFFSET_REG_BG2PB * 0x22 ; ‚a‚f‚Q ‚’¼•ûŒü‚wÀ•W·•ª OFFSET_REG_BG2PC * 0x24 ; ‚a‚f‚Qƒ‰ƒCƒ“•ûŒü‚xÀ•W·•ª OFFSET_REG_BG2PD * 0x26 ; ‚a‚f‚Q ‚’¼•ûŒü‚xÀ•W·•ª OFFSET_REG_BG2X * 0x28 ; ‚a‚f‚QƒXƒ^[ƒg‚wÀ•W OFFSET_REG_BG2Y * 0x2c ; ‚a‚f‚QƒXƒ^[ƒg‚xÀ•W OFFSET_REG_BG3AFFINE * 0x30 ; ‚a‚f‚RƒAƒtƒBƒ“•ÏŠ·ƒpƒ‰ƒ[ƒ^ŒQ OFFSET_REG_BG3PA * 0x30 ; ‚a‚f‚Rƒ‰ƒCƒ“•ûŒü‚wÀ•W·•ª OFFSET_REG_BG3PB * 0x32 ; ‚a‚f‚R ‚’¼•ûŒü‚wÀ•W·•ª OFFSET_REG_BG3PC * 0x34 ; ‚a‚f‚Rƒ‰ƒCƒ“•ûŒü‚xÀ•W·•ª OFFSET_REG_BG3PD * 0x36 ; ‚a‚f‚R ‚’¼•ûŒü‚xÀ•W·•ª OFFSET_REG_BG3X * 0x38 ; ‚a‚f‚RƒXƒ^[ƒg‚wÀ•W OFFSET_REG_BG3Y * 0x3c ; ‚a‚f‚RƒXƒ^[ƒg‚xÀ•W OFFSET_REG_GXFIFO * 0x400 ; ƒWƒIƒƒgƒŠ‚e‚h‚e‚n OFFSET_REG_LISTRAM_COUNT * 0x604 ; ƒ|ƒŠƒSƒ“ƒŠƒXƒg‚q‚`‚lƒJƒEƒ“ƒ^ OFFSET_REG_VTXRAM_COUNT * 0x606 ; ’¸“_‚q‚`‚lƒJƒEƒ“ƒ^ OFFSET_REG_RDLINES_COUNT * 0x320 ; ƒŒƒ“ƒ_ƒŠƒ“ƒOς݃‰ƒCƒ“”ƒJƒEƒ“ƒ^ OFFSET_REG_SWAP_BUFFERS * 0x540 ; ƒŒƒ“ƒ_ƒŠƒ“ƒOƒGƒ“ƒWƒ“ŽQƃf[ƒ^ŒQ‚̃Xƒƒbƒv OFFSET_REG_VIEWPORT * 0x580 ; Ž‹ŠE OFFSET_REG_MTX_MODE * 0x440 ; s—ñƒ‚[ƒh OFFSET_REG_MTX_PUSH * 0x444 ; s—ñƒvƒbƒVƒ… OFFSET_REG_MTX_POP * 0x448 ; s—ñƒ|ƒbƒv OFFSET_REG_MTX_STORE * 0x44c ; s—ñƒXƒgƒA OFFSET_REG_MTX_RESTORE * 0x450 ; s—ñƒŠƒXƒgƒA OFFSET_REG_MTX_IDENTITY * 0x454 ; ’PˆÊs—ñ ‰Šú‰» OFFSET_REG_MTX_LOAD_4x4 * 0x458 ; s—ñƒ[ƒhi‚S‚˜‚Sj OFFSET_REG_MTX_LOAD_4x3 * 0x45c ; i‚S‚˜‚Rj OFFSET_REG_MTX_MULT_4x4 * 0x460 ; s—ñæŽZ i‚S‚˜‚Sj OFFSET_REG_MTX_MULT_4x3 * 0x464 ; i‚S‚˜‚Rj OFFSET_REG_MTX_MULT_3x3 * 0x468 ; i‚R‚˜‚Rj OFFSET_REG_MTX_SCALE * 0x46c ; ƒXƒP[ƒ‹s—ñæŽZi‚P‚˜‚Rj OFFSET_REG_MTX_TRANS * 0x470 ; ˆÚ“®s—ñæŽZi‚P‚˜‚Rj OFFSET_REG_CLIPMTX_RESULT * 0x640 ; ƒJƒŒƒ“ƒgƒNƒŠƒbƒvÀ•Ws—ñ “Ç‚Ýž‚Ý OFFSET_REG_VECMTX_RESULT * 0x680 ; ƒJƒŒƒ“ƒgƒxƒNƒgƒ‹s—ñ “Ç‚Ýž‚Ý OFFSET_REG_LIGHT_VECTOR * 0x4c8 ; ƒ‰ƒCƒgƒxƒNƒgƒ‹ OFFSET_REG_LIGHT_COLOR * 0x4cc ; ƒ‰ƒCƒgƒJƒ‰[ OFFSET_REG_MATERIAL_COLOR * 0x4c0 ; ƒ}ƒeƒŠƒAƒ‹ƒJƒ‰[ OFFSET_REG_DIF_AMB * 0x4c0 ; ŠgŽUŒõ • ŠÂ‹«Œõ¬•ª OFFSET_REG_SPE_EMI * 0x4c4 ; ”½ŽËŒõ • •úŽËŒõ¬•ª OFFSET_REG_SHININESS * 0x4d0 ; ‹¾–Ê”½ŽË‹P“x OFFSET_REG_POLYGON_ATTR * 0x4a4 ; ƒ|ƒŠƒSƒ“‘®« OFFSET_REG_TEX_PARAM * 0x4a8 ; ƒeƒNƒXƒ`ƒƒƒpƒ‰ƒ[ƒ^ OFFSET_REG_TEXIMAGE_PARAM * 0x4a8 OFFSET_REG_TEXPLTT_BASE * 0x4ac OFFSET_REG_BEGIN_VTXS * 0x500 ; ’¸“_ƒŠƒXƒg ƒXƒ^[ƒg OFFSET_REG_END_VTXS * 0x504 ; ’¸“_ƒŠƒXƒg ƒGƒ“ƒh OFFSET_REG_COLOR * 0x480 ; ’¸“_ƒJƒ‰[ OFFSET_REG_NORMAL * 0x484 ; ’¸“_–@ü OFFSET_REG_TEXCOORD * 0x488 ; ’¸“_ƒeƒNƒXƒ`ƒƒÀ•W OFFSET_REG_VTX_16 * 0x48c ; ’¸“_16bitÀ•W OFFSET_REG_VTX_10 * 0x490 ; ’¸“_10bitÀ•W OFFSET_REG_VTX_XY * 0x494 ; ’¸“_16bitXYÀ•W OFFSET_REG_VTX_XZ * 0x498 ; ’¸“_16bitXZÀ•W OFFSET_REG_VTX_YZ * 0x49c ; ’¸“_16bitYZÀ•W OFFSET_REG_VTX_DIFF * 0x4a0 ; ’¸“_16bitÀ•W·•ª’l OFFSET_REG_BOX_TEST * 0x5c0 ; ƒ{ƒbƒNƒXƒeƒXƒg OFFSET_REG_POS_TEST * 0x5c4 ; ˆÊ’uƒeƒXƒg OFFSET_REG_VEC_TEST * 0x5c8 ; ƒxƒNƒgƒ‹ƒeƒXƒg OFFSET_REG_POS_RESULT * 0x620 ; ˆÊ’uƒeƒXƒgŒ‹‰Ê OFFSET_REG_VEC_RESULT * 0x630 ; ƒxƒNƒgƒ‹ƒeƒXƒgŒ‹‰Ê OFFSET_REG_CLEAR_COLOR_ATTR * 0x350 ; ƒJƒ‰[•‘®«ƒoƒbƒtƒ@ ƒNƒŠƒA’l OFFSET_REG_CLEAR_DEPTH * 0x354 ; ‚yƒoƒbƒtƒ@ ƒNƒŠƒA’l OFFSET_REG_CLRIMAGE_OFFSET * 0x356 ; ƒNƒŠƒAƒCƒ[ƒW ƒIƒtƒZƒbƒg OFFSET_REG_EDGE_COLOR * 0x330 ; ƒGƒbƒWƒJƒ‰[ OFFSET_REG_FOG_COLOR * 0x358 ; ƒtƒHƒO ƒJƒ‰[ OFFSET_REG_FOG_OFFSET * 0x35c ; ƒtƒHƒO ƒIƒtƒZƒbƒg OFFSET_REG_FOG_TABLE * 0x360 ; ƒtƒHƒO”Z“xƒe[ƒuƒ‹ OFFSET_REG_TOON_TABLE * 0x380 ; ƒgƒD[ƒ“ƒVƒF[ƒfƒBƒ“ƒOEƒe[ƒuƒ‹ OFFSET_REG_ALPHA_TEST_REF * 0x340 ; ƒAƒ‹ƒtƒ@ƒeƒXƒgŽQÆ’l OFFSET_REG_DISP_1DOT_DEPTH * 0x610 ; ‚Pƒhƒbƒgƒ|ƒŠƒSƒ“•`‰æŠJŽn‚y’l OFFSET_REG_DMA0 * 0xb0 ; ‚c‚l‚`‚O OFFSET_REG_DMA0SAD * 0xb0 OFFSET_REG_DMA0DAD * 0xb4 OFFSET_REG_DMA0CNT * 0xb8 OFFSET_REG_DMA0CNT_L * 0xb8 OFFSET_REG_DMA0CNT_H * 0xba OFFSET_REG_DMA1 * 0xbc ; ‚c‚l‚`‚P OFFSET_REG_DMA1SAD * 0xbc OFFSET_REG_DMA1DAD * 0xc0 OFFSET_REG_DMA1CNT * 0xc4 OFFSET_REG_DMA1CNT_L * 0xc4 OFFSET_REG_DMA1CNT_H * 0xc6 OFFSET_REG_DMA2 * 0xc8 ; ‚c‚l‚`‚Q OFFSET_REG_DMA2SAD * 0xc8 OFFSET_REG_DMA2DAD * 0xcc OFFSET_REG_DMA2CNT * 0xd0 OFFSET_REG_DMA2CNT_L * 0xd0 OFFSET_REG_DMA2CNT_H * 0xd2 OFFSET_REG_DMA3 * 0xd4 ; ‚c‚l‚`‚R OFFSET_REG_DMA3SAD * 0xd4 OFFSET_REG_DMA3DAD * 0xd8 OFFSET_REG_DMA3CNT * 0xdc OFFSET_REG_DMA3CNT_L * 0xdc OFFSET_REG_DMA3CNT_H * 0xde IF :DEF: IRIS_TS OFFSET_REG_DMA0_CLR_DATA * 0xe0 ; ‚c‚l‚` ƒNƒŠƒAƒf[ƒ^ OFFSET_REG_DMA1_CLR_DATA * 0xe4 OFFSET_REG_DMA2_CLR_DATA * 0xe8 OFFSET_REG_DMA3_CLR_DATA * 0xec ENDIF OFFSET_REG_TM0CNT * 0x100 ; ƒ^ƒCƒ}[‚O OFFSET_REG_TM0CNT_L * 0x100 OFFSET_REG_TM0CNT_H * 0x102 OFFSET_REG_TM1CNT * 0x104 ; ƒ^ƒCƒ}[‚P OFFSET_REG_TM1CNT_L * 0x104 OFFSET_REG_TM1CNT_H * 0x106 OFFSET_REG_TM2CNT * 0x108 ; ƒ^ƒCƒ}[‚Q OFFSET_REG_TM2CNT_L * 0x108 OFFSET_REG_TM2CNT_H * 0x10a OFFSET_REG_TM3CNT * 0x10c ; ƒ^ƒCƒ}[‚R OFFSET_REG_TM3CNT_L * 0x10c OFFSET_REG_TM3CNT_H * 0x10e OFFSET_REG_KEYINPUT * 0x130 ; ƒL[“ü—Í OFFSET_REG_KEYCNT * 0x132 ; ƒL[ƒRƒ“ƒgƒ[ƒ‹ OFFSET_REG_R0CNT * 0x134 ; ”Ä—pƒ|[ƒg‚O OFFSET_REG_R1CNT * 0x138 ; ‚P ENDIF ; _IRIS_MEMORY_MAP_H END