mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
781 lines
58 KiB
Plaintext
781 lines
58 KiB
Plaintext
|
||
|
||
|
||
78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
|
||
|
||
|
||
|
||
Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\vreg_twl.asm
|
||
Para-file:
|
||
In-file: inter_asm\vreg_twl.asm
|
||
Obj-file: vreg_twl.rel
|
||
Prn-file: vreg_twl.prn
|
||
|
||
Assemble list
|
||
|
||
ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
|
||
|
||
1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24
|
||
2 2
|
||
3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
|
||
4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
|
||
5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no vreg_twl.c
|
||
6 6 ; In-file : vreg_twl.c
|
||
7 7 ; Asm-file : inter_asm\vreg_twl.asm
|
||
8 8 ; Para-file :
|
||
9 9
|
||
10 10 $PROCESSOR(9F0104)
|
||
11 11 $DEBUG
|
||
12 12 $NODEBUGA
|
||
13 13 $KANJICODE SJIS
|
||
14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
|
||
15 15
|
||
16 16 $DGS FIL_NAM, .file, 062H, 0FFFEH, 03FH, 067H, 01H, 00H
|
||
17 17 $DGS AUX_FIL, vreg_twl.c
|
||
18 18 $DGS MOD_NAM, vreg_twl, 00H, 0FFFEH, 00H, 077H, 00H, 00H
|
||
19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
|
||
20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
|
||
21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
|
||
22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
|
||
23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
|
||
24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
|
||
25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
|
||
26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
|
||
27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
|
||
28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
|
||
29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
|
||
30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
|
||
31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
|
||
32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
|
||
33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
|
||
34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
|
||
35 35 $DGS LAB_SYM, bs_S0051, U, U, 00H, 06H, 00H, 00H
|
||
36 36 $DGS LAB_SYM, es_S0051, U, U, 00H, 06H, 00H, 00H
|
||
37 37 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
|
||
38 38 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
|
||
39 39 $DGS STA_SYM, _tasks, U, U, 01H, 03H, 01H, 027H
|
||
40 40 $DGS AUX_STR, 00H, 00H, 016H, 0BH, 00H, 00H, 00H, 04H
|
||
41 41 $DGS GLV_SYM, _vreg_twl_init, U, U, 01H, 026H, 01H, 02H
|
||
42 42 $DGS AUX_FUN, 00H, U, U, 01FH, 00H, 00H
|
||
43 43 $DGS BEG_FUN, ??bf_vreg_twl_init, U, U, 00H, 065H, 01H, 00H
|
||
44 44 $DGS AUX_BEG, 019H, 00H, 01FH
|
||
45 45 $DGS END_FUN, ??ef_vreg_twl_init, U, U, 00H, 065H, 01H, 00H
|
||
46 46 $DGS AUX_END, 03H
|
||
47 47 $DGS GLV_SYM, _vreg_twl_write, U, U, 01H, 026H, 01H, 02H
|
||
48 48 $DGS AUX_FUN, 00H, U, U, 033H, 00H, 00H
|
||
49 49 $DGS BEG_FUN, ??bf_vreg_twl_write, U, U, 00H, 065H, 01H, 00H
|
||
50 50 $DGS AUX_BEG, 023H, 02H, 025H
|
||
51 51 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H
|
||
52 52 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H
|
||
53 53 $DGS BEG_BLK, ??bb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
54 54 $DGS AUX_BEG, 03H, 00H, 027H
|
||
55 55 $DGS BEG_BLK, ??bb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
56 56 $DGS AUX_BEG, 05H, 00H, 02BH
|
||
57 57 $DGS END_BLK, ??eb01_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
58 58 $DGS AUX_END, 08H
|
||
59 59 $DGS BEG_BLK, ??bb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
60 60 $DGS AUX_BEG, 027H, 00H, 00H
|
||
61 61 $DGS END_BLK, ??eb02_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
62 62 $DGS AUX_END, 02AH
|
||
63 63 $DGS END_BLK, ??eb00_vreg_twl_write, U, U, 00H, 064H, 01H, 00H
|
||
64 64 $DGS AUX_END, 02BH
|
||
65 65 $DGS END_FUN, ??ef_vreg_twl_write, U, U, 00H, 065H, 01H, 00H
|
||
66 66 $DGS AUX_END, 02DH
|
||
67 67 $DGS GLV_SYM, _vreg_twl_read, U, U, 0CH, 026H, 01H, 02H
|
||
68 68 $DGS AUX_FUN, 00H, U, U, 057H, 00H, 00H
|
||
69 69 $DGS BEG_FUN, ??bf_vreg_twl_read, U, U, 00H, 065H, 01H, 00H
|
||
70 70 $DGS AUX_BEG, 059H, 02H, 039H
|
||
71 71 $DGS REG_PAR, _phy_adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H
|
||
72 72 $DGS REG_VAR, _temp, 07H, 0FFFFH, 010CH, 04H, 00H, 00H
|
||
73 73 $DGS BEG_BLK, ??bb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
74 74 $DGS AUX_BEG, 04H, 00H, 03BH
|
||
75 75 $DGS BEG_BLK, ??bb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
76 76 $DGS AUX_BEG, 09H, 00H, 03FH
|
||
77 77 $DGS END_BLK, ??eb01_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
78 78 $DGS AUX_END, 0BH
|
||
79 79 $DGS BEG_BLK, ??bb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
80 80 $DGS AUX_BEG, 0BH, 00H, 043H
|
||
81 81 $DGS END_BLK, ??eb02_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
82 82 $DGS AUX_END, 0DH
|
||
83 83 $DGS BEG_BLK, ??bb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
84 84 $DGS AUX_BEG, 0DH, 00H, 047H
|
||
85 85 $DGS END_BLK, ??eb03_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
86 86 $DGS AUX_END, 0FH
|
||
87 87 $DGS BEG_BLK, ??bb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
88 88 $DGS AUX_BEG, 0FH, 00H, 04BH
|
||
89 89 $DGS END_BLK, ??eb04_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
90 90 $DGS AUX_END, 011H
|
||
91 91 $DGS BEG_BLK, ??bb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
92 92 $DGS AUX_BEG, 011H, 00H, 04FH
|
||
93 93 $DGS END_BLK, ??eb05_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
94 94 $DGS AUX_END, 013H
|
||
95 95 $DGS BEG_BLK, ??bb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
96 96 $DGS AUX_BEG, 013H, 00H, 00H
|
||
97 97 $DGS END_BLK, ??eb06_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
98 98 $DGS AUX_END, 015H
|
||
99 99 $DGS END_BLK, ??eb00_vreg_twl_read, U, U, 00H, 064H, 01H, 00H
|
||
100 100 $DGS AUX_END, 023H
|
||
101 101 $DGS END_FUN, ??ef_vreg_twl_read, U, U, 00H, 065H, 01H, 00H
|
||
102 102 $DGS AUX_END, 024H
|
||
103 103 $DGS GLV_SYM, _adrs_table_twl_ext2int, U, U, 0CH, 026H, 01H, 02H
|
||
104 104 $DGS AUX_FUN, 00H, U, U, 062H, 00H, 00H
|
||
105 105 $DGS BEG_FUN, ??bf_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H
|
||
106 106 $DGS AUX_BEG, 084H, 02H, 05CH
|
||
107 107 $DGS REG_PAR, _img, 06H, 0FFFFH, 010CH, 011H, 00H, 00H
|
||
108 108 $DGS BEG_BLK, ??bb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H
|
||
109 109 $DGS AUX_BEG, 02H, 00H, 00H
|
||
110 110 $DGS END_BLK, ??eb00_adrs_table_twl_ext2int, U, U, 00H, 064H, 01H, 00H
|
||
111 111 $DGS AUX_END, 0EH
|
||
112 112 $DGS END_FUN, ??ef_adrs_table_twl_ext2int, U, U, 00H, 065H, 01H, 00H
|
||
113 113 $DGS AUX_END, 0FH
|
||
114 114 $DGS GLV_SYM, _vreg_twl, U, U, 0CH, 026H, 01H, 03H
|
||
115 115 $DGS AUX_STR, 00H, 00H, 0FH, 0FH, 00H, 00H, 00H, 00H
|
||
116 116 $DGS GLV_SYM, _tsk_sw, U, U, 01H, 02H, 01H, 02H
|
||
117 117 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
118 118 $DGS GLV_SYM, _tsk_adc, U, U, 01H, 02H, 01H, 02H
|
||
119 119 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
120 120 $DGS GLV_SYM, _tsk_batt, U, U, 01H, 02H, 01H, 02H
|
||
121 121 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
122 122 $DGS GLV_SYM, _tsk_led_pow, U, U, 01H, 02H, 01H, 02H
|
||
123 123 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
124 124 $DGS GLV_SYM, _tsk_led_wifi, U, U, 01H, 02H, 01H, 02H
|
||
125 125 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
126 126 $DGS GLV_SYM, _tsk_led_notify, U, U, 01H, 02H, 01H, 02H
|
||
127 127 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
128 128 $DGS GLV_SYM, _tsk_led_cam, U, U, 01H, 02H, 01H, 02H
|
||
129 129 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
130 130 $DGS GLV_SYM, _tsk_misc_stat, U, U, 01H, 02H, 01H, 02H
|
||
131 131 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
132 132 $DGS GLV_SYM, _tsk_debug, U, U, 01H, 02H, 01H, 02H
|
||
133 133 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
134 134 $DGS GLV_SYM, _tsk_debug2, U, U, 01H, 02H, 01H, 02H
|
||
135 135 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
136 136 $DGS GLV_SYM, _tsk_sys, U, U, 01H, 02H, 01H, 02H
|
||
137 137 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
138 138 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
|
||
139 139 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
140 140 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
|
||
141 141 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
|
||
142 142
|
||
143 143 EXTRN _tsk_sw
|
||
144 144 EXTRN _tsk_adc
|
||
145 145 EXTRN _tsk_batt
|
||
146 146 EXTRN _tsk_led_pow
|
||
147 147 EXTRN _tsk_led_wifi
|
||
148 148 EXTRN _tsk_led_notify
|
||
149 149 EXTRN _tsk_led_cam
|
||
150 150 EXTRN _tsk_misc_stat
|
||
151 151 EXTRN _tsk_debug
|
||
152 152 EXTRN _tsk_debug2
|
||
153 153 EXTRN _tsk_sys
|
||
154 154 EXTRN _set_irq
|
||
155 155 EXTRN _vreg_ctr
|
||
156 156 PUBLIC _vreg_twl
|
||
157 157 PUBLIC _vreg_twl_init
|
||
158 158 PUBLIC _vreg_twl_write
|
||
159 159 PUBLIC _vreg_twl_read
|
||
160 160 PUBLIC _adrs_table_twl_ext2int
|
||
161 161
|
||
162 162 ----- @@BITS BSEG
|
||
163 163
|
||
164 164 ----- @@CNST CSEG MIRRORP
|
||
165 165 00000 01 _lpf_coeff: DB 01H ; 1
|
||
166 166 00001 02 DB 02H ; 2
|
||
167 167 00002 02 DB 02H ; 2
|
||
168 168 00003 03 DB 03H ; 3
|
||
169 169 00004 03 DB 03H ; 3
|
||
170 170 00005 02 DB 02H ; 2
|
||
171 171 00006 00 DB 00H ; 0
|
||
172 172 00007 FE DB 0FEH ; 254
|
||
173 173 00008 FB DB 0FBH ; 251
|
||
174 174 00009 F7 DB 0F7H ; 247
|
||
175 175 0000A F3 DB 0F3H ; 243
|
||
176 176 0000B F0 DB 0F0H ; 240
|
||
177 177 0000C F0 DB 0F0H ; 240
|
||
178 178 0000D F3 DB 0F3H ; 243
|
||
179 179 0000E FA DB 0FAH ; 250
|
||
180 180 0000F 04 DB 04H ; 4
|
||
181 181 00010 12 DB 012H ; 18
|
||
182 182 00011 25 DB 025H ; 37
|
||
183 183 00012 38 DB 038H ; 56
|
||
184 184 00013 4D DB 04DH ; 77
|
||
185 185 00014 5F DB 05FH ; 95
|
||
186 186 00015 6E DB 06EH ; 110
|
||
187 187 00016 77 DB 077H ; 119
|
||
188 188 00017 7A DB 07AH ; 122
|
||
189 189 00018 77 DB 077H ; 119
|
||
190 190 00019 6E DB 06EH ; 110
|
||
191 191 0001A 5F DB 05FH ; 95
|
||
192 192 0001B 4D DB 04DH ; 77
|
||
193 193 0001C 38 DB 038H ; 56
|
||
194 194 0001D 25 DB 025H ; 37
|
||
195 195 0001E 12 DB 012H ; 18
|
||
196 196 0001F 04 DB 04H ; 4
|
||
197 197 00020 FA DB 0FAH ; 250
|
||
198 198 00021 F3 DB 0F3H ; 243
|
||
199 199 00022 F0 DB 0F0H ; 240
|
||
200 200 00023 F0 DB 0F0H ; 240
|
||
201 201 00024 F3 DB 0F3H ; 243
|
||
202 202 00025 F7 DB 0F7H ; 247
|
||
203 203 00026 FB DB 0FBH ; 251
|
||
204 204 00027 FE DB 0FEH ; 254
|
||
205 205 00028 00 DB 00H ; 0
|
||
206 206 00029 02 DB 02H ; 2
|
||
207 207 0002A 03 DB 03H ; 3
|
||
208 208 0002B 03 DB 03H ; 3
|
||
209 209 0002C 02 DB 02H ; 2
|
||
210 210 0002D 02 DB 02H ; 2
|
||
211 211 0002E 01 DB 01H ; 1
|
||
212 212 0002F 00 DB (1)
|
||
213 213
|
||
214 214 ----- @@R_INIT CSEG UNIT64KP
|
||
215 215 00000 R0000 DW loww (_tsk_sw)
|
||
216 216 00002 R0000 DW loww (_tsk_adc)
|
||
217 217 00004 R0000 DW loww (_tsk_batt)
|
||
218 218 00006 R0000 DW loww (_tsk_led_pow)
|
||
219 219 00008 R0000 DW loww (_tsk_led_wifi)
|
||
220 220 0000A R0000 DW loww (_tsk_led_notify)
|
||
221 221 0000C R0000 DW loww (_tsk_led_cam)
|
||
222 222 0000E R0000 DW loww (_tsk_misc_stat)
|
||
223 223 00010 R0000 DW loww (_tsk_debug)
|
||
224 224 00012 R0000 DW loww (_tsk_debug2)
|
||
225 225 00014 R0000 DW loww (_tsk_sys)
|
||
226 226
|
||
227 227 ----- @@INIT DSEG BASEP
|
||
228 228 00000 _tasks: DS (22)
|
||
229 229
|
||
230 230 ----- @@DATA DSEG BASEP
|
||
231 231 00000 _vreg_twl: DS (15)
|
||
232 232 0000F DS (1)
|
||
233 233
|
||
234 234 ----- @@R_INIS CSEG UNIT64KP
|
||
235 235
|
||
236 236 ----- @@INIS DSEG SADDRP
|
||
237 237
|
||
238 238 ----- @@DATS DSEG SADDRP
|
||
239 239
|
||
240 240 ----- @@CNSTL CSEG PAGE64KP
|
||
241 241
|
||
242 242 ----- @@RLINIT CSEG UNIT64KP
|
||
243 243
|
||
244 244 ----- @@INITL DSEG UNIT64KP
|
||
245 245
|
||
246 246 ----- @@DATAL DSEG UNIT64KP
|
||
247 247
|
||
248 248 ----- @@CALT CSEG CALLT0
|
||
249 249
|
||
250 250 ; Sub-Routines created by CC78K0R
|
||
251 251
|
||
252 252 ----- ROM_CODE CSEG BASE
|
||
253 253 00000 bs_S0051:
|
||
254 254 00000 67 mov a,h ;[INF] 1, 1
|
||
255 255 00001 5C03 and a,#03H ; 3 ;[INF] 2, 1
|
||
256 256 00003 72 mov c,a ;[INF] 1, 1
|
||
257 257 00004 66 mov a,l ;[INF] 1, 1
|
||
258 258 00005 73 mov b,a ;[INF] 1, 1
|
||
259 259 00006 62 mov a,c ;[INF] 1, 1
|
||
260 260 00007 R180000 mov _vreg_twl[b],a ;[INF] 3, 1
|
||
261 261 0000A D7 ret ;[INF] 1, 6
|
||
262 262 0000B es_S0051:
|
||
263 263
|
||
264 264 ; *** Sub-Routine Information ***
|
||
265 265 ;
|
||
266 266 ; $SUB bs_S0051
|
||
267 267 ; CODE SIZE= 11 bytes
|
||
268 268
|
||
269 269 ; End of Sub-Routines
|
||
270 270
|
||
271 271 ; line 1 : /* ========================================================
|
||
272 272 ; line 2 :
|
||
273 273 ; line 3 : TWL<57>݊<EFBFBD><DD8A><EFBFBD><EFBFBD><EFBFBD>I2C<32><43><EFBFBD>W<EFBFBD>X<EFBFBD>^
|
||
274 274 ; line 4 :
|
||
275 275 ; line 5 : ======================================================== */
|
||
276 276 ; line 6 : #include "incs.h"
|
||
277 277 ; line 7 : #include "jhl_defs.h"
|
||
278 278 ; line 8 : #include "vreg_twl.h"
|
||
279 279 ; line 9 :
|
||
280 280 ; line 10 : #include "vreg_ctr.h"
|
||
281 281 ; line 11 : #include "renge\renge_task_intval.h"
|
||
282 282 ; line 12 :
|
||
283 283 ; line 13 : // ========================================================
|
||
284 284 ; line 14 : #define TWL_REG_VER_INFO 0x35
|
||
285 285 ; line 15 : #define NON_EXIST_REG 0xFF
|
||
286 286 ; line 16 :
|
||
287 287 ; line 17 : // ========================================================
|
||
288 288 ; line 18 : u8 vreg_twl[_REG_TWL_INT_ADRS_ENDMARK];
|
||
289 289 ; line 19 :
|
||
290 290 ; line 20 :
|
||
291 291 ; line 21 : /* ========================================================
|
||
292 292 ; line 22 : <20><><EFBFBD>z<EFBFBD><7A><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
|
||
293 293 ; line 23 : ======================================================== */
|
||
294 294 ; line 24 : void vreg_twl_init( )
|
||
295 295 ; line 25 : {
|
||
296 296
|
||
297 297 ----- ROM_CODE CSEG BASE
|
||
298 298 0000B _vreg_twl_init:
|
||
299 299 $DGL 1,25
|
||
300 300 0000B ??bf_vreg_twl_init:
|
||
301 301 ; line 26 : vreg_twl[ REG_TWL_INT_ADRS_MODE ] = 0x03;
|
||
302 302 $DGL 0,2
|
||
303 303 0000B RCF030003 mov !_vreg_twl+3,#03H ; 3 ;[INF] 4, 1
|
||
304 304 ; line 27 : }
|
||
305 305 $DGL 0,3
|
||
306 306 0000F ??ef_vreg_twl_init:
|
||
307 307 0000F D7 ret ;[INF] 1, 6
|
||
308 308 00010 ??ee_vreg_twl_init:
|
||
309 309 ; line 28 :
|
||
310 310 ; line 29 :
|
||
311 311 ; line 30 : // ========================================================
|
||
312 312 ; line 31 : // I2C<32><43><EFBFBD>z<EFBFBD><7A><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ɏ<EFBFBD><C98F><EFBFBD><EFBFBD>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>N<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
313 313 ; line 32 : //<2F>@<40><><EFBFBD><EFBFBD> adrs <20>͓<EFBFBD><CD93><EFBFBD><EFBFBD>A<EFBFBD>h<EFBFBD><68><EFBFBD>X
|
||
314 314 ; line 33 : // <20>@<40><><EFBFBD>݂<EFBFBD><DD82>Ȃ<EFBFBD><C882>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>ɃA<C983>N<EFBFBD>Z<EFBFBD>X<EFBFBD><58><EFBFBD><EFBFBD><EFBFBD>ꍇ<EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82><EFBFBD><EFBFBD>B
|
||
315 315 ; line 34 : void vreg_twl_write( u8 adrs, u8 data )
|
||
316 316 ; line 35 : {
|
||
317 317 00010 _vreg_twl_write:
|
||
318 318 $DGL 1,31
|
||
319 319 00010 C7 push hl ;[INF] 1, 1
|
||
320 320 00011 8806 mov a,[sp+6] ;[INF] 2, 1
|
||
321 321 00013 16 movw hl,ax ;[INF] 1, 1
|
||
322 322 00014 ??bf_vreg_twl_write:
|
||
323 323 ; line 36 : switch ( adrs )
|
||
324 324 $DGL 0,2
|
||
325 325 00014 17 movw ax,hl ;[INF] 1, 1
|
||
326 326 00015 F1 clrb a ;[INF] 1, 1
|
||
327 327 00016 E7 onew bc ;[INF] 1, 1
|
||
328 328 00017 340200 movw de,#02H ; 2 ;[INF] 3, 1
|
||
329 329 0001A 25 subw ax,de ;[INF] 1, 1
|
||
330 330 0001B DD2F bz $?L0010 ;[INF] 2, 4
|
||
331 331 0001D 23 subw ax,bc ;[INF] 1, 1
|
||
332 332 0001E DD17 bz $?L0007 ;[INF] 2, 4
|
||
333 333 00020 25 subw ax,de ;[INF] 1, 1
|
||
334 334 00021 DD19 bz $?L0008 ;[INF] 2, 4
|
||
335 335 00023 23 subw ax,bc ;[INF] 1, 1
|
||
336 336 00024 DD05 bz $?L0006 ;[INF] 2, 4
|
||
337 337 00026 23 subw ax,bc ;[INF] 1, 1
|
||
338 338 00027 DD1B bz $?L0009 ;[INF] 2, 4
|
||
339 339 00029 EF2D br $?L0013 ;[INF] 2, 3
|
||
340 340 ; line 37 : {
|
||
341 341 0002B ??bb00_vreg_twl_write:
|
||
342 342 ; line 38 : case ( REG_TWL_INT_ADRS_VOL ):
|
||
343 343 0002B ?L0006:
|
||
344 344 ; line 39 : {
|
||
345 345 0002B ??bb01_vreg_twl_write:
|
||
346 346 ; line 40 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_SNDVOL_CHANGE );
|
||
347 347 $DGL 0,6
|
||
348 348 0002B 304000 movw ax,#040H ; 64 ;[INF] 3, 1
|
||
349 349 0002E C1 push ax ;[INF] 1, 1
|
||
350 350 0002F 5012 mov x,#012H ; 18 ;[INF] 2, 1
|
||
351 351 00031 RFD0000 call !_set_irq ;[INF] 3, 3
|
||
352 352 00034 C0 pop ax ;[INF] 1, 1
|
||
353 353 ; line 41 : break;
|
||
354 354 $DGL 0,7
|
||
355 355 00035 EF21 br $?L0013 ;[INF] 2, 3
|
||
356 356 00037 ??eb01_vreg_twl_write:
|
||
357 357 ; line 42 : }
|
||
358 358 ; line 43 :
|
||
359 359 ; line 44 : case ( REG_TWL_INT_ADRS_MODE ):
|
||
360 360 00037 ?L0007:
|
||
361 361 ; line 45 : vreg_twl[adrs] = ( data & 0x03 );
|
||
362 362 $DGL 0,11
|
||
363 363 00037 RFD0000 call !bs_S0051 ;[INF] 3, 3
|
||
364 364 ; line 46 : break;
|
||
365 365 $DGL 0,12
|
||
366 366 0003A EF1C br $?L0013 ;[INF] 2, 3
|
||
367 367 ; line 47 :
|
||
368 368 ; line 48 : case ( REG_TWL_INT_ADRS_CAM ):
|
||
369 369 0003C ?L0008:
|
||
370 370 ; line 49 : vreg_twl[adrs] = ( data & 0x03 );
|
||
371 371 $DGL 0,15
|
||
372 372 0003C RFD0000 call !bs_S0051 ;[INF] 3, 3
|
||
373 373 ; line 50 : tsk_led_cam(); // todo <20><><EFBFBD><EFBFBD><EFBFBD>v<EFBFBD>H
|
||
374 374 $DGL 0,16
|
||
375 375 0003F RFD0000 call !_tsk_led_cam ;[INF] 3, 3
|
||
376 376 ; line 51 : break;
|
||
377 377 $DGL 0,17
|
||
378 378 00042 EF14 br $?L0013 ;[INF] 2, 3
|
||
379 379 ; line 52 :
|
||
380 380 ; line 53 : case ( REG_TWL_INT_ADRS_TEMP0 ):
|
||
381 381 00044 ?L0009:
|
||
382 382 ; line 54 : vreg_twl[adrs] = data;
|
||
383 383 $DGL 0,20
|
||
384 384 00044 66 mov a,l ;[INF] 1, 1
|
||
385 385 00045 73 mov b,a ;[INF] 1, 1
|
||
386 386 00046 67 mov a,h ;[INF] 1, 1
|
||
387 387 00047 R180000 mov _vreg_twl[b],a ;[INF] 3, 1
|
||
388 388 ; line 55 : break;
|
||
389 389 $DGL 0,21
|
||
390 390 0004A EF0C br $?L0013 ;[INF] 2, 3
|
||
391 391 ; line 56 :
|
||
392 392 ; line 57 : case ( REG_TWL_INT_ADRS_COMMAND ):
|
||
393 393 0004C ?L0010:
|
||
394 394 ; line 58 : /*
|
||
395 395 ; line 59 : if( data <= 2 ){
|
||
396 396 ; line 60 : if( ( data & REG_BIT_TWL_OFF_REQ ) != 0 )
|
||
397 397 ; line 61 : {
|
||
398 398 ; line 62 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_OFF_REQ );
|
||
399 399 ; // OFF<46><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>炵<EFBFBD><E782B5><EFBFBD>B
|
||
400 400 ; line 63 : break;
|
||
401 401 ; line 64 : }
|
||
402 402 ; line 65 : else if( ( data & REG_BIT_TWL_RESET_REQ ) != 0 )
|
||
403 403 ; line 66 : {
|
||
404 404 ; line 67 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );
|
||
405 405 ; //<2F><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>B<EFBFBD><42><EFBFBD>̂́ASPI<50><49><EFBFBD>痈<EFBFBD>܂<EFBFBD><DC82>B
|
||
406 406 ; line 68 : break;
|
||
407 407 ; line 69 : }
|
||
408 408 ; line 70 : }
|
||
409 409 ; line 71 : */
|
||
410 410 ; line 72 : if( data == REG_BIT_TWL_RESET_REQ )
|
||
411 411 $DGL 0,38
|
||
412 412 0004C 67 mov a,h ;[INF] 1, 1
|
||
413 413 0004D 91 dec a ;[INF] 1, 1
|
||
414 414 0004E DF08 bnz $?L0013 ;[INF] 2, 4
|
||
415 415 ; line 73 : {
|
||
416 416 00050 ??bb02_vreg_twl_write:
|
||
417 417 ; line 74 : set_irq( VREG_C_IRQ2, REG_BIT_TWL_RESET_REQ );
|
||
418 418 ; //<2F><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>B<EFBFBD><42><EFBFBD>̂́ASPI<50><49><EFBFBD>痈<EFBFBD>܂<EFBFBD><DC82>B
|
||
419 419 $DGL 0,40
|
||
420 420 00050 E6 onew ax ;[INF] 1, 1
|
||
421 421 00051 C1 push ax ;[INF] 1, 1
|
||
422 422 00052 5012 mov x,#012H ; 18 ;[INF] 2, 1
|
||
423 423 00054 RFD0000 call !_set_irq ;[INF] 3, 3
|
||
424 424 00057 C0 pop ax ;[INF] 1, 1
|
||
425 425 ; line 75 : break;
|
||
426 426 00058 ??eb02_vreg_twl_write:
|
||
427 427 ; line 76 : }
|
||
428 428 00058 ?L0013:
|
||
429 429 00058 ??eb00_vreg_twl_write:
|
||
430 430 ; line 77 : }
|
||
431 431 ; line 78 : return;
|
||
432 432 ; line 79 : }
|
||
433 433 $DGL 0,45
|
||
434 434 00058 ??ef_vreg_twl_write:
|
||
435 435 00058 C6 pop hl ;[INF] 1, 1
|
||
436 436 00059 D7 ret ;[INF] 1, 6
|
||
437 437 0005A ??ee_vreg_twl_write:
|
||
438 438 ; line 80 :
|
||
439 439 ; line 81 :
|
||
440 440 ; line 82 :
|
||
441 441 ; line 83 : // ========================================================
|
||
442 442 ; line 84 : // I2C<32><43><EFBFBD>z<EFBFBD><7A><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>ǂ݂܂<DD82><DC82>B
|
||
443 443 ; line 85 : //<2F>@<40><><EFBFBD><EFBFBD> adrs <20>O<EFBFBD><4F><EFBFBD>猩<EFBFBD><E78CA9><EFBFBD>Ƃ<EFBFBD><C682>́A<CC81>A<EFBFBD>h<EFBFBD><68><EFBFBD>X
|
||
444 444 ; line 86 : //<2F>@<40>߂<EFBFBD> xx <20>f<EFBFBD>[<5B>^
|
||
445 445 ; line 87 : // <20>@<40><><EFBFBD>݂<EFBFBD><DD82>Ȃ<EFBFBD><C882>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>ɃA<C983>N<EFBFBD>Z<EFBFBD>X<EFBFBD><58><EFBFBD><EFBFBD><EFBFBD>ꍇ<EFBFBD>A<EFBFBD>߂<EFBFBD><DF82>l<EFBFBD><6C>0x5A
|
||
446 446 ; line 88 : u8 vreg_twl_read( u8 phy_adrs )
|
||
447 447 ; line 89 : {
|
||
448 448 0005A _vreg_twl_read:
|
||
449 449 $DGL 1,51
|
||
450 450 0005A C7 push hl ;[INF] 1, 1
|
||
451 451 0005B 16 movw hl,ax ;[INF] 1, 1
|
||
452 452 0005C ??bf_vreg_twl_read:
|
||
453 453 ; line 90 : u8 temp;
|
||
454 454 ; line 91 :
|
||
455 455 ; line 92 : switch( phy_adrs ){
|
||
456 456 $DGL 0,4
|
||
457 457 0005C 17 movw ax,hl ;[INF] 1, 1
|
||
458 458 0005D F1 clrb a ;[INF] 1, 1
|
||
459 459 0005E E7 onew bc ;[INF] 1, 1
|
||
460 460 0005F 240000 subw ax,#00H ; 0 ;[INF] 3, 1
|
||
461 461 00062 DD0F bz $?L0018 ;[INF] 2, 4
|
||
462 462 00064 23 subw ax,bc ;[INF] 1, 1
|
||
463 463 00065 DD61 bz $?L0020 ;[INF] 2, 4
|
||
464 464 00067 240300 subw ax,#03H ; 3 ;[INF] 3, 1
|
||
465 465 0006A DD0C bz $?L0019 ;[INF] 2, 4
|
||
466 466 0006C 24FB00 subw ax,#0FBH ; 251 ;[INF] 3, 1
|
||
467 467 0006F DD6C bz $?L0022 ;[INF] 2, 4
|
||
468 468 00071 EF60 br $?L0021 ;[INF] 2, 3
|
||
469 469 00073 ??bb00_vreg_twl_read:
|
||
470 470 ; line 93 : case( REG_TWL_INT_ADRS_VER_INFO ):
|
||
471 471 00073 ?L0018:
|
||
472 472 ; line 94 : return( TWL_REG_VER_INFO );
|
||
473 473 $DGL 0,6
|
||
474 474 00073 323500 movw bc,#035H ; 53 ;[INF] 3, 1
|
||
475 475 00076 EF66 br $?L0017 ;[INF] 2, 3
|
||
476 476 ; line 95 :
|
||
477 477 ; line 96 : case( REG_TWL_INT_ADRS_POWER_INFO ):
|
||
478 478 00078 ?L0019:
|
||
479 479 ; line 97 : if( vreg_ctr[ VREG_C_BT_REMAIN ] > 90 ){
|
||
480 480 $DGL 0,9
|
||
481 481 00078 R400B005B cmp !_vreg_ctr+11,#05BH ; 91 ;[INF] 4, 1
|
||
482 482 0007C DC06 bc $?L0025 ;[INF] 2, 4
|
||
483 483 0007E ??bb01_vreg_twl_read:
|
||
484 484 ; line 98 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0F;
|
||
485 485 $DGL 0,10
|
||
486 486 0007E RCF04000F mov !_vreg_twl+4,#0FH ; 15 ;[INF] 4, 1
|
||
487 487 00082 ??eb01_vreg_twl_read:
|
||
488 488 ; line 99 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 75 ){
|
||
489 489 $DGL 0,11
|
||
490 490 00082 EF32 br $?L0034 ;[INF] 2, 3
|
||
491 491 00084 ?L0025:
|
||
492 492 00084 R400B004C cmp !_vreg_ctr+11,#04CH ; 76 ;[INF] 4, 1
|
||
493 493 00088 DC06 bc $?L0027 ;[INF] 2, 4
|
||
494 494 0008A ??bb02_vreg_twl_read:
|
||
495 495 ; line 100 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x0B;
|
||
496 496 $DGL 0,12
|
||
497 497 0008A RCF04000B mov !_vreg_twl+4,#0BH ; 11 ;[INF] 4, 1
|
||
498 498 0008E ??eb02_vreg_twl_read:
|
||
499 499 ; line 101 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 50 ){
|
||
500 500 $DGL 0,13
|
||
501 501 0008E EF26 br $?L0034 ;[INF] 2, 3
|
||
502 502 00090 ?L0027:
|
||
503 503 00090 R400B0033 cmp !_vreg_ctr+11,#033H ; 51 ;[INF] 4, 1
|
||
504 504 00094 DC06 bc $?L0029 ;[INF] 2, 4
|
||
505 505 00096 ??bb03_vreg_twl_read:
|
||
506 506 ; line 102 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x07;
|
||
507 507 $DGL 0,14
|
||
508 508 00096 RCF040007 mov !_vreg_twl+4,#07H ; 7 ;[INF] 4, 1
|
||
509 509 0009A ??eb03_vreg_twl_read:
|
||
510 510 ; line 103 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 25 ){
|
||
511 511 $DGL 0,15
|
||
512 512 0009A EF1A br $?L0034 ;[INF] 2, 3
|
||
513 513 0009C ?L0029:
|
||
514 514 0009C R400B001A cmp !_vreg_ctr+11,#01AH ; 26 ;[INF] 4, 1
|
||
515 515 000A0 DC06 bc $?L0031 ;[INF] 2, 4
|
||
516 516 000A2 ??bb04_vreg_twl_read:
|
||
517 517 ; line 104 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x03;
|
||
518 518 $DGL 0,16
|
||
519 519 000A2 RCF040003 mov !_vreg_twl+4,#03H ; 3 ;[INF] 4, 1
|
||
520 520 000A6 ??eb04_vreg_twl_read:
|
||
521 521 ; line 105 : }else if( vreg_ctr[ VREG_C_BT_REMAIN ] > 5 ){
|
||
522 522 $DGL 0,17
|
||
523 523 000A6 EF0E br $?L0034 ;[INF] 2, 3
|
||
524 524 000A8 ?L0031:
|
||
525 525 000A8 R400B0006 cmp !_vreg_ctr+11,#06H ; 6 ;[INF] 4, 1
|
||
526 526 000AC DC05 bc $?L0033 ;[INF] 2, 4
|
||
527 527 000AE ??bb05_vreg_twl_read:
|
||
528 528 ; line 106 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x01;
|
||
529 529 $DGL 0,18
|
||
530 530 000AE RE50400 oneb !_vreg_twl+4 ;[INF] 3, 1
|
||
531 531 000B1 ??eb05_vreg_twl_read:
|
||
532 532 ; line 107 : }else{
|
||
533 533 $DGL 0,19
|
||
534 534 000B1 EF03 br $?L0034 ;[INF] 2, 3
|
||
535 535 000B3 ?L0033:
|
||
536 536 000B3 ??bb06_vreg_twl_read:
|
||
537 537 ; line 108 : vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] = 0x00;
|
||
538 538 $DGL 0,20
|
||
539 539 000B3 RF50400 clrb !_vreg_twl+4 ;[INF] 3, 1
|
||
540 540 000B6 ??eb06_vreg_twl_read:
|
||
541 541 ; line 109 : }
|
||
542 542 000B6 ?L0034:
|
||
543 543 ; line 110 :
|
||
544 544 ; line 111 : return( vreg_twl[ REG_TWL_INT_ADRS_POWER_INFO ] | ( !B
|
||
545 545 ; T_CHG_n ? 0x80: 0x00 ) ); // <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^bit
|
||
546 546 $DGL 0,23
|
||
547 547 000B6 31120505 bt P5.1,$?L0035 ;[INF] 4, 5
|
||
548 548 000BA 308000 movw ax,#080H ; 128 ;[INF] 3, 1
|
||
549 549 000BD EF01 br $?L0036 ;[INF] 2, 3
|
||
550 550 000BF ?L0035:
|
||
551 551 000BF F6 clrw ax ;[INF] 1, 1
|
||
552 552 000C0 ?L0036:
|
||
553 553 000C0 08 xch a,x ;[INF] 1, 1
|
||
554 554 000C1 R6F0400 or a,!_vreg_twl+4 ;[INF] 3, 1
|
||
555 555 000C4 08 xch a,x ;[INF] 1, 1
|
||
556 556 000C5 12 movw bc,ax ;[INF] 1, 1
|
||
557 557 000C6 EF16 br $?L0017 ;[INF] 2, 3
|
||
558 558 ; line 112 :
|
||
559 559 ; line 113 : case( REG_TWL_INT_ADRS_IRQ ):
|
||
560 560 000C8 ?L0020:
|
||
561 561 ; line 114 : temp = vreg_twl[ REG_TWL_INT_ADRS_IRQ ];
|
||
562 562 $DGL 0,26
|
||
563 563 000C8 R8F0100 mov a,!_vreg_twl+1 ;[INF] 3, 1
|
||
564 564 ; line 115 : vreg_twl[ REG_TWL_INT_ADRS_IRQ ]= 0;
|
||
565 565 $DGL 0,27
|
||
566 566 000CB RF50100 clrb !_vreg_twl+1 ;[INF] 3, 1
|
||
567 567 ; line 116 : return( temp );
|
||
568 568 $DGL 0,28
|
||
569 569 000CE 318E shrw ax,8 ;[INF] 2, 1
|
||
570 570 000D0 12 movw bc,ax ;[INF] 1, 1
|
||
571 571 000D1 EF0B br $?L0017 ;[INF] 2, 3
|
||
572 572 ; line 117 :
|
||
573 573 ; line 118 : default:
|
||
574 574 000D3 ?L0021:
|
||
575 575 ; line 119 : return( vreg_twl[ phy_adrs ] );
|
||
576 576 $DGL 0,31
|
||
577 577 000D3 66 mov a,l ;[INF] 1, 1
|
||
578 578 000D4 73 mov b,a ;[INF] 1, 1
|
||
579 579 000D5 R090000 mov a,_vreg_twl[b] ;[INF] 3, 1
|
||
580 580 000D8 318E shrw ax,8 ;[INF] 2, 1
|
||
581 581 000DA 12 movw bc,ax ;[INF] 1, 1
|
||
582 582 000DB EF01 br $?L0017 ;[INF] 2, 3
|
||
583 583 ; line 120 :
|
||
584 584 ; line 121 : case( REG_TWL_ADRS_NON_EXIST ):
|
||
585 585 000DD ?L0022:
|
||
586 586 ; line 122 : return( 0x00 );
|
||
587 587 $DGL 0,34
|
||
588 588 000DD F7 clrw bc ;[INF] 1, 1
|
||
589 589 000DE ??eb00_vreg_twl_read:
|
||
590 590 ; line 123 : }
|
||
591 591 000DE ?L0017:
|
||
592 592 ; line 124 : }
|
||
593 593 $DGL 0,36
|
||
594 594 000DE ??ef_vreg_twl_read:
|
||
595 595 000DE C6 pop hl ;[INF] 1, 1
|
||
596 596 000DF D7 ret ;[INF] 1, 6
|
||
597 597 000E0 ??ee_vreg_twl_read:
|
||
598 598 ; line 125 :
|
||
599 599 ; line 126 :
|
||
600 600 ; line 127 :
|
||
601 601 ; line 128 : // ========================================================
|
||
602 602 ; line 129 : // <20>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD>猩<EFBFBD><E78CA9><EFBFBD>钎<EFBFBD>H<EFBFBD><48><EFBFBD>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD><58><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>̘A<CC98><41><EFBFBD>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>ɓǂݑւ<DD91><D682><EFBFBD>
|
||
603 603 ; line 130 : // 0xFF<46>͑<EFBFBD><CD91>݂<EFBFBD><DD82>Ȃ<EFBFBD><C882>A<EFBFBD>h<EFBFBD><68><EFBFBD>X<EFBFBD>B
|
||
604 604 ; line 131 : u8 adrs_table_twl_ext2int( u8 img )
|
||
605 605 ; line 132 : {
|
||
606 606 000E0 _adrs_table_twl_ext2int:
|
||
607 607 $DGL 1,87
|
||
608 608 000E0 C7 push hl ;[INF] 1, 1
|
||
609 609 000E1 16 movw hl,ax ;[INF] 1, 1
|
||
610 610 000E2 ??bf_adrs_table_twl_ext2int:
|
||
611 611 ; line 133 : switch( img ){
|
||
612 612 $DGL 0,2
|
||
613 613 000E2 17 movw ax,hl ;[INF] 1, 1
|
||
614 614 000E3 F1 clrb a ;[INF] 1, 1
|
||
615 615 000E4 E7 onew bc ;[INF] 1, 1
|
||
616 616 000E5 240000 subw ax,#00H ; 0 ;[INF] 3, 1
|
||
617 617 000E8 DD3C bz $?L0046 ;[INF] 2, 4
|
||
618 618 000EA 241000 subw ax,#010H ; 16 ;[INF] 3, 1
|
||
619 619 000ED DD1C bz $?L0040 ;[INF] 2, 4
|
||
620 620 000EF 23 subw ax,bc ;[INF] 1, 1
|
||
621 621 000F0 DD1C bz $?L0041 ;[INF] 2, 4
|
||
622 622 000F2 23 subw ax,bc ;[INF] 1, 1
|
||
623 623 000F3 DD34 bz $?L0047 ;[INF] 2, 4
|
||
624 624 000F5 240E00 subw ax,#0EH ; 14 ;[INF] 3, 1
|
||
625 625 000F8 DD18 bz $?L0042 ;[INF] 2, 4
|
||
626 626 000FA 241100 subw ax,#011H ; 17 ;[INF] 3, 1
|
||
627 627 000FD DD18 bz $?L0043 ;[INF] 2, 4
|
||
628 628 000FF 240F00 subw ax,#0FH ; 15 ;[INF] 3, 1
|
||
629 629 00102 DD18 bz $?L0044 ;[INF] 2, 4
|
||
630 630 00104 243000 subw ax,#030H ; 48 ;[INF] 3, 1
|
||
631 631 00107 DD18 bz $?L0045 ;[INF] 2, 4
|
||
632 632 00109 EF23 br $?L0048 ;[INF] 2, 3
|
||
633 633 0010B ??bb00_adrs_table_twl_ext2int:
|
||
634 634 ; line 134 : case( REG_TWL_ADRS_IRQ ): return( REG_TWL_INT_ADRS_
|
||
635 635 ; IRQ );
|
||
636 636 $DGL 0,3
|
||
637 637 0010B ?L0040:
|
||
638 638 0010B E7 onew bc ;[INF] 1, 1
|
||
639 639 0010C EF22 br $?L0039 ;[INF] 2, 3
|
||
640 640 ; line 135 : case( REG_TWL_ADRS_COMMAND ): return( REG_TWL_INT_ADRS_
|
||
641 641 ; COMMAND );
|
||
642 642 $DGL 0,4
|
||
643 643 0010E ?L0041:
|
||
644 644 0010E E7 onew bc ;[INF] 1, 1
|
||
645 645 0010F A3 incw bc ;[INF] 1, 1
|
||
646 646 00110 EF1E br $?L0039 ;[INF] 2, 3
|
||
647 647 ; line 136 : case( REG_TWL_ADRS_POWER_INFO ): return( REG_TWL_INT_ADRS_
|
||
648 648 ; POWER_INFO );
|
||
649 649 $DGL 0,5
|
||
650 650 00112 ?L0042:
|
||
651 651 00112 320400 movw bc,#04H ; 4 ;[INF] 3, 1
|
||
652 652 00115 EF19 br $?L0039 ;[INF] 2, 3
|
||
653 653 ; line 137 : case( REG_TWL_ADRS_CAM ): return( REG_TWL_INT_ADRS_
|
||
654 654 ; CAM );
|
||
655 655 $DGL 0,6
|
||
656 656 00117 ?L0043:
|
||
657 657 00117 320500 movw bc,#05H ; 5 ;[INF] 3, 1
|
||
658 658 0011A EF14 br $?L0039 ;[INF] 2, 3
|
||
659 659 ; line 138 : case( REG_TWL_ADRS_VOL ): return( REG_TWL_INT_ADRS_
|
||
660 660 ; VOL );
|
||
661 661 $DGL 0,7
|
||
662 662 0011C ?L0044:
|
||
663 663 0011C 320600 movw bc,#06H ; 6 ;[INF] 3, 1
|
||
664 664 0011F EF0F br $?L0039 ;[INF] 2, 3
|
||
665 665 ; line 139 : case( REG_TWL_ADRS_TEMP0 ): return( REG_TWL_INT_ADRS_
|
||
666 666 ; TEMP0 );
|
||
667 667 $DGL 0,8
|
||
668 668 00121 ?L0045:
|
||
669 669 00121 320700 movw bc,#07H ; 7 ;[INF] 3, 1
|
||
670 670 00124 EF0A br $?L0039 ;[INF] 2, 3
|
||
671 671 ; line 140 : case( REG_TWL_ADRS_VER_INFO ): return( REG_TWL_INT_ADRS_
|
||
672 672 ; VER_INFO );
|
||
673 673 $DGL 0,9
|
||
674 674 00126 ?L0046:
|
||
675 675 00126 F7 clrw bc ;[INF] 1, 1
|
||
676 676 00127 EF07 br $?L0039 ;[INF] 2, 3
|
||
677 677 ; line 141 : case( REG_TWL_ADRS_MODE ): return( REG_TWL_INT_ADRS_
|
||
678 678 ; MODE );
|
||
679 679 $DGL 0,10
|
||
680 680 00129 ?L0047:
|
||
681 681 00129 320300 movw bc,#03H ; 3 ;[INF] 3, 1
|
||
682 682 0012C EF02 br $?L0039 ;[INF] 2, 3
|
||
683 683 ; line 142 : default: return( REG_TWL_ADRS_NON_
|
||
684 684 ; EXIST );
|
||
685 685 $DGL 0,11
|
||
686 686 0012E ?L0048:
|
||
687 687 0012E F7 clrw bc ;[INF] 1, 1
|
||
688 688 0012F 92 dec c ;[INF] 1, 1
|
||
689 689 00130 ??eb00_adrs_table_twl_ext2int:
|
||
690 690 ; line 143 : // 0<><30><EFBFBD>ǂ߂<C782><DF82>悢<CE82>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>ėǂ<C497>
|
||
691 691 ; line 144 : // case( REG_TWL_ADRS_WIFI ): return( REG_TWL_INT_ADR
|
||
692 692 ; S_WIFI );
|
||
693 693 ; line 145 : }
|
||
694 694 00130 ?L0039:
|
||
695 695 ; line 146 : }
|
||
696 696 $DGL 0,15
|
||
697 697 00130 ??ef_adrs_table_twl_ext2int:
|
||
698 698 00130 C6 pop hl ;[INF] 1, 1
|
||
699 699 00131 D7 ret ;[INF] 1, 6
|
||
700 700 00132 ??ee_adrs_table_twl_ext2int:
|
||
701 701
|
||
702 702 ----- @@CODEL CSEG
|
||
703 703
|
||
704 704 ----- @@BASE CSEG BASE
|
||
705 705 END
|
||
706 706
|
||
707 707
|
||
708 708 ; *** Code Information ***
|
||
709 709 ;
|
||
710 710 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\vreg_twl.c
|
||
711 711 ;
|
||
712 712 ; $FUNC vreg_twl_init(25)
|
||
713 713 ; void=(void)
|
||
714 714 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 7 clocks, STACK_SIZE= 0 bytes
|
||
715 715 ;
|
||
716 716 ; $FUNC vreg_twl_write(35)
|
||
717 717 ; void=(unsigned char adrs:x, unsigned char data:[sp+6])
|
||
718 718 ; CODE SIZE= 74 bytes, CLOCK_SIZE= 113 clocks, STACK_SIZE= 8 bytes
|
||
719 719 ;
|
||
720 720 ; $CALL set_irq(40)
|
||
721 721 ; void=(int:ax, int:[sp+4])
|
||
722 722 ;
|
||
723 723 ; $CALL tsk_led_cam(50)
|
||
724 724 ; void=(void)
|
||
725 725 ;
|
||
726 726 ; $CALL set_irq(74)
|
||
727 727 ; void=(int:ax, int:[sp+4])
|
||
728 728 ;
|
||
729 729 ; $FUNC vreg_twl_read(89)
|
||
730 730 ; bc=(unsigned char phy_adrs:x)
|
||
731 731 ; CODE SIZE= 134 bytes, CLOCK_SIZE= 118 clocks, STACK_SIZE= 2 bytes
|
||
732 732 ;
|
||
733 733 ; $FUNC adrs_table_twl_ext2int(132)
|
||
734 734 ; bc=(unsigned char img:x)
|
||
735 735 ; CODE SIZE= 82 bytes, CLOCK_SIZE= 90 clocks, STACK_SIZE= 2 bytes
|
||
736 736
|
||
737 737 ; Target chip : uPD79F0104
|
||
738 738 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.0 @@BITS
|
||
00000 00030H @@CNST
|
||
00000 00016H @@R_INIT
|
||
00000 00016H @@INIT
|
||
00000 00010H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H @@CNSTL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 00132H ROM_CODE
|
||
00000 00000H @@CODEL
|
||
00000 00000H @@BASE
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|