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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
1363 lines
100 KiB
Plaintext
1363 lines
100 KiB
Plaintext
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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
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Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\task_sys.asm
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Para-file:
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In-file: inter_asm\task_sys.asm
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Obj-file: task_sys.rel
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Prn-file: task_sys.prn
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Assemble list
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ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
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1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
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2 2
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3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no task_sys.c
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6 6 ; In-file : task_sys.c
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7 7 ; Asm-file : inter_asm\task_sys.asm
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8 8 ; Para-file :
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9 9
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10 10 $PROCESSOR(9F0104)
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11 11 $DEBUG
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12 12 $NODEBUGA
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13 13 $KANJICODE SJIS
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14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
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15 15
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16 16 $DGS FIL_NAM, .file, 0C7H, 0FFFEH, 03FH, 067H, 01H, 00H
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17 17 $DGS AUX_FIL, task_sys.c
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18 18 $DGS MOD_NAM, task_sys, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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36 36 $DGS AUX_TAG, 01H, 01EH
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37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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45 45 $DGS AUX_EOS, 013H, 01H
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46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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47 47 $DGS AUX_TAG, 01H, 025H
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48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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52 52 $DGS AUX_EOS, 01EH, 01H
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53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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54 54 $DGS AUX_TAG, 01H, 02FH
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55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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62 62 $DGS AUX_EOS, 025H, 01H
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63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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64 64 $DGS AUX_TAG, 04H, 041H
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65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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70 70 $DGS AUX_BIT, 00H, 01H
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71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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72 72 $DGS AUX_BIT, 00H, 01H
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73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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74 74 $DGS AUX_BIT, 00H, 01H
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75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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76 76 $DGS AUX_BIT, 00H, 01H
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77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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80 80 $DGS AUX_EOS, 02FH, 04H
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81 81 $DGS ENM_TAG, .2fake, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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82 82 $DGS AUX_TAG, 01H, 047H
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83 83 $DGS MEB_ENM, _ERR_FINISED, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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84 84 $DGS MEB_ENM, _ERR_CONTINUE, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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85 85 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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86 86 $DGS AUX_EOS, 041H, 01H
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87 87 $DGS LAB_SYM, bs_F0057, U, U, 00H, 06H, 00H, 00H
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88 88 $DGS LAB_SYM, es_F0057, U, U, 00H, 06H, 00H, 00H
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89 89 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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90 90 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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91 91 $DGS GLV_SYM, _tsk_sys, U, U, 01H, 026H, 01H, 02H
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92 92 $DGS AUX_FUN, 00H, U, U, 0A6H, 00H, 00H
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93 93 $DGS BEG_FUN, ??bf_tsk_sys, U, U, 00H, 065H, 01H, 00H
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94 94 $DGS AUX_BEG, 023H, 00H, 050H
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95 95 $DGS STA_SYM, _timeout, ?L0003, U, 0CH, 03H, 00H, 00H
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96 96 $DGS BEG_BLK, ??bb00_tsk_sys, U, U, 00H, 064H, 01H, 00H
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97 97 $DGS AUX_BEG, 05H, 00H, 052H
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98 98 $DGS BEG_BLK, ??bb01_tsk_sys, U, U, 00H, 064H, 01H, 00H
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99 99 $DGS AUX_BEG, 0BH, 00H, 054H
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100 100 $DGS BEG_BLK, ??bb02_tsk_sys, U, U, 00H, 064H, 01H, 00H
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101 101 $DGS AUX_BEG, 010H, 00H, 058H
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102 102 $DGS END_BLK, ??eb02_tsk_sys, U, U, 00H, 064H, 01H, 00H
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103 103 $DGS AUX_END, 012H
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104 104 $DGS BEG_BLK, ??bb03_tsk_sys, U, U, 00H, 064H, 01H, 00H
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105 105 $DGS AUX_BEG, 014H, 00H, 05CH
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106 106 $DGS END_BLK, ??eb03_tsk_sys, U, U, 00H, 064H, 01H, 00H
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107 107 $DGS AUX_END, 016H
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108 108 $DGS BEG_BLK, ??bb04_tsk_sys, U, U, 00H, 064H, 01H, 00H
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109 109 $DGS AUX_BEG, 018H, 00H, 060H
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110 110 $DGS END_BLK, ??eb04_tsk_sys, U, U, 00H, 064H, 01H, 00H
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111 111 $DGS AUX_END, 01CH
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112 112 $DGS BEG_BLK, ??bb05_tsk_sys, U, U, 00H, 064H, 01H, 00H
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113 113 $DGS AUX_BEG, 01FH, 00H, 066H
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114 114 $DGS END_BLK, ??eb05_tsk_sys, U, U, 00H, 064H, 01H, 00H
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115 115 $DGS AUX_END, 022H
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116 116 $DGS END_BLK, ??eb01_tsk_sys, U, U, 00H, 064H, 01H, 00H
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117 117 $DGS AUX_END, 029H
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118 118 $DGS BEG_BLK, ??bb06_tsk_sys, U, U, 00H, 064H, 01H, 00H
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119 119 $DGS AUX_BEG, 034H, 00H, 06AH
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120 120 $DGS END_BLK, ??eb06_tsk_sys, U, U, 00H, 064H, 01H, 00H
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121 121 $DGS AUX_END, 039H
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122 122 $DGS BEG_BLK, ??bb07_tsk_sys, U, U, 00H, 064H, 01H, 00H
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123 123 $DGS AUX_BEG, 048H, 00H, 06EH
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124 124 $DGS END_BLK, ??eb07_tsk_sys, U, U, 00H, 064H, 01H, 00H
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125 125 $DGS AUX_END, 04BH
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126 126 $DGS BEG_BLK, ??bb08_tsk_sys, U, U, 00H, 064H, 01H, 00H
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127 127 $DGS AUX_BEG, 04DH, 00H, 072H
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128 128 $DGS END_BLK, ??eb08_tsk_sys, U, U, 00H, 064H, 01H, 00H
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129 129 $DGS AUX_END, 051H
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130 130 $DGS BEG_BLK, ??bb09_tsk_sys, U, U, 00H, 064H, 01H, 00H
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131 131 $DGS AUX_BEG, 065H, 00H, 076H
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132 132 $DGS END_BLK, ??eb09_tsk_sys, U, U, 00H, 064H, 01H, 00H
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133 133 $DGS AUX_END, 067H
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134 134 $DGS BEG_BLK, ??bb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H
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135 135 $DGS AUX_BEG, 069H, 00H, 07AH
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136 136 $DGS END_BLK, ??eb0A_tsk_sys, U, U, 00H, 064H, 01H, 00H
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137 137 $DGS AUX_END, 069H
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138 138 $DGS BEG_BLK, ??bb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H
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139 139 $DGS AUX_BEG, 084H, 00H, 07EH
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140 140 $DGS END_BLK, ??eb0B_tsk_sys, U, U, 00H, 064H, 01H, 00H
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141 141 $DGS AUX_END, 087H
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142 142 $DGS BEG_BLK, ??bb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H
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143 143 $DGS AUX_BEG, 092H, 00H, 082H
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144 144 $DGS END_BLK, ??eb0C_tsk_sys, U, U, 00H, 064H, 01H, 00H
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145 145 $DGS AUX_END, 0A1H
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146 146 $DGS BEG_BLK, ??bb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H
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147 147 $DGS AUX_BEG, 0A9H, 00H, 086H
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148 148 $DGS END_BLK, ??eb0D_tsk_sys, U, U, 00H, 064H, 01H, 00H
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149 149 $DGS AUX_END, 0ABH
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150 150 $DGS BEG_BLK, ??bb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H
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151 151 $DGS AUX_BEG, 0B1H, 00H, 08AH
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152 152 $DGS END_BLK, ??eb0E_tsk_sys, U, U, 00H, 064H, 01H, 00H
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153 153 $DGS AUX_END, 0B1H
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154 154 $DGS BEG_BLK, ??bb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H
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155 155 $DGS AUX_BEG, 0C4H, 00H, 08EH
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156 156 $DGS END_BLK, ??eb0F_tsk_sys, U, U, 00H, 064H, 01H, 00H
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157 157 $DGS AUX_END, 0C7H
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158 158 $DGS BEG_BLK, ??bb10_tsk_sys, U, U, 00H, 064H, 01H, 00H
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159 159 $DGS AUX_BEG, 0DEH, 00H, 090H
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160 160 $DGS BEG_BLK, ??bb11_tsk_sys, U, U, 00H, 064H, 01H, 00H
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161 161 $DGS AUX_BEG, 0E5H, 00H, 096H
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162 162 $DGS END_BLK, ??eb11_tsk_sys, U, U, 00H, 064H, 01H, 00H
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163 163 $DGS AUX_END, 0EAH
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164 164 $DGS END_BLK, ??eb10_tsk_sys, U, U, 00H, 064H, 01H, 00H
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165 165 $DGS AUX_END, 0ECH
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166 166 $DGS BEG_BLK, ??bb12_tsk_sys, U, U, 00H, 064H, 01H, 00H
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167 167 $DGS AUX_BEG, 0EEH, 00H, 098H
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168 168 $DGS BEG_BLK, ??bb13_tsk_sys, U, U, 00H, 064H, 01H, 00H
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169 169 $DGS AUX_BEG, 0F2H, 00H, 09EH
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170 170 $DGS END_BLK, ??eb13_tsk_sys, U, U, 00H, 064H, 01H, 00H
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171 171 $DGS AUX_END, 0F2H
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172 172 $DGS END_BLK, ??eb12_tsk_sys, U, U, 00H, 064H, 01H, 00H
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173 173 $DGS AUX_END, 0110H
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174 174 $DGS BEG_BLK, ??bb14_tsk_sys, U, U, 00H, 064H, 01H, 00H
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175 175 $DGS AUX_BEG, 0114H, 00H, 00H
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176 176 $DGS END_BLK, ??eb14_tsk_sys, U, U, 00H, 064H, 01H, 00H
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177 177 $DGS AUX_END, 0117H
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178 178 $DGS END_BLK, ??eb00_tsk_sys, U, U, 00H, 064H, 01H, 00H
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179 179 $DGS AUX_END, 0119H
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180 180 $DGS END_FUN, ??ef_tsk_sys, U, U, 00H, 065H, 01H, 00H
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181 181 $DGS AUX_END, 011AH
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182 182 $DGS STA_SYM, _chk_emergencyExit, U, U, 01H, 03H, 01H, 02H
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183 183 $DGS AUX_FUN, 00H, U, U, 0C1H, 00H, 00H
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184 184 $DGS BEG_FUN, ??bf_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H
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185 185 $DGS AUX_BEG, 0143H, 00H, 0ABH
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186 186 $DGS STA_SYM, _state, ?L0048, U, 04H, 03H, 00H, 00H
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187 187 $DGS BEG_BLK, ??bb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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188 188 $DGS AUX_BEG, 06H, 00H, 0ADH
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189 189 $DGS BEG_BLK, ??bb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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190 190 $DGS AUX_BEG, 08H, 00H, 0B1H
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191 191 $DGS END_BLK, ??eb01_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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192 192 $DGS AUX_END, 0CH
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193 193 $DGS BEG_BLK, ??bb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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194 194 $DGS AUX_BEG, 0EH, 00H, 0B3H
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195 195 $DGS BEG_BLK, ??bb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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196 196 $DGS AUX_BEG, 010H, 00H, 0BBH
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197 197 $DGS END_BLK, ??eb03_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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198 198 $DGS AUX_END, 017H
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199 199 $DGS END_BLK, ??eb02_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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200 200 $DGS AUX_END, 018H
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201 201 $DGS END_BLK, ??eb00_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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202 202 $DGS AUX_END, 019H
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203 203 $DGS BEG_BLK, ??bb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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204 204 $DGS AUX_BEG, 01BH, 00H, 00H
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205 205 $DGS END_BLK, ??eb04_chk_emergencyExit, U, U, 00H, 064H, 01H, 00H
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206 206 $DGS AUX_END, 01DH
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207 207 $DGS END_FUN, ??ef_chk_emergencyExit, U, U, 00H, 065H, 01H, 00H
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208 208 $DGS AUX_END, 01FH
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209 209 $DGS GLV_SYM, _tski_firm_update, U, U, 0AH, 026H, 01H, 02H
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210 210 $DGS AUX_FUN, 041H, U, U, 0C7H, 00H, 00H
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211 211 $DGS BEG_FUN, ??bf_tski_firm_update, U, U, 00H, 065H, 01H, 00H
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212 212 $DGS AUX_BEG, 0181H, 00H, 0C7H
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213 213 $DGS END_FUN, ??ef_tski_firm_update, U, U, 00H, 065H, 01H, 00H
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214 214 $DGS AUX_END, 04H
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215 215 $DGS GLV_SYM, _iic_mcu_write_a_byte, U, U, 0CH, 02H, 01H, 02H
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216 216 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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217 217 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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218 218 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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219 219 $DGS GLV_SYM, _SW_pow_count, U, U, 0CH, 02H, 00H, 00H
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220 220 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H
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221 221 $DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H
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222 222 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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223 223 $DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H
|
||
224 224 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
225 225 $DGS GLV_SYM, _PM_sys_pow_on, U, U, 0CH, 02H, 01H, 02H
|
||
226 226 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
227 227 $DGS GLV_SYM, _iic_mcu_stop, U, U, 01H, 02H, 01H, 02H
|
||
228 228 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
229 229 $DGS GLV_SYM, _PM_LCD_vcom_set, U, U, 0CH, 02H, 01H, 02H
|
||
230 230 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
231 231 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
|
||
232 232 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
|
||
233 233 $DGS GLV_SYM, _LED_init, U, U, 01H, 02H, 01H, 02H
|
||
234 234 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
235 235 $DGS GLV_SYM, _IIC_ctr_Init, U, U, 01H, 02H, 01H, 02H
|
||
236 236 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
237 237 $DGS GLV_SYM, _set_irq, U, U, 01H, 02H, 01H, 02H
|
||
238 238 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
239 239 $DGS GLV_SYM, _IIC_twl_Init, U, U, 01H, 02H, 01H, 02H
|
||
240 240 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
241 241 $DGS GLV_SYM, _wait_ms, U, U, 01H, 02H, 01H, 02H
|
||
242 242 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
243 243 $DGS GLV_SYM, _LED_stop, U, U, 01H, 02H, 01H, 02H
|
||
244 244 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
245 245 $DGS GLV_SYM, _IIC_ctr_Stop, U, U, 01H, 02H, 01H, 02H
|
||
246 246 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
247 247 $DGS GLV_SYM, _IIC_twl_Stop, U, U, 01H, 02H, 01H, 02H
|
||
248 248 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
249 249 $DGS GLV_SYM, _PM_sys_pow_off, U, U, 0CH, 02H, 01H, 02H
|
||
250 250 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
251 251 $DGS GLV_SYM, _SW_wifi_count, U, U, 0CH, 02H, 00H, 00H
|
||
252 252 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
|
||
253 253 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
254 254 $DGS GLV_SYM, _do_command0, U, U, 0AH, 02H, 01H, 02H
|
||
255 255 $DGS AUX_FUN, 041H, U, U, 00H, 00H, 00H
|
||
256 256 $DGS GLV_SYM, _renge_task_immed_add, U, U, 0CH, 02H, 01H, 02H
|
||
257 257 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
258 258 $DGS GLV_SYM, _firm_update, U, U, 0CH, 02H, 01H, 02H
|
||
259 259 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
|
||
260 260
|
||
261 261 EXTRN _iic_mcu_write_a_byte
|
||
262 262 EXTRN _system_status
|
||
263 263 EXTRN _SW_pow_count
|
||
264 264 EXTRN _iic_mcu_start
|
||
265 265 EXTRN _PM_init
|
||
266 266 EXTRN _PM_sys_pow_on
|
||
267 267 EXTRN _iic_mcu_stop
|
||
268 268 EXTRN _PM_LCD_vcom_set
|
||
269 269 EXTRN _vreg_ctr
|
||
270 270 EXTRN _LED_init
|
||
271 271 EXTRN _IIC_ctr_Init
|
||
272 272 EXTRN _set_irq
|
||
273 273 EXTRN _IIC_twl_Init
|
||
274 274 EXTRN _wait_ms
|
||
275 275 EXTRN _LED_stop
|
||
276 276 EXTRN _IIC_ctr_Stop
|
||
277 277 EXTRN _IIC_twl_Stop
|
||
278 278 EXTRN _PM_sys_pow_off
|
||
279 279 EXTRN _SW_wifi_count
|
||
280 280 EXTRN _iic_mcu_read_a_byte
|
||
281 281 EXTRN _do_command0
|
||
282 282 EXTRN _renge_task_immed_add
|
||
283 283 EXTRN _firm_update
|
||
284 284 EXTBIT _renge_task_interval_run_force
|
||
285 285 PUBLIC _tsk_sys
|
||
286 286 PUBLIC _tski_firm_update
|
||
287 287
|
||
288 288 ----- @@BITS BSEG
|
||
289 289
|
||
290 290 ----- @@CNST CSEG MIRRORP
|
||
291 291 00000 01 _lpf_coeff: DB 01H ; 1
|
||
292 292 00001 02 DB 02H ; 2
|
||
293 293 00002 02 DB 02H ; 2
|
||
294 294 00003 03 DB 03H ; 3
|
||
295 295 00004 03 DB 03H ; 3
|
||
296 296 00005 02 DB 02H ; 2
|
||
297 297 00006 00 DB 00H ; 0
|
||
298 298 00007 FE DB 0FEH ; 254
|
||
299 299 00008 FB DB 0FBH ; 251
|
||
300 300 00009 F7 DB 0F7H ; 247
|
||
301 301 0000A F3 DB 0F3H ; 243
|
||
302 302 0000B F0 DB 0F0H ; 240
|
||
303 303 0000C F0 DB 0F0H ; 240
|
||
304 304 0000D F3 DB 0F3H ; 243
|
||
305 305 0000E FA DB 0FAH ; 250
|
||
306 306 0000F 04 DB 04H ; 4
|
||
307 307 00010 12 DB 012H ; 18
|
||
308 308 00011 25 DB 025H ; 37
|
||
309 309 00012 38 DB 038H ; 56
|
||
310 310 00013 4D DB 04DH ; 77
|
||
311 311 00014 5F DB 05FH ; 95
|
||
312 312 00015 6E DB 06EH ; 110
|
||
313 313 00016 77 DB 077H ; 119
|
||
314 314 00017 7A DB 07AH ; 122
|
||
315 315 00018 77 DB 077H ; 119
|
||
316 316 00019 6E DB 06EH ; 110
|
||
317 317 0001A 5F DB 05FH ; 95
|
||
318 318 0001B 4D DB 04DH ; 77
|
||
319 319 0001C 38 DB 038H ; 56
|
||
320 320 0001D 25 DB 025H ; 37
|
||
321 321 0001E 12 DB 012H ; 18
|
||
322 322 0001F 04 DB 04H ; 4
|
||
323 323 00020 FA DB 0FAH ; 250
|
||
324 324 00021 F3 DB 0F3H ; 243
|
||
325 325 00022 F0 DB 0F0H ; 240
|
||
326 326 00023 F0 DB 0F0H ; 240
|
||
327 327 00024 F3 DB 0F3H ; 243
|
||
328 328 00025 F7 DB 0F7H ; 247
|
||
329 329 00026 FB DB 0FBH ; 251
|
||
330 330 00027 FE DB 0FEH ; 254
|
||
331 331 00028 00 DB 00H ; 0
|
||
332 332 00029 02 DB 02H ; 2
|
||
333 333 0002A 03 DB 03H ; 3
|
||
334 334 0002B 03 DB 03H ; 3
|
||
335 335 0002C 02 DB 02H ; 2
|
||
336 336 0002D 02 DB 02H ; 2
|
||
337 337 0002E 01 DB 01H ; 1
|
||
338 338 0002F 00 DB (1)
|
||
339 339
|
||
340 340 ----- @@R_INIT CSEG UNIT64KP
|
||
341 341 00000 00 DB 00H ; 0
|
||
342 342 00001 00 DB (1)
|
||
343 343
|
||
344 344 ----- @@INIT DSEG BASEP
|
||
345 345 00000 ?L0003: DS (1)
|
||
346 346 00001 DS (1)
|
||
347 347
|
||
348 348 ----- @@DATA DSEG BASEP
|
||
349 349 00000 ?L0048: DS (2)
|
||
350 350
|
||
351 351 ----- @@R_INIS CSEG UNIT64KP
|
||
352 352
|
||
353 353 ----- @@INIS DSEG SADDRP
|
||
354 354
|
||
355 355 ----- @@DATS DSEG SADDRP
|
||
356 356
|
||
357 357 ----- @@CNSTL CSEG PAGE64KP
|
||
358 358
|
||
359 359 ----- @@RLINIT CSEG UNIT64KP
|
||
360 360
|
||
361 361 ----- @@INITL DSEG UNIT64KP
|
||
362 362
|
||
363 363 ----- @@DATAL DSEG UNIT64KP
|
||
364 364
|
||
365 365 ----- @@CALT CSEG CALLT0
|
||
366 366
|
||
367 367 ; Sub-Routines created by CC78K0R
|
||
368 368
|
||
369 369 ----- ROM_CODE CSEG BASE
|
||
370 370 00000 bs_F0057:
|
||
371 371 00000 C1 push ax ;[INF] 1, 1
|
||
372 372 00001 5005 mov x,#05H ; 5 ;[INF] 2, 1
|
||
373 373 00003 C1 push ax ;[INF] 1, 1
|
||
374 374 00004 5084 mov x,#084H ; 132 ;[INF] 2, 1
|
||
375 375 00006 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
|
||
376 376 00009 1004 addw sp,#04H ; 4 ;[INF] 2, 1
|
||
377 377 0000B D7 ret ;[INF] 1, 6
|
||
378 378 0000C es_F0057:
|
||
379 379
|
||
380 380 ; *** Sub-Routine Information ***
|
||
381 381 ;
|
||
382 382 ; $SUB bs_F0057
|
||
383 383 ; CODE SIZE= 12 bytes
|
||
384 384
|
||
385 385 ; End of Sub-Routines
|
||
386 386
|
||
387 387 ; line 1 : #pragma SFR
|
||
388 388 ; line 2 : #pragma NOP
|
||
389 389 ; line 3 : #pragma HALT
|
||
390 390 ; line 4 : #pragma STOP
|
||
391 391 ; line 5 :
|
||
392 392 ; line 6 : #include "incs.h"
|
||
393 393 ; line 7 :
|
||
394 394 ; line 8 : #include "i2c_twl.h"
|
||
395 395 ; line 9 : #include "i2c_ctr.h"
|
||
396 396 ; line 10 : #include "led.h"
|
||
397 397 ; line 11 : #include "accero.h"
|
||
398 398 ; line 12 : #include "pm.h"
|
||
399 399 ; line 13 : #include "rtc.h"
|
||
400 400 ; line 14 : #include "sw.h"
|
||
401 401 ; line 15 : #include "adc.h"
|
||
402 402 ; line 16 :
|
||
403 403 ; line 17 :
|
||
404 404 ; line 18 :
|
||
405 405 ; line 19 : //=========================================================
|
||
406 406 ; line 20 : static void chk_emergencyExit();
|
||
407 407 ; line 21 :
|
||
408 408 ; line 22 :
|
||
409 409 ; line 23 :
|
||
410 410 ; line 24 : //=========================================================
|
||
411 411 ; line 25 :
|
||
412 412 ; line 26 :
|
||
413 413 ; line 27 :
|
||
414 414 ; line 28 : /* ========================================================
|
||
415 415 ; line 29 : <20>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŕK<C595>v<EFBFBD>Ȃ<EFBFBD><C882><EFBFBD>
|
||
416 416 ; line 30 : <20>E<EFBFBD>ȓd<C893>͂ɓ<CD82><C993><EFBFBD><EFBFBD><EFBFBD>
|
||
417 417 ; line 31 : <20>@system_status.pwr_state == OFF_TRIG <20>ŁA<C581><41><EFBFBD>̃^<5E>X<EFBFBD>N<EFBFBD><4E><EFBFBD>Ă<C482><CE82><EFBFBD>
|
||
418 418 ; <20>ƁA
|
||
419 419 ; line 32 : <20>ȓd<C893>̓<EFBFBD><CD83>[<5B>h<EFBFBD>ɓ<EFBFBD><C993><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
420 420 ; line 33 : ======================================================== */
|
||
421 421 ; line 34 : void tsk_sys( )
|
||
422 422 ; line 35 : {
|
||
423 423
|
||
424 424 ----- ROM_CODE CSEG BASE
|
||
425 425 0000C _tsk_sys:
|
||
426 426 $DGL 1,75
|
||
427 427 0000C ??bf_tsk_sys:
|
||
428 428 ; line 36 : static u8 timeout = 0;
|
||
429 429 ; line 37 :
|
||
430 430 ; line 38 : switch ( system_status.pwr_state )
|
||
431 431 $DGL 0,4
|
||
432 432 0000C R8F0000 mov a,!_system_status ;[INF] 3, 1
|
||
433 433 0000F 318F sarw ax,8 ;[INF] 2, 1
|
||
434 434 00011 E7 onew bc ;[INF] 1, 1
|
||
435 435 00012 240000 subw ax,#00H ; 0 ;[INF] 3, 1
|
||
436 436 00015 61F8 sknz ;[INF] 2, 1
|
||
437 437 00017 RED1701 br !?L0010 ;[INF] 3, 3
|
||
438 438 0001A 23 subw ax,bc ;[INF] 1, 1
|
||
439 439 0001B DD1E bz $?L0005 ;[INF] 2, 4
|
||
440 440 0001D 23 subw ax,bc ;[INF] 1, 1
|
||
441 441 0001E DD7B bz $?L0006 ;[INF] 2, 4
|
||
442 442 00020 23 subw ax,bc ;[INF] 1, 1
|
||
443 443 00021 61F8 sknz ;[INF] 2, 1
|
||
444 444 00023 REDDA00 br !?L0007 ;[INF] 3, 3
|
||
445 445 00026 23 subw ax,bc ;[INF] 1, 1
|
||
446 446 00027 61F8 sknz ;[INF] 2, 1
|
||
447 447 00029 REDE900 br !?L0008 ;[INF] 3, 3
|
||
448 448 0002C 23 subw ax,bc ;[INF] 1, 1
|
||
449 449 0002D 61F8 sknz ;[INF] 2, 1
|
||
450 450 0002F REDF400 br !?L0009 ;[INF] 3, 3
|
||
451 451 00032 23 subw ax,bc ;[INF] 1, 1
|
||
452 452 00033 61F8 sknz ;[INF] 2, 1
|
||
453 453 00035 RED6C01 br !?L0011 ;[INF] 3, 3
|
||
454 454 00038 REDB901 br !?L0038 ;[INF] 3, 3
|
||
455 455 ; line 39 : {
|
||
456 456 0003B ??bb00_tsk_sys:
|
||
457 457 ; line 40 : case OFF: //-------------------------------
|
||
458 458 ; ------------------------
|
||
459 459 0003B ?L0005:
|
||
460 460 ; line 41 : // <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD>ȂǂŊ<C782><C58A>荞<EFBFBD>݂<EFBFBD><DD82><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>X<EFBFBD><58><EFBFBD>[<5B>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
461 461 ; <20><><EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD>ɗ<EFBFBD><C997>܂<EFBFBD><DC82>B
|
||
462 462 ; line 42 :
|
||
463 463 ; line 43 : #ifndef _PARRADIUM_
|
||
464 464 ; line 44 : switch ( system_status.poweron_reason )
|
||
465 465 $DGL 0,10
|
||
466 466 0003B R8F0100 mov a,!_system_status+1 ;[INF] 3, 1
|
||
467 467 0003E 318F sarw ax,8 ;[INF] 2, 1
|
||
468 468 00040 240200 subw ax,#02H ; 2 ;[INF] 3, 1
|
||
469 469 00043 DD26 bz $?L0015 ;[INF] 2, 4
|
||
470 470 ; line 45 : {
|
||
471 471 00045 ??bb01_tsk_sys:
|
||
472 472 ; line 46 : default:
|
||
473 473 ; line 47 : // <20>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>œd<C593><64>on
|
||
474 474 ; line 48 :
|
||
475 475 ; line 49 : if( SW_pow_count != 0 )
|
||
476 476 $DGL 0,15
|
||
477 477 00045 RD50000 cmp0 !_SW_pow_count ;[INF] 3, 1
|
||
478 478 00048 DD05 bz $?L0018 ;[INF] 2, 4
|
||
479 479 ; line 50 : {
|
||
480 480 0004A ??bb02_tsk_sys:
|
||
481 481 ; line 51 : timeout = 0;
|
||
482 482 $DGL 0,17
|
||
483 483 0004A RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
484 484 0004D ??eb02_tsk_sys:
|
||
485 485 ; line 52 : }
|
||
486 486 $DGL 0,18
|
||
487 487 0004D EF03 br $?L0019 ;[INF] 2, 3
|
||
488 488 0004F ?L0018:
|
||
489 489 ; line 53 : else
|
||
490 490 ; line 54 : {
|
||
491 491 0004F ??bb03_tsk_sys:
|
||
492 492 ; line 55 : timeout += 1;
|
||
493 493 $DGL 0,21
|
||
494 494 0004F RA00000 inc !?L0003 ; timeout ;[INF] 3, 2
|
||
495 495 00052 ??eb03_tsk_sys:
|
||
496 496 ; line 56 : }
|
||
497 497 00052 ?L0019:
|
||
498 498 ; line 57 : if( timeout > 127 )
|
||
499 499 $DGL 0,23
|
||
500 500 00052 R8F0000 mov a,!?L0003 ; timeout ;[INF] 3, 1
|
||
501 501 00055 01 addw ax,ax ;[INF] 1, 1
|
||
502 502 00056 DE07 bnc $?L0020 ;[INF] 2, 4
|
||
503 503 ; line 58 : {
|
||
504 504 00058 ??bb04_tsk_sys:
|
||
505 505 ; line 59 : system_status.pwr_state = OFF_TRIG; // <20>X<EFBFBD>C<EFBFBD>b
|
||
506 506 ; <20>`<60>̓m<CD83>C<EFBFBD>Y<EFBFBD><59><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD>Q<EFBFBD><51><EFBFBD>B
|
||
507 507 $DGL 0,25
|
||
508 508 00058 RF50000 clrb !_system_status ;[INF] 3, 1
|
||
509 509 ; line 60 : renge_task_interval_run_force = 1;
|
||
510 510 $DGL 0,26
|
||
511 511 0005B R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
512 512 ; line 61 : return;
|
||
513 513 $DGL 0,27
|
||
514 514 0005E D7 ret ;[INF] 1, 6
|
||
515 515 0005F ??eb04_tsk_sys:
|
||
516 516 ; line 62 : }
|
||
517 517 0005F ?L0020:
|
||
518 518 ; line 63 :
|
||
519 519 ; line 64 : if( SW_pow_count < 3 )
|
||
520 520 $DGL 0,30
|
||
521 521 0005F R40000003 cmp !_SW_pow_count,#03H ; 3 ;[INF] 4, 1
|
||
522 522 00063 61D8 sknc ;[INF] 2, 1
|
||
523 523 00065 REDBC01 br !?L0004 ;[INF] 3, 3
|
||
524 524 ; line 65 : {
|
||
525 525 00068 ??bb05_tsk_sys:
|
||
526 526 ; line 66 : // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>̗l<CC97>q<EFBFBD><71><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
527 527 ; line 67 : return;
|
||
528 528 00068 ??eb05_tsk_sys:
|
||
529 529 ; line 68 : }
|
||
530 530 ; line 69 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
531 531 ; line 70 : system_status.poweron_reason = PWSW;
|
||
532 532 $DGL 0,36
|
||
533 533 00068 RE50100 oneb !_system_status+1 ;[INF] 3, 1
|
||
534 534 ; line 71 : break;
|
||
535 535 ; line 72 :
|
||
536 536 ; line 73 : case ( RTC_ALARM ):
|
||
537 537 ; line 74 : break;
|
||
538 538 0006B ??eb01_tsk_sys:
|
||
539 539 ; line 75 : }
|
||
540 540 0006B ?L0015:
|
||
541 541 ; line 76 :
|
||
542 542 ; line 77 : timeout = 0;
|
||
543 543 $DGL 0,43
|
||
544 544 0006B RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
545 545 ; line 78 :
|
||
546 546 ; line 79 : // <20>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD> //
|
||
547 547 ; line 80 : iic_mcu_start( );
|
||
548 548 $DGL 0,46
|
||
549 549 0006E RFD0000 call !_iic_mcu_start ;[INF] 3, 3
|
||
550 550 ; line 81 :
|
||
551 551 ; line 82 : // <20><><EFBFBD>œd<C593>r<EFBFBD>c<EFBFBD><63>IC<49>̋N<CC8B><4E><EFBFBD>҂<EFBFBD><D282>E<EFBFBD>F<EFBFBD>C<EFBFBD>g<EFBFBD>Ȃǂ<C882><C782><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
552 552 ; line 83 : PM_init( ); // <20>d<EFBFBD>r<EFBFBD>c<EFBFBD><63>IC<49>̐ݒ<CC90>
|
||
553 553 $DGL 0,49
|
||
554 554 00071 RFD0000 call !_PM_init ;[INF] 3, 3
|
||
555 555 ; line 84 :
|
||
556 556 ; line 85 : if( PM_sys_pow_on( ) != ERR_SUCCESS )
|
||
557 557 $DGL 0,51
|
||
558 558 00074 RFD0000 call !_PM_sys_pow_on ;[INF] 3, 3
|
||
559 559 00077 D2 cmp0 c ;[INF] 1, 1
|
||
560 560 00078 DD0A bz $?L0024 ;[INF] 2, 4
|
||
561 561 ; line 86 : { // <20>d<EFBFBD><64><EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD>G<C283><47><EFBFBD>[
|
||
562 562 0007A ??bb06_tsk_sys:
|
||
563 563 ; line 87 : renge_task_interval_run_force = 1;
|
||
564 564 $DGL 0,53
|
||
565 565 0007A R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
566 566 ; line 88 : iic_mcu_stop( );
|
||
567 567 $DGL 0,54
|
||
568 568 0007D RFD0000 call !_iic_mcu_stop ;[INF] 3, 3
|
||
569 569 ; line 89 : system_status.pwr_state = OFF_TRIG;
|
||
570 570 $DGL 0,55
|
||
571 571 00080 RF50000 clrb !_system_status ;[INF] 3, 1
|
||
572 572 ; line 90 : return;
|
||
573 573 $DGL 0,56
|
||
574 574 00083 D7 ret ;[INF] 1, 6
|
||
575 575 00084 ??eb06_tsk_sys:
|
||
576 576 ; line 91 : }
|
||
577 577 00084 ?L0024:
|
||
578 578 ; line 92 : PM_CHG_TIMEOUT_ENABLE();
|
||
579 579 ; line 93 : // IRQ0_active;
|
||
580 580 ; line 94 :
|
||
581 581 ; line 95 : #else
|
||
582 582 ; line 96 : vreg_ctr[ VREG_C_STATUS_1 ] |= REG_BIT_GASGAUGE_ERR;
|
||
583 583 ; line 97 : system_status.poweron_reason = PWSW;
|
||
584 584 ; line 98 : #endif // _PARADDIUM_
|
||
585 585 ; line 99 :
|
||
586 586 ; line 100 : PM_LCD_vcom_set( ); // LCD<43>̑Ό<CC91><CE8C>d<EFBFBD><64><EFBFBD>l<EFBFBD>ȂǏ<C882><C78F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
587 587 $DGL 0,66
|
||
588 588 00084 RFD0000 call !_PM_LCD_vcom_set ;[INF] 3, 3
|
||
589 589 ; line 101 : #ifdef _PMIC_TWL_
|
||
590 590 ; line 102 : PM_TEG_LCD_dis( 0 );
|
||
591 591 ; line 103 : #endif
|
||
592 592 ; line 104 :
|
||
593 593 ; line 105 : if( system_status.poweron_reason == PWSW )
|
||
594 594 $DGL 0,71
|
||
595 595 00087 R40010001 cmp !_system_status+1,#01H ; 1 ;[INF] 4, 1
|
||
596 596 0008B DF05 bnz $?L0026 ;[INF] 2, 4
|
||
597 597 ; line 106 : {
|
||
598 598 0008D ??bb07_tsk_sys:
|
||
599 599 ; line 107 : // <20>d<EFBFBD><64><EFBFBD>{<7B>^<5E><><EFBFBD>ł<EFBFBD>on<6F>̎<EFBFBD><CC8E>́ALED<45><44><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
600 600 ; line 108 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_AUTO;
|
||
601 601 $DGL 0,74
|
||
602 602 0008D RF52900 clrb !_vreg_ctr+41 ;[INF] 3, 1
|
||
603 603 00090 ??eb07_tsk_sys:
|
||
604 604 ; line 109 : }
|
||
605 605 $DGL 0,75
|
||
606 606 00090 EF04 br $?L0027 ;[INF] 2, 3
|
||
607 607 00092 ?L0026:
|
||
608 608 ; line 110 : else
|
||
609 609 ; line 111 : {
|
||
610 610 00092 ??bb08_tsk_sys:
|
||
611 611 ; line 112 : // <20>Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>ALED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԂŋN<C58B><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
612 612 ; line 113 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF;
|
||
613 613 $DGL 0,79
|
||
614 614 00092 RCF290003 mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1
|
||
615 615 00096 ??eb08_tsk_sys:
|
||
616 616 ; line 114 : // todo?
|
||
617 617 ; line 115 : }
|
||
618 618 00096 ?L0027:
|
||
619 619 ; line 116 : system_status.pwr_state = ON_TRIG;
|
||
620 620 $DGL 0,82
|
||
621 621 00096 RCF000002 mov !_system_status,#02H ; 2 ;[INF] 4, 1
|
||
622 622 ; line 117 : // <20><><EFBFBD><EFBFBD><EFBFBD>܂ŗ<DC82><C597><EFBFBD><EFBFBD>ƁA<C681>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>m<EFBFBD><6D>
|
||
623 623 ; line 118 : break;
|
||
624 624 $DGL 0,84
|
||
625 625 0009A D7 ret ;[INF] 1, 6
|
||
626 626 ; line 119 :
|
||
627 627 ; line 120 : case ON_TRIG: //-------------------------------
|
||
628 628 ; ------------------------
|
||
629 629 0009B ?L0006:
|
||
630 630 ; line 121 :
|
||
631 631 ; line 122 : LED_init( );
|
||
632 632 $DGL 0,88
|
||
633 633 0009B RFD0000 call !_LED_init ;[INF] 3, 3
|
||
634 634 ; line 123 :
|
||
635 635 ; line 124 : PU7 = 0b00011101; // 4:SW_WIFI 3:SW_PWSW 2:PM_IRQ 0:PM_
|
||
636 636 ; EXTDC_n
|
||
637 637 $DGL 0,90
|
||
638 638 0009E CF37001D mov !PU7,#01DH ; 29 ;[INF] 4, 1
|
||
639 639 ; line 125 :
|
||
640 640 ; line 126 : IIC_ctr_Init( );
|
||
641 641 $DGL 0,92
|
||
642 642 000A2 RFD0000 call !_IIC_ctr_Init ;[INF] 3, 3
|
||
643 643 ; line 127 : if( ( vreg_ctr[ VREG_C_MCU_STATUS ] & REG_BIT_STATUS_WDT
|
||
644 644 ; _RESET )
|
||
645 645 ; line 128 : /*
|
||
646 646 ; line 129 : if( vreg_ctr[ VREG_C_IRQ0 ]
|
||
647 647 ; line 130 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
648 648 ; line 131 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
649 649 ; line 132 : | vreg_ctr[ VREG_C_IRQ0 ]
|
||
650 650 ; line 133 : */
|
||
651 651 ; line 134 : != 0 )
|
||
652 652 $DGL 0,100
|
||
653 653 000A5 R8F0200 mov a,!_vreg_ctr+2 ;[INF] 3, 1
|
||
654 654 000A8 5C02 and a,#02H ; 2 ;[INF] 2, 1
|
||
655 655 000AA D1 cmp0 a ;[INF] 1, 1
|
||
656 656 000AB DD0A bz $?L0028 ;[INF] 2, 4
|
||
657 657 ; line 135 : {
|
||
658 658 000AD ??bb09_tsk_sys:
|
||
659 659 ; line 136 : set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
|
||
660 660 $DGL 0,102
|
||
661 661 000AD 308000 movw ax,#080H ; 128 ;[INF] 3, 1
|
||
662 662 000B0 C1 push ax ;[INF] 1, 1
|
||
663 663 000B1 5010 mov x,#010H ; 16 ;[INF] 2, 1
|
||
664 664 000B3 RFD0000 call !_set_irq ;[INF] 3, 3
|
||
665 665 000B6 C0 pop ax ;[INF] 1, 1
|
||
666 666 000B7 ??eb09_tsk_sys:
|
||
667 667 ; line 137 : }
|
||
668 668 000B7 ?L0028:
|
||
669 669 ; line 138 : IIC_twl_Init( );
|
||
670 670 $DGL 0,104
|
||
671 671 000B7 RFD0000 call !_IIC_twl_Init ;[INF] 3, 3
|
||
672 672 ; line 139 : RTC_32k_on( );
|
||
673 673 $DGL 0,105
|
||
674 674 000BA ??bb0A_tsk_sys:
|
||
675 675 000BA 714A9D set1 RTCC0.4 ;[INF] 3, 2
|
||
676 676 000BD ??eb0A_tsk_sys:
|
||
677 677 ; line 140 :
|
||
678 678 ; line 141 : KRM = 0b00000000;
|
||
679 679 $DGL 0,107
|
||
680 680 000BD F537FF clrb !KRM ;[INF] 3, 1
|
||
681 681 ; line 142 :
|
||
682 682 ; line 143 : system_status.poweron_reason = NONE;
|
||
683 683 $DGL 0,109
|
||
684 684 000C0 RF50100 clrb !_system_status+1 ;[INF] 3, 1
|
||
685 685 ; line 144 : renge_task_interval_run_force = 1;
|
||
686 686 $DGL 0,110
|
||
687 687 000C3 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
688 688 ; line 145 :
|
||
689 689 ; line 146 : MK0 = INT_MSK0_RSV;
|
||
690 690 $DGL 0,112
|
||
691 691 000C6 CBE43FEF movw MK0,#0EF3FH ; -4289 ;[INF] 4, 1
|
||
692 692 ; line 147 : MK1 = INT_MSK1_RSV;
|
||
693 693 $DGL 0,113
|
||
694 694 000CA CBE6F6F0 movw MK1,#0F0F6H ; -3850 ;[INF] 4, 1
|
||
695 695 ; line 148 : #ifdef _MCU_BSR_
|
||
696 696 ; line 149 : // MK2 = ~( INT_MSK2_IIC_TWL | INT_MSK2_WIFI_TX_BSR | INT
|
||
697 697 ; _MSK2_CODEC_PMIRQ );
|
||
698 698 ; line 150 : // PMK21 = 0; // wifi <20>g<EFBFBD><67><EFBFBD>Ȃ<EFBFBD>
|
||
699 699 ; line 151 : PMK6 = 0; // pm_irq
|
||
700 700 $DGL 0,117
|
||
701 701 000CE 713BD4 clr1 MK2L.3 ;[INF] 3, 2
|
||
702 702 ; line 152 : #else
|
||
703 703 ; line 153 : MK2L = ~INT_MSK2_WIFI_TX_KE3;
|
||
704 704 ; line 154 : #endif
|
||
705 705 ; line 155 :
|
||
706 706 ; line 156 : system_status.reboot = 0;
|
||
707 707 $DGL 0,122
|
||
708 708 000D1 R71380200 clr1 !_system_status+2.3 ;[INF] 4, 2
|
||
709 709 ; line 157 : system_status.pwr_state = ON;
|
||
710 710 $DGL 0,123
|
||
711 711 000D5 RCF000003 mov !_system_status,#03H ; 3 ;[INF] 4, 1
|
||
712 712 ; line 158 : break;
|
||
713 713 $DGL 0,124
|
||
714 714 000D9 D7 ret ;[INF] 1, 6
|
||
715 715 ; line 159 :
|
||
716 716 ; line 160 : case ON: //-------------------------------
|
||
717 717 ; --------------
|
||
718 718 000DA ?L0007:
|
||
719 719 ; line 161 : // PMIC<49>ɂ<EFBFBD><C982>鋭<EFBFBD><E98BAD><EFBFBD>d<EFBFBD><64><EFBFBD>f<EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N
|
||
720 720 ; line 162 : // <20>f<EFBFBD>o<EFBFBD>b<EFBFBD>K<EFBFBD><4B>reset1<74><31><EFBFBD>A<EFBFBD>T<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>邱<EFBFBD>Ƃ<EFBFBD><C682><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD>̂Ƃ<CC82><C682>͑S
|
||
721 721 ; <20><><EFBFBD><EFBFBD><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
722 722 ; line 163 : chk_emergencyExit();
|
||
723 723 $DGL 0,129
|
||
724 724 000DA RFDBD01 call !_chk_emergencyExit ;[INF] 3, 3
|
||
725 725 ; line 164 :
|
||
726 726 ; line 165 : // SLP<4C>Ď<EFBFBD>
|
||
727 727 ; line 166 : if( SLP_REQ ){
|
||
728 728 $DGL 0,132
|
||
729 729 000DD 31040C07 bf P12.0,$?L0030 ;[INF] 4, 5
|
||
730 730 000E1 ??bb0B_tsk_sys:
|
||
731 731 ; line 167 : system_status.pwr_state = SLEEP_TRIG;
|
||
732 732 $DGL 0,133
|
||
733 733 000E1 RCF000004 mov !_system_status,#04H ; 4 ;[INF] 4, 1
|
||
734 734 ; line 168 : renge_task_interval_run_force = 1;
|
||
735 735 $DGL 0,134
|
||
736 736 000E5 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
737 737 000E8 ??eb0B_tsk_sys:
|
||
738 738 ; line 169 : }
|
||
739 739 000E8 ?L0030:
|
||
740 740 ; line 170 : break;
|
||
741 741 $DGL 0,136
|
||
742 742 000E8 D7 ret ;[INF] 1, 6
|
||
743 743 ; line 171 :
|
||
744 744 ; line 172 : case SLEEP_TRIG: //-------------------------------
|
||
745 745 ; ------
|
||
746 746 000E9 ?L0008:
|
||
747 747 ; line 173 : PM_VDD_ecoMode();
|
||
748 748 $DGL 0,139
|
||
749 749 000E9 302700 movw ax,#027H ; 39 ;[INF] 3, 1
|
||
750 750 000EC RFD0000 call !bs_F0057 ;[INF] 3, 3
|
||
751 751 ; line 174 : system_status.pwr_state = SLEEP;
|
||
752 752 $DGL 0,140
|
||
753 753 000EF RCF000005 mov !_system_status,#05H ; 5 ;[INF] 4, 1
|
||
754 754 ; line 175 : break;
|
||
755 755 $DGL 0,141
|
||
756 756 000F3 D7 ret ;[INF] 1, 6
|
||
757 757 ; line 176 :
|
||
758 758 ; line 177 : case SLEEP: //-------------------------------
|
||
759 759 ; -----------
|
||
760 760 000F4 ?L0009:
|
||
761 761 ; line 178 : chk_emergencyExit();
|
||
762 762 $DGL 0,144
|
||
763 763 000F4 RFDBD01 call !_chk_emergencyExit ;[INF] 3, 3
|
||
764 764 ; line 179 : // <20>X<EFBFBD><58><EFBFBD>[<5B>v<EFBFBD><76><EFBFBD>畜<EFBFBD>A
|
||
765 765 ; line 180 : if( !SLP_REQ ){
|
||
766 766 $DGL 0,146
|
||
767 767 000F7 31020C1B bt P12.0,$?L0032 ;[INF] 4, 5
|
||
768 768 000FB ??bb0C_tsk_sys:
|
||
769 769 ; line 181 : PM_VDD_normMode();
|
||
770 770 $DGL 0,147
|
||
771 771 000FB F6 clrw ax ;[INF] 1, 1
|
||
772 772 000FC RFD0000 call !bs_F0057 ;[INF] 3, 3
|
||
773 773 ; line 182 : wait_ms( 5 ); // tdly_sw
|
||
774 774 $DGL 0,148
|
||
775 775 000FF 300500 movw ax,#05H ; 5 ;[INF] 3, 1
|
||
776 776 00102 RFD0000 call !_wait_ms ;[INF] 3, 3
|
||
777 777 ; line 183 :
|
||
778 778 ; line 184 : #ifdef _MODEL_CTR_
|
||
779 779 ; line 185 : SLP_ACK = 1;
|
||
780 780 $DGL 0,151
|
||
781 781 00105 717207 set1 P7.7 ;[INF] 3, 2
|
||
782 782 ; line 186 : NOP(); // <20>K<EFBFBD><4B><EFBFBD>E<EFBFBD>F<EFBFBD>C<EFBFBD>g
|
||
783 783 $DGL 0,152
|
||
784 784 00108 00 nop ;[INF] 1, 1
|
||
785 785 ; line 187 : NOP();
|
||
786 786 $DGL 0,153
|
||
787 787 00109 00 nop ;[INF] 1, 1
|
||
788 788 ; line 188 : NOP();
|
||
789 789 $DGL 0,154
|
||
790 790 0010A 00 nop ;[INF] 1, 1
|
||
791 791 ; line 189 : NOP();
|
||
792 792 $DGL 0,155
|
||
793 793 0010B 00 nop ;[INF] 1, 1
|
||
794 794 ; line 190 : SLP_ACK = 0;
|
||
795 795 $DGL 0,156
|
||
796 796 0010C 717307 clr1 P7.7 ;[INF] 3, 2
|
||
797 797 ; line 191 : #endif
|
||
798 798 ; line 192 :
|
||
799 799 ; line 193 : system_status.pwr_state = ON_TRIG;
|
||
800 800 $DGL 0,159
|
||
801 801 0010F RCF000002 mov !_system_status,#02H ; 2 ;[INF] 4, 1
|
||
802 802 ; line 194 : renge_task_interval_run_force = 1;
|
||
803 803 $DGL 0,160
|
||
804 804 00113 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
805 805 00116 ??eb0C_tsk_sys:
|
||
806 806 ; line 195 : }
|
||
807 807 00116 ?L0032:
|
||
808 808 ; line 196 :
|
||
809 809 ; line 197 : break;
|
||
810 810 $DGL 0,163
|
||
811 811 00116 D7 ret ;[INF] 1, 6
|
||
812 812 ; line 198 :
|
||
813 813 ; line 199 : case OFF_TRIG: //-------------------------------
|
||
814 814 ; --------
|
||
815 815 00117 ?L0010:
|
||
816 816 ; line 200 : // LED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>҂<EFBFBD>
|
||
817 817 ; line 201 : vreg_ctr[VREG_C_LED_POW] = LED_POW_ILM_OFF;
|
||
818 818 $DGL 0,167
|
||
819 819 00117 RCF290003 mov !_vreg_ctr+41,#03H ; 3 ;[INF] 4, 1
|
||
820 820 ; line 202 : if(( LED_duty_pow_H != 0 ) || ( LED_duty_pow_L != 0 ))
|
||
821 821 $DGL 0,168
|
||
822 822 0011B F6 clrw ax ;[INF] 1, 1
|
||
823 823 0011C 426CFF cmpw ax,!TDR06 ;[INF] 3, 1
|
||
824 824 0011F DF05 bnz $?L0036 ;[INF] 2, 4
|
||
825 825 00121 426EFF cmpw ax,!TDR07 ;[INF] 3, 1
|
||
826 826 00124 61E8 skz ;[INF] 2, 1
|
||
827 827 00126 ?L0036:
|
||
828 828 ; line 203 : {
|
||
829 829 00126 ??bb0D_tsk_sys:
|
||
830 830 ; line 204 : return;
|
||
831 831 $DGL 0,170
|
||
832 832 00126 D7 ret ;[INF] 1, 6
|
||
833 833 00127 ??eb0D_tsk_sys:
|
||
834 834 ; line 205 : }
|
||
835 835 00127 ?L0034:
|
||
836 836 ; line 206 :
|
||
837 837 ; line 207 : PM_CHG_TIMEOUT_ENABLE();
|
||
838 838 ; line 208 : LED_stop( );
|
||
839 839 $DGL 0,174
|
||
840 840 00127 RFD0000 call !_LED_stop ;[INF] 3, 3
|
||
841 841 ; line 209 : IIC_ctr_Stop( );
|
||
842 842 $DGL 0,175
|
||
843 843 0012A RFD0000 call !_IIC_ctr_Stop ;[INF] 3, 3
|
||
844 844 ; line 210 : IIC_twl_Stop( );
|
||
845 845 $DGL 0,176
|
||
846 846 0012D RFD0000 call !_IIC_twl_Stop ;[INF] 3, 3
|
||
847 847 ; line 211 : RTC_32k_off();
|
||
848 848 $DGL 0,177
|
||
849 849 00130 ??bb0E_tsk_sys:
|
||
850 850 00130 714B9D clr1 RTCC0.4 ;[INF] 3, 2
|
||
851 851 00133 ??eb0E_tsk_sys:
|
||
852 852 ; line 212 :
|
||
853 853 ; line 213 : vreg_ctr[VREG_C_IRQ0] = 0;
|
||
854 854 $DGL 0,179
|
||
855 855 00133 RF51000 clrb !_vreg_ctr+16 ;[INF] 3, 1
|
||
856 856 ; line 214 : vreg_ctr[VREG_C_IRQ1] = 0;
|
||
857 857 $DGL 0,180
|
||
858 858 00136 RF51100 clrb !_vreg_ctr+17 ;[INF] 3, 1
|
||
859 859 ; line 215 : vreg_ctr[VREG_C_IRQ2] = 0;
|
||
860 860 $DGL 0,181
|
||
861 861 00139 RF51200 clrb !_vreg_ctr+18 ;[INF] 3, 1
|
||
862 862 ; line 216 : vreg_ctr[VREG_C_IRQ3] = 0;
|
||
863 863 $DGL 0,182
|
||
864 864 0013C RF51300 clrb !_vreg_ctr+19 ;[INF] 3, 1
|
||
865 865 ; line 217 :
|
||
866 866 ; line 218 : // <20>d<EFBFBD><64><EFBFBD>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̊<EFBFBD><CC8A>荞<EFBFBD>݃Z<DD83>b<EFBFBD>g
|
||
867 867 ; line 219 : // PWSW KR3 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>L
|
||
868 868 ; line 220 : // BG24 KR4
|
||
869 869 ; line 221 : // <20>ӂ<EFBFBD><D382>J<EFBFBD><4A> INTP5 <20><EFBFBD><C282><EFBFBD><EFBFBD><EFBFBD>L
|
||
870 870 ; line 222 : // AC<41>A<EFBFBD>_<EFBFBD>v<EFBFBD>^ INTP4 <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>L
|
||
871 871 ; line 223 : // RTC
|
||
872 872 ; line 224 :
|
||
873 873 ; line 225 : #ifdef _PMIC_TWL_
|
||
874 874 ; line 226 : PM_TEG_LCD_dis( 1 );
|
||
875 875 ; line 227 : #endif
|
||
876 876 ; line 228 : // IRQ0_deactive;
|
||
877 877 ; line 229 : // pullup_off(); <20><>
|
||
878 878 ; line 230 : {
|
||
879 879 0013F ??bb0F_tsk_sys:
|
||
880 880 ; line 231 : PU5 = 0b00000011; // PM_CHG,PM_CHGERR
|
||
881 881 $DGL 0,197
|
||
882 882 0013F CF350003 mov !PU5,#03H ; 3 ;[INF] 4, 1
|
||
883 883 ; line 232 : PU7 = 0b00011001; // SW_WiFi,PWSWI,PM_EXTTDC
|
||
884 884 $DGL 0,198
|
||
885 885 00143 CF370019 mov !PU7,#019H ; 25 ;[INF] 4, 1
|
||
886 886 00147 ??eb0F_tsk_sys:
|
||
887 887 ; line 233 : }
|
||
888 888 ; line 234 :
|
||
889 889 ; line 235 : PM_sys_pow_off( );
|
||
890 890 $DGL 0,201
|
||
891 891 00147 RFD0000 call !_PM_sys_pow_off ;[INF] 3, 3
|
||
892 892 ; line 236 :
|
||
893 893 ; line 237 : KRM = ( KR_SW_POW ); // Mask <20>ł͂Ȃ<CD82><C882>AMode<64>Ȃ̂<C882><CC82><EFBFBD><EFBFBD><EFBFBD>
|
||
894 894 ; <20><><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>킵<EFBFBD><ED82B5>
|
||
895 895 $DGL 0,203
|
||
896 896 0014A CE3708 mov KRM,#08H ; 8 ;[INF] 3, 1
|
||
897 897 ; line 238 : // intp20<32>n<EFBFBD>͌<EFBFBD><CD8C>ق<EFBFBD>
|
||
898 898 ; line 239 : MK0 = ~( INT_MSK0_EXTDC );
|
||
899 899 $DGL 0,205
|
||
900 900 0014D CBE4BFFF movw MK0,#0FFBFH ; -65 ;[INF] 4, 1
|
||
901 901 ; line 240 : MK1 = ~( INT_MSK1_KR | INT_MSK1_RTCALARM | INT_MSK1_RTCI
|
||
902 902 ; NTVAL );
|
||
903 903 $DGL 0,206
|
||
904 904 00151 CBE6FFF1 movw MK1,#0F1FFH ; -3585 ;[INF] 4, 1
|
||
905 905 ; line 241 : MK2L = 0b11111111;
|
||
906 906 $DGL 0,207
|
||
907 907 00155 CED4FF mov MK2L,#0FFH ; 255 ;[INF] 3, 1
|
||
908 908 ; line 242 :
|
||
909 909 ; line 243 : IF0 = 0;
|
||
910 910 $DGL 0,209
|
||
911 911 00158 F6 clrw ax ;[INF] 1, 1
|
||
912 912 00159 BEE0 movw IF0,ax ;[INF] 2, 1
|
||
913 913 ; line 244 : IF1 = 0;
|
||
914 914 $DGL 0,210
|
||
915 915 0015B BEE2 movw IF1,ax ;[INF] 2, 1
|
||
916 916 ; line 245 : IF2 = 0;
|
||
917 917 $DGL 0,211
|
||
918 918 0015D BED0 movw IF2,ax ;[INF] 2, 1
|
||
919 919 ; line 246 :
|
||
920 920 ; line 247 : timeout = 0;
|
||
921 921 $DGL 0,213
|
||
922 922 0015F RF50000 clrb !?L0003 ; timeout ;[INF] 3, 1
|
||
923 923 ; line 248 :
|
||
924 924 ; line 249 : system_status.pwr_state = BT_CHARGE;
|
||
925 925 $DGL 0,215
|
||
926 926 00162 RCF000006 mov !_system_status,#06H ; 6 ;[INF] 4, 1
|
||
927 927 ; line 250 : SW_pow_count = 0;
|
||
928 928 $DGL 0,216
|
||
929 929 00166 RF50000 clrb !_SW_pow_count ;[INF] 3, 1
|
||
930 930 ; line 251 : SW_wifi_count = 0;
|
||
931 931 $DGL 0,217
|
||
932 932 00169 RF50000 clrb !_SW_wifi_count ;[INF] 3, 1
|
||
933 933 ; line 252 : // no break //
|
||
934 934 ; line 253 :
|
||
935 935 ; line 254 : case BT_CHARGE:
|
||
936 936 0016C ?L0011:
|
||
937 937 ; line 255 : if( !PM_EXTDC_n )
|
||
938 938 $DGL 0,221
|
||
939 939 0016C 3102071F bt P7.0,$?L0037 ;[INF] 4, 5
|
||
940 940 ; line 256 : {
|
||
941 941 00170 ??bb10_tsk_sys:
|
||
942 942 ; line 257 : // <20>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E>L<EFBFBD><4C><EFBFBD>F<EFBFBD>[<5B>d<EFBFBD><64><EFBFBD>x<EFBFBD>Ď<EFBFBD>
|
||
943 943 ; line 258 : BT_TEMP_P = 1;
|
||
944 944 $DGL 0,224
|
||
945 945 00170 717201 set1 P1.7 ;[INF] 3, 2
|
||
946 946 ; line 259 :
|
||
947 947 ; line 260 : // <20>d<EFBFBD><64>on<6F>H
|
||
948 948 ; line 261 : if( ( SW_pow_count > 3 ) || ( SW_wifi_count > 3 )
|
||
949 949 ; line 262 : || ( system_status.poweron_reason == RTC_ALARM )
|
||
950 950 ; )
|
||
951 951 $DGL 0,228
|
||
952 952 00173 R40000004 cmp !_SW_pow_count,#04H ; 4 ;[INF] 4, 1
|
||
953 953 00177 DE0C bnc $?L0041 ;[INF] 2, 4
|
||
954 954 00179 R40000004 cmp !_SW_wifi_count,#04H ; 4 ;[INF] 4, 1
|
||
955 955 0017D DE06 bnc $?L0041 ;[INF] 2, 4
|
||
956 956 0017F R40010002 cmp !_system_status+1,#02H ; 2 ;[INF] 4, 1
|
||
957 957 00183 DF37 bnz $?L0004 ;[INF] 2, 4
|
||
958 958 00185 ?L0041:
|
||
959 959 ; line 263 : {
|
||
960 960 00185 ??bb11_tsk_sys:
|
||
961 961 ; line 264 : system_status.pwr_state = OFF; // <20><EFBFBD><E18AB1><EFBFBD>R<EFBFBD>L<EFBFBD>邪
|
||
962 962 ; ...
|
||
963 963 $DGL 0,230
|
||
964 964 00185 RE50000 oneb !_system_status ;[INF] 3, 1
|
||
965 965 ; line 265 : renge_task_interval_run_force = 1;
|
||
966 966 $DGL 0,231
|
||
967 967 00188 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
968 968 ; line 266 : KRMK = 1;
|
||
969 969 $DGL 0,232
|
||
970 970 0018B 713AE7 set1 MK1H.3 ;[INF] 3, 2
|
||
971 971 ; line 267 : return;
|
||
972 972 $DGL 0,233
|
||
973 973 0018E D7 ret ;[INF] 1, 6
|
||
974 974 0018F ??eb11_tsk_sys:
|
||
975 975 ; line 268 : }
|
||
976 976 ; line 269 : return;
|
||
977 977 0018F ??eb10_tsk_sys:
|
||
978 978 ; line 270 : }
|
||
979 979 0018F ?L0037:
|
||
980 980 ; line 271 : else
|
||
981 981 ; line 272 : {
|
||
982 982 0018F ??bb12_tsk_sys:
|
||
983 983 ; line 273 : // <20>ȓd<C893>͂ֈڍs
|
||
984 984 ; line 274 : BT_TEMP_P = 0;
|
||
985 985 $DGL 0,240
|
||
986 986 0018F 717301 clr1 P1.7 ;[INF] 3, 2
|
||
987 987 ; line 275 : while( RWST )
|
||
988 988 $DGL 0,241
|
||
989 989 00192 ?L0042:
|
||
990 990 00192 31949E02 bf RTCC1.1,$?L0043 ;[INF] 4, 5
|
||
991 991 ; line 276 : {;}
|
||
992 992 $DGL 0,242
|
||
993 993 00196 ??bb13_tsk_sys:
|
||
994 994 00196 ??eb13_tsk_sys:
|
||
995 995 00196 EFFA br $?L0042 ;[INF] 2, 3
|
||
996 996 00198 ?L0043:
|
||
997 997 ; line 277 :
|
||
998 998 ; line 278 : iic_mcu_stop( );
|
||
999 999 $DGL 0,244
|
||
1000 1000 00198 RFD0000 call !_iic_mcu_stop ;[INF] 3, 3
|
||
1001 1001 ; line 279 :
|
||
1002 1002 ; line 280 : // <20><><EFBFBD>荞<EFBFBD>ݑ҂<DD91><D282>ŐQ<C590><51> //
|
||
1003 1003 ; line 281 : RTCIMK = 1;
|
||
1004 1004 $DGL 0,247
|
||
1005 1005 0019B 712AE7 set1 MK1H.2 ;[INF] 3, 2
|
||
1006 1006 ; line 282 : #ifndef _PARRADIUM_
|
||
1007 1007 ; line 283 :
|
||
1008 1008 ; line 284 : #ifdef _MCU_BSR_
|
||
1009 1009 ; line 285 : CKC = 0b00001001;
|
||
1010 1010 $DGL 0,251
|
||
1011 1011 0019E CEA409 mov CKC,#09H ; 9 ;[INF] 3, 1
|
||
1012 1012 ; line 286 : OSMC = 0x00;
|
||
1013 1013 $DGL 0,252
|
||
1014 1014 001A1 F5F300 clrb !OSMC ;[INF] 3, 1
|
||
1015 1015 ; line 287 : #endif
|
||
1016 1016 ; line 288 : STOP( );
|
||
1017 1017 $DGL 0,254
|
||
1018 1018 001A4 61FD stop ;[INF] 2, 3
|
||
1019 1019 ; line 289 : #ifdef _MCU_BSR_
|
||
1020 1020 ; line 290 : OSMC = 0x01;
|
||
1021 1021 $DGL 0,256
|
||
1022 1022 001A6 E5F300 oneb !OSMC ;[INF] 3, 1
|
||
1023 1023 ; line 291 : CKC = 0b00001000;
|
||
1024 1024 $DGL 0,257
|
||
1025 1025 001A9 CEA408 mov CKC,#08H ; 8 ;[INF] 3, 1
|
||
1026 1026 ; line 292 : #endif
|
||
1027 1027 ; line 293 :
|
||
1028 1028 ; line 294 : #endif
|
||
1029 1029 ; line 295 : RTCIMK = 0;
|
||
1030 1030 $DGL 0,261
|
||
1031 1031 001AC 712BE7 clr1 MK1H.2 ;[INF] 3, 2
|
||
1032 1032 ; line 296 : // <20>N<EFBFBD><4E><EFBFBD><EFBFBD> //
|
||
1033 1033 ; line 297 :
|
||
1034 1034 ; line 298 : // <20>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
1035 1035 ; line 299 : // <20>EKeyReturn<72><6E><EFBFBD>荞<EFBFBD>݁i<DD81>d<EFBFBD><64><EFBFBD>{<7B><><EFBFBD><EFBFBD><EFBFBD>j
|
||
1036 1036 ; line 300 : // <20>ERTC<54>A<EFBFBD><41><EFBFBD>[<5B><>
|
||
1037 1037 ; line 301 : // <20>E<EFBFBD>A<EFBFBD>_<EFBFBD>v<EFBFBD>^<5E>}<7D><>
|
||
1038 1038 ; line 302 : system_status.pwr_state = OFF; //
|
||
1039 1039 $DGL 0,268
|
||
1040 1040 001AF RE50000 oneb !_system_status ;[INF] 3, 1
|
||
1041 1041 ; line 303 : renge_task_interval_run_force = 1;
|
||
1042 1042 $DGL 0,269
|
||
1043 1043 001B2 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
1044 1044 ; line 304 : KRMK = 1;
|
||
1045 1045 $DGL 0,270
|
||
1046 1046 001B5 713AE7 set1 MK1H.3 ;[INF] 3, 2
|
||
1047 1047 ; line 305 : return;
|
||
1048 1048 $DGL 0,271
|
||
1049 1049 001B8 D7 ret ;[INF] 1, 6
|
||
1050 1050 001B9 ??eb12_tsk_sys:
|
||
1051 1051 ; line 306 : }
|
||
1052 1052 001B9 ?L0038:
|
||
1053 1053 ; line 307 :
|
||
1054 1054 ; line 308 : default:
|
||
1055 1055 ; line 309 : while( 1 )
|
||
1056 1056 ; line 310 : {
|
||
1057 1057 001B9 ??bb14_tsk_sys:
|
||
1058 1058 ; line 311 : NOP( );
|
||
1059 1059 $DGL 0,277
|
||
1060 1060 001B9 00 nop ;[INF] 1, 1
|
||
1061 1061 001BA ??eb14_tsk_sys:
|
||
1062 1062 ; line 312 : // <20><><EFBFBD>蓾<EFBFBD>Ȃ<EFBFBD><C882>X<EFBFBD>e<EFBFBD>[<5B>g
|
||
1063 1063 ; line 313 : }
|
||
1064 1064 $DGL 0,279
|
||
1065 1065 001BA EFFD br $?L0038 ;[INF] 2, 3
|
||
1066 1066 001BC ??eb00_tsk_sys:
|
||
1067 1067 ; line 314 :
|
||
1068 1068 ; line 315 : }
|
||
1069 1069 001BC ?L0004:
|
||
1070 1070 ; line 316 : }
|
||
1071 1071 $DGL 0,282
|
||
1072 1072 001BC ??ef_tsk_sys:
|
||
1073 1073 001BC D7 ret ;[INF] 1, 6
|
||
1074 1074 001BD ??ee_tsk_sys:
|
||
1075 1075 ; line 317 :
|
||
1076 1076 ; line 318 :
|
||
1077 1077 ; line 319 :
|
||
1078 1078 ; line 320 : /*******************************************************//**
|
||
1079 1079 ; line 321 : PMIC<49><43><EFBFBD>d<EFBFBD><64><EFBFBD>ُ<EFBFBD><D98F>Ŏ~<7E>߂<EFBFBD><DF82><EFBFBD><EFBFBD>m<EFBFBD>F
|
||
1080 1080 ; line 322 : **********************************************************/
|
||
1081 1081 ; line 323 : static void chk_emergencyExit(){
|
||
1082 1082 001BD _chk_emergencyExit:
|
||
1083 1083 $DGL 1,166
|
||
1084 1084 001BD ??bf_chk_emergencyExit:
|
||
1085 1085 ; line 324 : #ifndef _PARRADIUM_
|
||
1086 1086 ; line 325 : static state;
|
||
1087 1087 ; line 326 :
|
||
1088 1088 ; line 327 : if( !RESET1_n )
|
||
1089 1089 $DGL 0,5
|
||
1090 1090 001BD 31020040 bt P0.0,$?L0049 ;[INF] 4, 5
|
||
1091 1091 ; line 328 : {
|
||
1092 1092 001C1 ??bb00_chk_emergencyExit:
|
||
1093 1093 ; line 329 : if( PM_chk_LDSW( ) == 0 )
|
||
1094 1094 $DGL 0,7
|
||
1095 1095 001C1 300300 movw ax,#03H ; 3 ;[INF] 3, 1
|
||
1096 1096 001C4 C1 push ax ;[INF] 1, 1
|
||
1097 1097 001C5 5084 mov x,#084H ; 132 ;[INF] 2, 1
|
||
1098 1098 001C7 RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
|
||
1099 1099 001CA C0 pop ax ;[INF] 1, 1
|
||
1100 1100 001CB 62 mov a,c ;[INF] 1, 1
|
||
1101 1101 001CC 5C01 and a,#01H ; 1 ;[INF] 2, 1
|
||
1102 1102 001CE D1 cmp0 a ;[INF] 1, 1
|
||
1103 1103 001CF DF07 bnz $?L0051 ;[INF] 2, 4
|
||
1104 1104 ; line 330 : {
|
||
1105 1105 001D1 ??bb01_chk_emergencyExit:
|
||
1106 1106 ; line 331 : // PMIC<49><43><EFBFBD>ُ<EFBFBD><D98F>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>f<EFBFBD><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
1107 1107 ; line 332 : system_status.pwr_state = OFF_TRIG;
|
||
1108 1108 $DGL 0,10
|
||
1109 1109 001D1 RF50000 clrb !_system_status ;[INF] 3, 1
|
||
1110 1110 ; line 333 : renge_task_interval_run_force = 1;
|
||
1111 1111 $DGL 0,11
|
||
1112 1112 001D4 R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
1113 1113 001D7 ??eb01_chk_emergencyExit:
|
||
1114 1114 ; line 334 : }
|
||
1115 1115 $DGL 0,12
|
||
1116 1116 001D7 D7 ret ;[INF] 1, 6
|
||
1117 1117 001D8 ?L0051:
|
||
1118 1118 ; line 335 : else
|
||
1119 1119 ; line 336 : {
|
||
1120 1120 001D8 ??bb02_chk_emergencyExit:
|
||
1121 1121 ; line 337 : if( state == 0 )
|
||
1122 1122 $DGL 0,15
|
||
1123 1123 001D8 F6 clrw ax ;[INF] 1, 1
|
||
1124 1124 001D9 R420000 cmpw ax,!?L0048 ; state ;[INF] 3, 1
|
||
1125 1125 001DC DF27 bnz $?L0050 ;[INF] 2, 4
|
||
1126 1126 ; line 338 : {
|
||
1127 1127 001DE ??bb03_chk_emergencyExit:
|
||
1128 1128 ; line 339 : state = 1;
|
||
1129 1129 $DGL 0,17
|
||
1130 1130 001DE E6 onew ax ;[INF] 1, 1
|
||
1131 1131 001DF RBF0000 movw !?L0048,ax ; state ;[INF] 3, 1
|
||
1132 1132 ; line 340 : // <20>f<EFBFBD>o<EFBFBD>b<EFBFBD>K<EFBFBD>Ȃ肪<C882><E882AA><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
1133 1133 ; line 341 : iic_mcu_write_a_byte( IIC_SLA_PMIC, PM_REG_ADRS_BL,
|
||
1134 1134 ; 0 );
|
||
1135 1135 $DGL 0,19
|
||
1136 1136 001E2 F6 clrw ax ;[INF] 1, 1
|
||
1137 1137 001E3 C1 push ax ;[INF] 1, 1
|
||
1138 1138 001E4 5004 mov x,#04H ; 4 ;[INF] 2, 1
|
||
1139 1139 001E6 C1 push ax ;[INF] 1, 1
|
||
1140 1140 001E7 5084 mov x,#084H ; 132 ;[INF] 2, 1
|
||
1141 1141 001E9 RFD0000 call !_iic_mcu_write_a_byte ;[INF] 3, 3
|
||
1142 1142 001EC 1004 addw sp,#04H ; 4 ;[INF] 2, 1
|
||
1143 1143 ; line 342 : vreg_ctr[VREG_C_STATUS] = ( vreg_ctr[VREG_C_STATUS]
|
||
1144 1144 ; & 0b10011111 );
|
||
1145 1145 $DGL 0,20
|
||
1146 1146 001EE R8F0F00 mov a,!_vreg_ctr+15 ;[INF] 3, 1
|
||
1147 1147 001F1 5C9F and a,#09FH ; 159 ;[INF] 2, 1
|
||
1148 1148 001F3 R9F0F00 mov !_vreg_ctr+15,a ;[INF] 3, 1
|
||
1149 1149 ; line 343 : vreg_ctr[VREG_C_COMMAND0] |= REG_BIT_RESET1_REQ;
|
||
1150 1150 $DGL 0,21
|
||
1151 1151 001F6 R71102000 set1 !_vreg_ctr+32.1 ;[INF] 4, 2
|
||
1152 1152 ; line 344 : renge_task_immed_add( do_command0 );
|
||
1153 1153 $DGL 0,22
|
||
1154 1154 001FA R300000 movw ax,#loww (_do_command0) ;[INF] 3, 1
|
||
1155 1155 001FD RFD0000 call !_renge_task_immed_add ;[INF] 3, 3
|
||
1156 1156 00200 ??eb03_chk_emergencyExit:
|
||
1157 1157 ; line 345 : }
|
||
1158 1158 ; line 346 : }
|
||
1159 1159 00200 ??eb02_chk_emergencyExit:
|
||
1160 1160 ; line 347 : }
|
||
1161 1161 $DGL 0,25
|
||
1162 1162 00200 ??eb00_chk_emergencyExit:
|
||
1163 1163 00200 D7 ret ;[INF] 1, 6
|
||
1164 1164 00201 ?L0049:
|
||
1165 1165 ; line 348 : else
|
||
1166 1166 ; line 349 : {
|
||
1167 1167 00201 ??bb04_chk_emergencyExit:
|
||
1168 1168 ; line 350 : state = 0;
|
||
1169 1169 $DGL 0,28
|
||
1170 1170 00201 F6 clrw ax ;[INF] 1, 1
|
||
1171 1171 00202 RBF0000 movw !?L0048,ax ; state ;[INF] 3, 1
|
||
1172 1172 00205 ??eb04_chk_emergencyExit:
|
||
1173 1173 ; line 351 : }
|
||
1174 1174 00205 ?L0050:
|
||
1175 1175 ; line 352 : #endif
|
||
1176 1176 ; line 353 : }
|
||
1177 1177 $DGL 0,31
|
||
1178 1178 00205 ??ef_chk_emergencyExit:
|
||
1179 1179 00205 D7 ret ;[INF] 1, 6
|
||
1180 1180 00206 ??ee_chk_emergencyExit:
|
||
1181 1181 ; line 354 :
|
||
1182 1182 ; line 355 :
|
||
1183 1183 ; line 356 :
|
||
1184 1184 ; line 357 :
|
||
1185 1185 ; line 358 :
|
||
1186 1186 ; line 359 : /* ========================================================
|
||
1187 1187 ; line 360 : CPU<50><55><EFBFBD><EFBFBD><EFBFBD>̃X<CC83><58><EFBFBD>[<5B>v<EFBFBD>v<EFBFBD><76>
|
||
1188 1188 ; line 361 : <20>@<40>|<7C>[<5B><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD>ɂ<EFBFBD><C982>܂<EFBFBD><DC82><EFBFBD><EFBFBD>B
|
||
1189 1189 ; line 362 : ======================================================== */
|
||
1190 1190 ; line 363 : /*
|
||
1191 1191 ; line 364 : __interrupt void intp0_slp( )
|
||
1192 1192 ; line 365 : { // SLP
|
||
1193 1193 ; line 366 : if( SLP_REQ ){
|
||
1194 1194 ; line 367 : system_status.pwr_state = SLEEP_TRIG;
|
||
1195 1195 ; line 368 : }else{
|
||
1196 1196 ; line 369 : system_status.pwr_state = ON_TRIG;
|
||
1197 1197 ; line 370 : if( PM_BL_set() != ERR_SUCCESS ){
|
||
1198 1198 ; line 371 : renge_task_interval_run_force = 1;
|
||
1199 1199 ; line 372 : iic_mcu_stop();
|
||
1200 1200 ; line 373 : system_status.pwr_state = OFF_TRIG;
|
||
1201 1201 ; line 374 : }
|
||
1202 1202 ; line 375 : }
|
||
1203 1203 ; line 376 : renge_task_interval_run_force = 1;
|
||
1204 1204 ; line 377 : }
|
||
1205 1205 ; line 378 : */
|
||
1206 1206 ; line 379 :
|
||
1207 1207 ; line 380 :
|
||
1208 1208 ; line 381 :
|
||
1209 1209 ; line 382 : /*******************************************************//**
|
||
1210 1210 ; line 383 : <20>S<EFBFBD><53><EFBFBD>Ӗ<EFBFBD><D396>Ȃ<EFBFBD><C882>ł<EFBFBD><C582><EFBFBD><EFBFBD>A<EFBFBD>C<EFBFBD><43><EFBFBD>I<EFBFBD>ȕ<EFBFBD><C895><EFBFBD>...
|
||
1211 1211 ; line 384 : **********************************************************/
|
||
1212 1212 ; line 385 : task_status_immed tski_firm_update(){
|
||
1213 1213 00206 _tski_firm_update:
|
||
1214 1214 $DGL 1,193
|
||
1215 1215 00206 ??bf_tski_firm_update:
|
||
1216 1216 ; line 386 : firm_update();
|
||
1217 1217 $DGL 0,2
|
||
1218 1218 00206 RFD0000 call !_firm_update ;[INF] 3, 3
|
||
1219 1219 ; line 387 : return( ERR_SUCCESS );
|
||
1220 1220 $DGL 0,3
|
||
1221 1221 00209 F7 clrw bc ;[INF] 1, 1
|
||
1222 1222 ; line 388 : }
|
||
1223 1223 $DGL 0,4
|
||
1224 1224 0020A ??ef_tski_firm_update:
|
||
1225 1225 0020A D7 ret ;[INF] 1, 6
|
||
1226 1226 0020B ??ee_tski_firm_update:
|
||
1227 1227
|
||
1228 1228 ----- @@CODEL CSEG
|
||
1229 1229
|
||
1230 1230 ----- @@BASE CSEG BASE
|
||
1231 1231 END
|
||
1232 1232
|
||
1233 1233
|
||
1234 1234 ; *** Code Information ***
|
||
1235 1235 ;
|
||
1236 1236 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\task_sys.c
|
||
1237 1237 ;
|
||
1238 1238 ; $FUNC tsk_sys(35)
|
||
1239 1239 ; void=(void)
|
||
1240 1240 ; CODE SIZE= 433 bytes, CLOCK_SIZE= 384 clocks, STACK_SIZE= 12 bytes
|
||
1241 1241 ;
|
||
1242 1242 ; $CALL iic_mcu_start(80)
|
||
1243 1243 ; void=(void)
|
||
1244 1244 ;
|
||
1245 1245 ; $CALL PM_init(83)
|
||
1246 1246 ; void=(void)
|
||
1247 1247 ;
|
||
1248 1248 ; $CALL PM_sys_pow_on(85)
|
||
1249 1249 ; bc=(void)
|
||
1250 1250 ;
|
||
1251 1251 ; $CALL iic_mcu_stop(88)
|
||
1252 1252 ; void=(void)
|
||
1253 1253 ;
|
||
1254 1254 ; $CALL PM_LCD_vcom_set(100)
|
||
1255 1255 ; bc=(void)
|
||
1256 1256 ;
|
||
1257 1257 ; $CALL LED_init(122)
|
||
1258 1258 ; void=(void)
|
||
1259 1259 ;
|
||
1260 1260 ; $CALL IIC_ctr_Init(126)
|
||
1261 1261 ; void=(void)
|
||
1262 1262 ;
|
||
1263 1263 ; $CALL set_irq(136)
|
||
1264 1264 ; void=(int:ax, int:[sp+4])
|
||
1265 1265 ;
|
||
1266 1266 ; $CALL IIC_twl_Init(138)
|
||
1267 1267 ; void=(void)
|
||
1268 1268 ;
|
||
1269 1269 ; $CALL chk_emergencyExit(163)
|
||
1270 1270 ; void=(void)
|
||
1271 1271 ;
|
||
1272 1272 ; $CALL iic_mcu_write_a_byte(173)
|
||
1273 1273 ; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
1274 1274 ;
|
||
1275 1275 ; $CALL chk_emergencyExit(178)
|
||
1276 1276 ; void=(void)
|
||
1277 1277 ;
|
||
1278 1278 ; $CALL iic_mcu_write_a_byte(181)
|
||
1279 1279 ; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
1280 1280 ;
|
||
1281 1281 ; $CALL wait_ms(182)
|
||
1282 1282 ; void=(int:ax)
|
||
1283 1283 ;
|
||
1284 1284 ; $CALL LED_stop(208)
|
||
1285 1285 ; void=(void)
|
||
1286 1286 ;
|
||
1287 1287 ; $CALL IIC_ctr_Stop(209)
|
||
1288 1288 ; void=(void)
|
||
1289 1289 ;
|
||
1290 1290 ; $CALL IIC_twl_Stop(210)
|
||
1291 1291 ; void=(void)
|
||
1292 1292 ;
|
||
1293 1293 ; $CALL PM_sys_pow_off(235)
|
||
1294 1294 ; bc=(void)
|
||
1295 1295 ;
|
||
1296 1296 ; $CALL iic_mcu_stop(278)
|
||
1297 1297 ; void=(void)
|
||
1298 1298 ;
|
||
1299 1299 ; $FUNC chk_emergencyExit(323)
|
||
1300 1300 ; void=(void)
|
||
1301 1301 ; CODE SIZE= 73 bytes, CLOCK_SIZE= 68 clocks, STACK_SIZE= 8 bytes
|
||
1302 1302 ;
|
||
1303 1303 ; $CALL iic_mcu_read_a_byte(329)
|
||
1304 1304 ; bc=(int:ax, int:[sp+4])
|
||
1305 1305 ;
|
||
1306 1306 ; $CALL iic_mcu_write_a_byte(341)
|
||
1307 1307 ; bc=(int:ax, int:[sp+4], int:[sp+6])
|
||
1308 1308 ;
|
||
1309 1309 ; $CALL renge_task_immed_add(344)
|
||
1310 1310 ; bc=(pointer:ax)
|
||
1311 1311 ;
|
||
1312 1312 ; $FUNC tski_firm_update(385)
|
||
1313 1313 ; bc=(void)
|
||
1314 1314 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 10 clocks, STACK_SIZE= 4 bytes
|
||
1315 1315 ;
|
||
1316 1316 ; $CALL firm_update(386)
|
||
1317 1317 ; bc=(void)
|
||
1318 1318
|
||
1319 1319 ; Target chip : uPD79F0104
|
||
1320 1320 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.0 @@BITS
|
||
00000 00030H @@CNST
|
||
00000 00002H @@R_INIT
|
||
00000 00002H @@INIT
|
||
00000 00002H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H @@CNSTL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 0020BH ROM_CODE
|
||
00000 00000H @@CODEL
|
||
00000 00000H @@BASE
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|