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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
803 lines
58 KiB
Plaintext
803 lines
58 KiB
Plaintext
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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
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Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\rtc.asm
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Para-file:
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In-file: inter_asm\rtc.asm
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Obj-file: rtc.rel
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Prn-file: rtc.prn
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Assemble list
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ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
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1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24
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2 2
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3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no rtc.c
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6 6 ; In-file : rtc.c
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7 7 ; Asm-file : inter_asm\rtc.asm
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8 8 ; Para-file :
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9 9
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10 10 $PROCESSOR(9F0104)
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11 11 $DEBUG
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12 12 $NODEBUGA
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13 13 $KANJICODE SJIS
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14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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15 15
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16 16 $DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H
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17 17 $DGS AUX_FIL, rtc.c
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18 18 $DGS MOD_NAM, rtc, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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27 27 $DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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32 32 $DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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33 33 $DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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36 36 $DGS AUX_TAG, 01H, 01EH
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37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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45 45 $DGS AUX_EOS, 013H, 01H
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46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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47 47 $DGS AUX_TAG, 01H, 025H
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48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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52 52 $DGS AUX_EOS, 01EH, 01H
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53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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54 54 $DGS AUX_TAG, 01H, 02FH
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55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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62 62 $DGS AUX_EOS, 025H, 01H
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63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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64 64 $DGS AUX_TAG, 04H, 041H
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65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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70 70 $DGS AUX_BIT, 00H, 01H
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71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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72 72 $DGS AUX_BIT, 00H, 01H
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73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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74 74 $DGS AUX_BIT, 00H, 01H
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75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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76 76 $DGS AUX_BIT, 00H, 01H
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77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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80 80 $DGS AUX_EOS, 02FH, 04H
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81 81 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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82 82 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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83 83 $DGS GLV_SYM, _RTC_init, U, U, 01H, 026H, 01H, 02H
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84 84 $DGS AUX_FUN, 00H, U, U, 051H, 00H, 00H
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85 85 $DGS BEG_FUN, ??bf_RTC_init, U, U, 00H, 065H, 01H, 00H
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86 86 $DGS AUX_BEG, 017H, 02H, 047H
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87 87 $DGS BEG_BLK, ??bb00_RTC_init, U, U, 00H, 064H, 01H, 00H
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88 88 $DGS AUX_BEG, 04H, 00H, 04BH
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89 89 $DGS END_BLK, ??eb00_RTC_init, U, U, 00H, 064H, 01H, 00H
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90 90 $DGS AUX_END, 017H
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91 91 $DGS BEG_BLK, ??bb01_RTC_init, U, U, 00H, 064H, 01H, 00H
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92 92 $DGS AUX_BEG, 022H, 00H, 00H
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93 93 $DGS END_BLK, ??eb01_RTC_init, U, U, 00H, 064H, 01H, 00H
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94 94 $DGS AUX_END, 023H
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95 95 $DGS END_FUN, ??ef_RTC_init, U, U, 00H, 065H, 01H, 00H
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96 96 $DGS AUX_END, 029H
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97 97 $DGS GLV_SYM, _int_rtc, U, U, 0E001H, 026H, 01H, 02H
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98 98 $DGS AUX_FUN, 00H, U, U, 067H, 00H, 00H
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99 99 $DGS BEG_FUN, ??bf_int_rtc, U, U, 00H, 065H, 01H, 00H
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100 100 $DGS AUX_BEG, 048H, 02H, 055H
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101 101 $DGS BEG_BLK, ??bb00_int_rtc, U, U, 00H, 064H, 01H, 00H
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102 102 $DGS AUX_BEG, 06H, 00H, 057H
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103 103 $DGS BEG_BLK, ??bb01_int_rtc, U, U, 00H, 064H, 01H, 00H
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104 104 $DGS AUX_BEG, 08H, 00H, 059H
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105 105 $DGS BEG_BLK, ??bb02_int_rtc, U, U, 00H, 064H, 01H, 00H
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106 106 $DGS AUX_BEG, 0AH, 00H, 05DH
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107 107 $DGS END_BLK, ??eb02_int_rtc, U, U, 00H, 064H, 01H, 00H
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108 108 $DGS AUX_END, 0AH
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109 109 $DGS BEG_BLK, ??bb03_int_rtc, U, U, 00H, 064H, 01H, 00H
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110 110 $DGS AUX_BEG, 0EH, 00H, 00H
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111 111 $DGS END_BLK, ??eb03_int_rtc, U, U, 00H, 064H, 01H, 00H
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112 112 $DGS AUX_END, 010H
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113 113 $DGS END_BLK, ??eb01_int_rtc, U, U, 00H, 064H, 01H, 00H
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114 114 $DGS AUX_END, 011H
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115 115 $DGS END_BLK, ??eb00_int_rtc, U, U, 00H, 064H, 01H, 00H
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116 116 $DGS AUX_END, 012H
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117 117 $DGS END_FUN, ??ef_int_rtc, U, U, 00H, 065H, 01H, 00H
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118 118 $DGS AUX_END, 013H
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119 119 $DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 026H, 01H, 02H
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120 120 $DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H
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121 121 $DGS BEG_FUN, ??bf_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H
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122 122 $DGS AUX_BEG, 063H, 02H, 06BH
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123 123 $DGS BEG_BLK, ??bb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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124 124 $DGS AUX_BEG, 03H, 00H, 06DH
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125 125 $DGS BEG_BLK, ??bb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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126 126 $DGS AUX_BEG, 07H, 00H, 00H
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127 127 $DGS END_BLK, ??eb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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128 128 $DGS AUX_END, 08H
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129 129 $DGS END_BLK, ??eb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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130 130 $DGS AUX_END, 0DH
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131 131 $DGS END_FUN, ??ef_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H
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132 132 $DGS AUX_END, 0EH
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133 133 $DGS GLV_SYM, _set_rtc, U, U, 01H, 026H, 01H, 02H
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134 134 $DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H
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135 135 $DGS BEG_FUN, ??bf_set_rtc, U, U, 00H, 065H, 01H, 00H
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136 136 $DGS AUX_BEG, 07BH, 02H, 07BH
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137 137 $DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H
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138 138 $DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H
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139 139 $DGS BEG_BLK, ??bb00_set_rtc, U, U, 00H, 064H, 01H, 00H
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140 140 $DGS AUX_BEG, 03H, 00H, 00H
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141 141 $DGS END_BLK, ??eb00_set_rtc, U, U, 00H, 064H, 01H, 00H
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142 142 $DGS AUX_END, 07H
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143 143 $DGS END_FUN, ??ef_set_rtc, U, U, 00H, 065H, 01H, 00H
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144 144 $DGS AUX_END, 09H
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145 145 $DGS GLV_SYM, _rtc_unlock, U, U, 01H, 026H, 01H, 02H
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146 146 $DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H
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147 147 $DGS BEG_FUN, ??bf_rtc_unlock, U, U, 00H, 065H, 01H, 00H
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148 148 $DGS AUX_BEG, 08CH, 02H, 085H
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149 149 $DGS BEG_BLK, ??bb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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150 150 $DGS AUX_BEG, 09H, 00H, 087H
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151 151 $DGS BEG_BLK, ??bb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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152 152 $DGS AUX_BEG, 0DH, 00H, 08DH
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153 153 $DGS END_BLK, ??eb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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154 154 $DGS AUX_END, 0EH
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155 155 $DGS END_BLK, ??eb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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156 156 $DGS AUX_END, 011H
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157 157 $DGS BEG_BLK, ??bb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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158 158 $DGS AUX_BEG, 015H, 00H, 00H
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159 159 $DGS END_BLK, ??eb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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160 160 $DGS AUX_END, 01BH
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161 161 $DGS END_FUN, ??ef_rtc_unlock, U, U, 00H, 065H, 01H, 00H
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162 162 $DGS AUX_END, 01CH
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163 163 $DGS GLV_SYM, _int_rtc_int, U, U, 0E001H, 026H, 01H, 02H
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164 164 $DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H
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165 165 $DGS BEG_FUN, ??bf_int_rtc_int, U, U, 00H, 065H, 01H, 00H
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166 166 $DGS AUX_BEG, 0B2H, 00H, 099H
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167 167 $DGS END_FUN, ??ef_int_rtc_int, U, U, 00H, 065H, 01H, 00H
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168 168 $DGS AUX_END, 03H
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169 169 $DGS GLV_SYM, _rtc_work, U, U, 0CH, 026H, 01H, 03H
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170 170 $DGS AUX_STR, 00H, 00H, 07H, 07H, 00H, 00H, 00H, 00H
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171 171 $DGS GLV_SYM, _rtc_lock, U, U, 034CH, 027H, 00H, 00H
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172 172 $DGS GLV_SYM, _rtc_dirty, U, U, 034CH, 027H, 00H, 00H
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173 173 $DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 027H, 00H, 00H
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174 174 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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175 175 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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176 176 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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177 177 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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178 178 $DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 02H, 00H, 00H
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179 179
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180 180 EXTRN _vreg_ctr
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181 181 EXTRN _system_status
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182 182 EXTBIT _renge_flg_interval
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183 183 PUBLIC _rtc_work
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184 184 PUBLIC _rtc_lock
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185 185 PUBLIC _rtc_dirty
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186 186 PUBLIC _rtc_alarm_dirty
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187 187 PUBLIC _RTC_init
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188 188 PUBLIC _int_rtc
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189 189 PUBLIC _rtc_buf_reflesh
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190 190 PUBLIC _set_rtc
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191 191 PUBLIC _rtc_unlock
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192 192 PUBLIC _int_rtc_int
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193 193
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194 194 ----- @@BITS BSEG
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195 195 00000.0 _rtc_lock DBIT
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196 196 00000.1 _rtc_dirty DBIT
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197 197 00000.2 _rtc_alarm_dirty DBIT
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198 198
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199 199 ----- @@CNST CSEG MIRRORP
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200 200 00000 01 _lpf_coeff: DB 01H ; 1
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201 201 00001 02 DB 02H ; 2
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202 202 00002 02 DB 02H ; 2
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203 203 00003 03 DB 03H ; 3
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204 204 00004 03 DB 03H ; 3
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205 205 00005 02 DB 02H ; 2
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206 206 00006 00 DB 00H ; 0
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207 207 00007 FE DB 0FEH ; 254
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208 208 00008 FB DB 0FBH ; 251
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209 209 00009 F7 DB 0F7H ; 247
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210 210 0000A F3 DB 0F3H ; 243
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211 211 0000B F0 DB 0F0H ; 240
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212 212 0000C F0 DB 0F0H ; 240
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213 213 0000D F3 DB 0F3H ; 243
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214 214 0000E FA DB 0FAH ; 250
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215 215 0000F 04 DB 04H ; 4
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216 216 00010 12 DB 012H ; 18
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217 217 00011 25 DB 025H ; 37
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218 218 00012 38 DB 038H ; 56
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219 219 00013 4D DB 04DH ; 77
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220 220 00014 5F DB 05FH ; 95
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221 221 00015 6E DB 06EH ; 110
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222 222 00016 77 DB 077H ; 119
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223 223 00017 7A DB 07AH ; 122
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224 224 00018 77 DB 077H ; 119
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225 225 00019 6E DB 06EH ; 110
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226 226 0001A 5F DB 05FH ; 95
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227 227 0001B 4D DB 04DH ; 77
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228 228 0001C 38 DB 038H ; 56
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229 229 0001D 25 DB 025H ; 37
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230 230 0001E 12 DB 012H ; 18
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231 231 0001F 04 DB 04H ; 4
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232 232 00020 FA DB 0FAH ; 250
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233 233 00021 F3 DB 0F3H ; 243
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234 234 00022 F0 DB 0F0H ; 240
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235 235 00023 F0 DB 0F0H ; 240
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236 236 00024 F3 DB 0F3H ; 243
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237 237 00025 F7 DB 0F7H ; 247
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238 238 00026 FB DB 0FBH ; 251
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239 239 00027 FE DB 0FEH ; 254
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240 240 00028 00 DB 00H ; 0
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241 241 00029 02 DB 02H ; 2
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242 242 0002A 03 DB 03H ; 3
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243 243 0002B 03 DB 03H ; 3
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244 244 0002C 02 DB 02H ; 2
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245 245 0002D 02 DB 02H ; 2
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246 246 0002E 01 DB 01H ; 1
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247 247 0002F 00 DB (1)
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248 248
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249 249 ----- @@R_INIT CSEG UNIT64KP
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250 250
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251 251 ----- @@INIT DSEG BASEP
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252 252
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253 253 ----- @@DATA DSEG BASEP
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254 254 00000 _rtc_work: DS (7)
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255 255 00007 DS (1)
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256 256
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257 257 ----- @@R_INIS CSEG UNIT64KP
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258 258
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259 259 ----- @@INIS DSEG SADDRP
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260 260
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261 261 ----- @@DATS DSEG SADDRP
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262 262
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263 263 ----- @@CNSTL CSEG PAGE64KP
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264 264
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265 265 ----- @@RLINIT CSEG UNIT64KP
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266 266
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267 267 ----- @@INITL DSEG UNIT64KP
|
||
268 268
|
||
269 269 ----- @@DATAL DSEG UNIT64KP
|
||
270 270
|
||
271 271 ----- @@CALT CSEG CALLT0
|
||
272 272
|
||
273 273 ; line 1 : /* ========================================================
|
||
274 274 ; line 2 : RTC
|
||
275 275 ; line 3 : ======================================================== */
|
||
276 276 ; line 4 : #pragma sfr
|
||
277 277 ; line 5 : #pragma inline
|
||
278 278 ; line 6 :
|
||
279 279 ; line 7 :
|
||
280 280 ; line 8 : #include "incs.h"
|
||
281 281 ; line 9 :
|
||
282 282 ; line 10 :
|
||
283 283 ; line 11 :
|
||
284 284 ; line 12 : // ========================================================
|
||
285 285 ; line 13 : u8 rtc_work[7];
|
||
286 286 ; line 14 : bit rtc_lock;
|
||
287 287 ; line 15 : bit rtc_dirty;
|
||
288 288 ; line 16 : bit rtc_alarm_dirty;
|
||
289 289 ; line 17 :
|
||
290 290 ; line 18 : /* ========================================================
|
||
291 291 ; line 19 : <20>y<EFBFBD><79><EFBFBD>t<EFBFBD>F<EFBFBD><46><EFBFBD><EFBFBD><EFBFBD>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
|
||
292 292 ; line 20 : <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̓d<CC93>r<EFBFBD><72><EFBFBD><EFBFBD><EFBFBD>r<EFBFBD>b<EFBFBD>g<EFBFBD>̃Z<CC83>b<EFBFBD>g
|
||
293 293 ; line 21 : ======================================================== */
|
||
294 294 ; line 22 : void RTC_init( void )
|
||
295 295 ; line 23 : {
|
||
296 296
|
||
297 297 ----- ROM_CODE CSEG BASE
|
||
298 298 00000 _RTC_init:
|
||
299 299 $DGL 1,67
|
||
300 300 00000 C7 push hl ;[INF] 1, 1
|
||
301 301 00001 ??bf_RTC_init:
|
||
302 302 ; line 24 :
|
||
303 303 ; line 25 : if( !RTCEN ) // <20>r<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>烊<EFBFBD>u<EFBFBD>[<5B>g
|
||
304 304 $DGL 0,3
|
||
305 305 00001 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1
|
||
306 306 00004 71F4 mov1 CY,[hl].7 ;[INF] 2, 1
|
||
307 307 00006 DC29 bc $?L0003 ;[INF] 2, 4
|
||
308 308 ; line 26 : {
|
||
309 309 00008 ??bb00_RTC_init:
|
||
310 310 ; line 27 : RTCEN = 1; // <20><><EFBFBD>W<EFBFBD><57><EFBFBD>[<5B><>ON
|
||
311 311 $DGL 0,5
|
||
312 312 00008 7170F000 set1 !PER0.7 ;[INF] 4, 2
|
||
313 313 ; line 28 :
|
||
314 314 ; line 29 : // RTC<54>ݒ<EFBFBD>
|
||
315 315 ; line 30 : RTCC0 = 0b00001000; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~<7E>A24<32><34><EFBFBD>Ԑ<EFBFBD><D490>A32k<32>o<EFBFBD>́u<CD81><75>
|
||
316 316 ; <20><><EFBFBD>Ȃ<EFBFBD><C882>v<EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD>݂Ȃ<DD82> */
|
||
317 317 $DGL 0,8
|
||
318 318 0000C CE9D08 mov RTCC0,#08H ; 8 ;[INF] 3, 1
|
||
319 319 ; line 31 : RTCC1 = 0b11000000; /* <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD>ݗL<DD97><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD>n
|
||
320 320 ; */
|
||
321 321 $DGL 0,9
|
||
322 322 0000F CE9EC0 mov RTCC1,#0C0H ; 192 ;[INF] 3, 1
|
||
323 323 ; line 32 : RTCC2 = 0b10000000; /* <20>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>:32k/2^6=2ms<6D>ARTCD
|
||
324 324 ; IV<49>o<EFBFBD>͂Ȃ<CD82> */
|
||
325 325 $DGL 0,10
|
||
326 326 00012 CE9F80 mov RTCC2,#080H ; 128 ;[INF] 3, 1
|
||
327 327 ; line 33 :
|
||
328 328 ; line 34 : SEC = 0x00;
|
||
329 329 $DGL 0,12
|
||
330 330 00015 F592FF clrb !SEC ;[INF] 3, 1
|
||
331 331 ; line 35 : MIN = 0x00;
|
||
332 332 $DGL 0,13
|
||
333 333 00018 F593FF clrb !MIN ;[INF] 3, 1
|
||
334 334 ; line 36 : HOUR = 0x15;
|
||
335 335 $DGL 0,14
|
||
336 336 0001B CE9415 mov HOUR,#015H ; 21 ;[INF] 3, 1
|
||
337 337 ; line 37 : DAY = 0x01;
|
||
338 338 $DGL 0,15
|
||
339 339 0001E E596FF oneb !DAY ;[INF] 3, 1
|
||
340 340 ; line 38 : WEEK = 0x00;
|
||
341 341 $DGL 0,16
|
||
342 342 00021 F595FF clrb !WEEK ;[INF] 3, 1
|
||
343 343 ; line 39 : MONTH = 0x11;
|
||
344 344 $DGL 0,17
|
||
345 345 00024 CE9711 mov MONTH,#011H ; 17 ;[INF] 3, 1
|
||
346 346 ; line 40 : YEAR = 0x09;
|
||
347 347 $DGL 0,18
|
||
348 348 00027 CE9809 mov YEAR,#09H ; 9 ;[INF] 3, 1
|
||
349 349 ; line 41 :
|
||
350 350 ; line 42 : ALARMWW = 0x7F;
|
||
351 351 $DGL 0,20
|
||
352 352 0002A CE9C7F mov ALARMWW,#07FH ; 127 ;[INF] 3, 1
|
||
353 353 ; line 43 :
|
||
354 354 ; line 44 : vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT;
|
||
355 355 $DGL 0,22
|
||
356 356 0002D R71000200 set1 !_vreg_ctr+2.0 ;[INF] 4, 2
|
||
357 357 00031 ??eb00_RTC_init:
|
||
358 358 ; line 45 : }
|
||
359 359 00031 ?L0003:
|
||
360 360 ; line 46 : // <20><><EFBFBD>荞<EFBFBD>ݐݒ<DD90>
|
||
361 361 ; line 47 : RTCIF = 0;
|
||
362 362 $DGL 0,25
|
||
363 363 00031 711BE3 clr1 IF1H.1 ;[INF] 3, 2
|
||
364 364 ; line 48 : RTCIIF = 0;
|
||
365 365 $DGL 0,26
|
||
366 366 00034 712BE3 clr1 IF1H.2 ;[INF] 3, 2
|
||
367 367 ; line 49 : RTCMK = 1; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)<29>֎~ */
|
||
368 368 $DGL 0,27
|
||
369 369 00037 711AE7 set1 MK1H.1 ;[INF] 3, 2
|
||
370 370 ; line 50 : RTCIMK = 0; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28>A<EFBFBD><41><EFBFBD>[<5B><>&<26>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>
|
||
371 371 ; )<29><><EFBFBD><EFBFBD> */
|
||
372 372 $DGL 0,28
|
||
373 373 0003A 712BE7 clr1 MK1H.2 ;[INF] 3, 2
|
||
374 374 ; line 51 :
|
||
375 375 ; line 52 : RTCE = 1; /* <20><><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD>n */
|
||
376 376 $DGL 0,30
|
||
377 377 0003D 717A9D set1 RTCC0.7 ;[INF] 3, 2
|
||
378 378 ; line 53 :
|
||
379 379 ; line 54 : RWAIT = 1;
|
||
380 380 $DGL 0,32
|
||
381 381 00040 710A9E set1 RTCC1.0 ;[INF] 3, 2
|
||
382 382 ; line 55 : while( !RWST )
|
||
383 383 $DGL 0,33
|
||
384 384 00043 ?L0005:
|
||
385 385 00043 31929E02 bt RTCC1.1,$?L0006 ;[INF] 4, 5
|
||
386 386 ; line 56 : {;
|
||
387 387 00047 ??bb01_RTC_init:
|
||
388 388 00047 ??eb01_RTC_init:
|
||
389 389 ; line 57 : }
|
||
390 390 $DGL 0,35
|
||
391 391 00047 EFFA br $?L0005 ;[INF] 2, 3
|
||
392 392 00049 ?L0006:
|
||
393 393 ; line 58 : RWAIT = 0;
|
||
394 394 $DGL 0,36
|
||
395 395 00049 710B9E clr1 RTCC1.0 ;[INF] 3, 2
|
||
396 396 ; line 59 :
|
||
397 397 ; line 60 : rtc_lock = 0;
|
||
398 398 $DGL 0,38
|
||
399 399 0004C R710300 clr1 _rtc_lock ;[INF] 3, 2
|
||
400 400 ; line 61 : rtc_dirty = 0;
|
||
401 401 $DGL 0,39
|
||
402 402 0004F R711300 clr1 _rtc_dirty ;[INF] 3, 2
|
||
403 403 ; line 62 : rtc_alarm_dirty = 0;
|
||
404 404 $DGL 0,40
|
||
405 405 00052 R712300 clr1 _rtc_alarm_dirty ;[INF] 3, 2
|
||
406 406 ; line 63 : }
|
||
407 407 $DGL 0,41
|
||
408 408 00055 ??ef_RTC_init:
|
||
409 409 00055 C6 pop hl ;[INF] 1, 1
|
||
410 410 00056 D7 ret ;[INF] 1, 6
|
||
411 411 00057 ??ee_RTC_init:
|
||
412 412 ; line 64 :
|
||
413 413 ; line 65 :
|
||
414 414 ; line 66 :
|
||
415 415 ; line 67 : /* ========================================================
|
||
416 416 ; line 68 : RTC <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
417 417 ; line 69 : 2^6/fXT<58>i1.953125 ms<6D>j
|
||
418 418 ; line 70 : ======================================================== */
|
||
419 419 ; line 71 : __interrupt void int_rtc( )
|
||
420 420 ; line 72 : {
|
||
421 421
|
||
422 422 ----- @@BASE CSEG BASE
|
||
423 423 00000 _int_rtc:
|
||
424 424 $DGL 1,81
|
||
425 425 00000 C1 push ax ;[INF] 1, 1
|
||
426 426 00001 ??bf_int_rtc:
|
||
427 427 ; line 73 : // <20><><EFBFBD>t<EFBFBD><74><EFBFBD>w<EFBFBD><77><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
428 428 ; line 74 : if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY )
|
||
429 429 ; line 75 : && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH )
|
||
430 430 ; line 76 : && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) )
|
||
431 431 $DGL 0,5
|
||
432 432 00001 R8F3A00 mov a,!_vreg_ctr+58 ;[INF] 3, 1
|
||
433 433 00004 4F96FF cmp a,!DAY ;[INF] 3, 1
|
||
434 434 00007 DF32 bnz $?L0013 ;[INF] 2, 4
|
||
435 435 00009 R8F3B00 mov a,!_vreg_ctr+59 ;[INF] 3, 1
|
||
436 436 0000C 4F97FF cmp a,!MONTH ;[INF] 3, 1
|
||
437 437 0000F DF2A bnz $?L0013 ;[INF] 2, 4
|
||
438 438 00011 R8F3C00 mov a,!_vreg_ctr+60 ;[INF] 3, 1
|
||
439 439 00014 4F98FF cmp a,!YEAR ;[INF] 3, 1
|
||
440 440 00017 DF22 bnz $?L0013 ;[INF] 2, 4
|
||
441 441 ; line 77 : {
|
||
442 442 00019 ??bb00_int_rtc:
|
||
443 443 ; line 78 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) =
|
||
444 444 ; = 0 )
|
||
445 445 $DGL 0,7
|
||
446 446 00019 R8F1900 mov a,!_vreg_ctr+25 ;[INF] 3, 1
|
||
447 447 0001C 5C04 and a,#04H ; 4 ;[INF] 2, 1
|
||
448 448 0001E D1 cmp0 a ;[INF] 1, 1
|
||
449 449 0001F DF1A bnz $?L0013 ;[INF] 2, 4
|
||
450 450 ; line 79 : {
|
||
451 451 00021 ??bb01_int_rtc:
|
||
452 452 ; line 80 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM;
|
||
453 453 $DGL 0,9
|
||
454 454 00021 R71201100 set1 !_vreg_ctr+17.2 ;[INF] 4, 2
|
||
455 455 ; line 81 : IRQ0_ast;
|
||
456 456 $DGL 0,10
|
||
457 457 00025 ??bb02_int_rtc:
|
||
458 458 00025 716307 clr1 P7.6 ;[INF] 3, 2
|
||
459 459 00028 716B27 clr1 PM7.6 ;[INF] 3, 2
|
||
460 460 0002B ??eb02_int_rtc:
|
||
461 461 ; line 82 : // <20>}<7D>X<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82><EFBFBD>
|
||
462 462 ; line 83 : if(( system_status.pwr_state == BT_CHARGE ) ||
|
||
463 463 $DGL 0,12
|
||
464 464 0002B R40000006 cmp !_system_status,#06H ; 6 ;[INF] 4, 1
|
||
465 465 0002F DD06 bz $?L0015 ;[INF] 2, 4
|
||
466 466 ; line 84 : ( system_status.pwr_state == OFF ))
|
||
467 467 $DGL 0,13
|
||
468 468 00031 R40000001 cmp !_system_status,#01H ; 1 ;[INF] 4, 1
|
||
469 469 00035 61F8 sknz ;[INF] 2, 1
|
||
470 470 00037 ?L0015:
|
||
471 471 ; line 85 : {
|
||
472 472 00037 ??bb03_int_rtc:
|
||
473 473 ; line 86 : system_status.poweron_reason = RTC_ALARM;
|
||
474 474 $DGL 0,15
|
||
475 475 00037 RCF010002 mov !_system_status+1,#02H ; 2 ;[INF] 4, 1
|
||
476 476 0003B ??eb03_int_rtc:
|
||
477 477 ; line 87 : }
|
||
478 478 0003B ?L0013:
|
||
479 479 0003B ??eb01_int_rtc:
|
||
480 480 ; line 88 : }
|
||
481 481 0003B ??eb00_int_rtc:
|
||
482 482 ; line 89 : }
|
||
483 483 ; line 90 : }
|
||
484 484 $DGL 0,19
|
||
485 485 0003B ??ef_int_rtc:
|
||
486 486 0003B C0 pop ax ;[INF] 1, 1
|
||
487 487 0003C 61FC reti ;[INF] 2, 6
|
||
488 488 0003E ??ee_int_rtc:
|
||
489 489 ; line 91 :
|
||
490 490 ; line 92 :
|
||
491 491 ; line 93 :
|
||
492 492 ; line 94 : /* ========================================================
|
||
493 493 ; line 95 : RTC <20>̃<EFBFBD><CC83>[<5B>h
|
||
494 494 ; line 96 : <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>́Asec,min,hour,week,day,month,year <20>̏<EFBFBD>
|
||
495 495 ; line 97 : ======================================================== */
|
||
496 496 ; line 98 : void rtc_buf_reflesh( )
|
||
497 497 ; line 99 : {
|
||
498 498
|
||
499 499 ----- ROM_CODE CSEG BASE
|
||
500 500 00057 _rtc_buf_reflesh:
|
||
501 501 $DGL 1,103
|
||
502 502 00057 C7 push hl ;[INF] 1, 1
|
||
503 503 00058 ??bf_rtc_buf_reflesh:
|
||
504 504 ; line 100 : if( rtc_lock == 0 )
|
||
505 505 $DGL 0,2
|
||
506 506 00058 R3102001E bt _rtc_lock,$?L0018 ;[INF] 4, 5
|
||
507 507 ; line 101 : {
|
||
508 508 0005C ??bb00_rtc_buf_reflesh:
|
||
509 509 ; line 102 : rtc_lock = 1;
|
||
510 510 $DGL 0,4
|
||
511 511 0005C R710200 set1 _rtc_lock ;[INF] 3, 2
|
||
512 512 ; line 103 : RWAIT = 1;
|
||
513 513 $DGL 0,5
|
||
514 514 0005F 710A9E set1 RTCC1.0 ;[INF] 3, 2
|
||
515 515 ; line 104 : while( !RWST )
|
||
516 516 $DGL 0,6
|
||
517 517 00062 ?L0020:
|
||
518 518 00062 31929E02 bt RTCC1.1,$?L0021 ;[INF] 4, 5
|
||
519 519 ; line 105 : {;
|
||
520 520 00066 ??bb01_rtc_buf_reflesh:
|
||
521 521 00066 ??eb01_rtc_buf_reflesh:
|
||
522 522 ; line 106 : }
|
||
523 523 $DGL 0,8
|
||
524 524 00066 EFFA br $?L0020 ;[INF] 2, 3
|
||
525 525 00068 ?L0021:
|
||
526 526 ; line 107 :
|
||
527 527 ; line 108 : memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 );
|
||
528 528 $DGL 0,10
|
||
529 529 00068 R343000 movw de,#loww (_vreg_ctr+48) ;[INF] 3, 1
|
||
530 530 0006B 3692FF movw hl,#0FF92H ; -110 ;[INF] 3, 1
|
||
531 531 0006E 5207 mov c,#07H ; 7 ;[INF] 2, 1
|
||
532 532 00070 ?L0022:
|
||
533 533 00070 8B mov a,[hl] ;[INF] 1, 1
|
||
534 534 00071 99 mov [de],a ;[INF] 1, 1
|
||
535 535 00072 A5 incw de ;[INF] 1, 1
|
||
536 536 00073 A7 incw hl ;[INF] 1, 1
|
||
537 537 00074 92 dec c ;[INF] 1, 1
|
||
538 538 00075 DFF9 bnz $?L0022 ;[INF] 2, 4
|
||
539 539 ; line 109 : RWAIT = 0;
|
||
540 540 $DGL 0,11
|
||
541 541 00077 710B9E clr1 RTCC1.0 ;[INF] 3, 2
|
||
542 542 0007A ??eb00_rtc_buf_reflesh:
|
||
543 543 ; line 110 : // renge_task_immed_add( tski_rtc_close );
|
||
544 544 ; line 111 : }
|
||
545 545 0007A ?L0018:
|
||
546 546 ; line 112 : }
|
||
547 547 $DGL 0,14
|
||
548 548 0007A ??ef_rtc_buf_reflesh:
|
||
549 549 0007A C6 pop hl ;[INF] 1, 1
|
||
550 550 0007B D7 ret ;[INF] 1, 6
|
||
551 551 0007C ??ee_rtc_buf_reflesh:
|
||
552 552 ; line 113 :
|
||
553 553 ; line 114 :
|
||
554 554 ; line 115 :
|
||
555 555 ; line 116 : /* ========================================================
|
||
556 556 ; line 117 : RTC <20>̃<EFBFBD><CC83>C<EFBFBD>g
|
||
557 557 ; line 118 : set_rtc_close <20>ƑŎg<C58E><67><EFBFBD>ĉ<EFBFBD><C489><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B
|
||
558 558 ; line 119 : <20><><EFBFBD><EFBFBD><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@<40>ɃR<C983>s<EFBFBD>[<5B><><EFBFBD>邾<EFBFBD><E982BE><EFBFBD>ŁA
|
||
559 559 ; line 120 : <20><><EFBFBD>ۂ<EFBFBD>RTC<54>ɃZ<C983>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD>set_rtc_close()<29>ł<EFBFBD><C582>B
|
||
560 560 ; line 121 : ======================================================== */
|
||
561 561 ; line 122 : void set_rtc( u8 adrs, u8 data )
|
||
562 562 ; line 123 : {
|
||
563 563 0007C _set_rtc:
|
||
564 564 $DGL 1,117
|
||
565 565 0007C C7 push hl ;[INF] 1, 1
|
||
566 566 0007D 8806 mov a,[sp+6] ;[INF] 2, 1
|
||
567 567 0007F 16 movw hl,ax ;[INF] 1, 1
|
||
568 568 00080 ??bf_set_rtc:
|
||
569 569 ; line 124 : if( rtc_dirty == 0 )
|
||
570 570 $DGL 0,2
|
||
571 571 00080 R31120015 bt _rtc_dirty,$?L0026 ;[INF] 4, 5
|
||
572 572 ; line 125 : {
|
||
573 573 00084 ??bb00_set_rtc:
|
||
574 574 ; line 126 : rtc_dirty = 1;
|
||
575 575 $DGL 0,4
|
||
576 576 00084 R711200 set1 _rtc_dirty ;[INF] 3, 2
|
||
577 577 ; line 127 : memcpy( rtc_work, &SEC, 7 );
|
||
578 578 $DGL 0,5
|
||
579 579 00087 C7 push hl ;[INF] 1, 1
|
||
580 580 00088 R340000 movw de,#loww (_rtc_work) ;[INF] 3, 1
|
||
581 581 0008B 3092FF movw ax,#0FF92H ; -110 ;[INF] 3, 1
|
||
582 582 0008E 16 movw hl,ax ;[INF] 1, 1
|
||
583 583 0008F 5207 mov c,#07H ; 7 ;[INF] 2, 1
|
||
584 584 00091 ?L0028:
|
||
585 585 00091 8B mov a,[hl] ;[INF] 1, 1
|
||
586 586 00092 99 mov [de],a ;[INF] 1, 1
|
||
587 587 00093 A5 incw de ;[INF] 1, 1
|
||
588 588 00094 A7 incw hl ;[INF] 1, 1
|
||
589 589 00095 92 dec c ;[INF] 1, 1
|
||
590 590 00096 DFF9 bnz $?L0028 ;[INF] 2, 4
|
||
591 591 00098 C6 pop hl ;[INF] 1, 1
|
||
592 592 00099 ??eb00_set_rtc:
|
||
593 593 ; line 128 : // renge_task_immed_add( tski_rtc_close ); // I2C<32>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>ɍs<C98D><73>
|
||
594 594 ; line 129 : }
|
||
595 595 00099 ?L0026:
|
||
596 596 ; line 130 : rtc_work[adrs] = data;
|
||
597 597 $DGL 0,8
|
||
598 598 00099 66 mov a,l ;[INF] 1, 1
|
||
599 599 0009A 73 mov b,a ;[INF] 1, 1
|
||
600 600 0009B 67 mov a,h ;[INF] 1, 1
|
||
601 601 0009C R180000 mov _rtc_work[b],a ;[INF] 3, 1
|
||
602 602 ; line 131 : }
|
||
603 603 $DGL 0,9
|
||
604 604 0009F ??ef_set_rtc:
|
||
605 605 0009F C6 pop hl ;[INF] 1, 1
|
||
606 606 000A0 D7 ret ;[INF] 1, 6
|
||
607 607 000A1 ??ee_set_rtc:
|
||
608 608 ; line 132 :
|
||
609 609 ; line 133 :
|
||
610 610 ; line 134 :
|
||
611 611 ; line 135 : /* ========================================================
|
||
612 612 ; line 136 : <20>K<EFBFBD>v<EFBFBD>Ȃ<EFBFBD><C882>ARTC<54><43><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̍X<CC8D>V
|
||
613 613 ; line 137 : ======================================================== */
|
||
614 614 ; line 138 : // task_status_immed tski_rtc_close(){
|
||
615 615 ; line 139 : void rtc_unlock( )
|
||
616 616 ; line 140 : {
|
||
617 617 000A1 _rtc_unlock:
|
||
618 618 $DGL 1,129
|
||
619 619 000A1 C7 push hl ;[INF] 1, 1
|
||
620 620 000A2 ??bf_rtc_unlock:
|
||
621 621 ; line 141 : // <20><><EFBFBD>[<5B>h<EFBFBD><68><EFBFBD>b<EFBFBD>N
|
||
622 622 ; line 142 : // if( rtc_lock != 0 ){
|
||
623 623 ; line 143 : rtc_lock = 0;
|
||
624 624 $DGL 0,4
|
||
625 625 000A2 R710300 clr1 _rtc_lock ;[INF] 3, 2
|
||
626 626 ; line 144 : // }
|
||
627 627 ; line 145 :
|
||
628 628 ; line 146 : // <20><><EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>b<EFBFBD>N
|
||
629 629 ; line 147 : if( rtc_dirty != 0 )
|
||
630 630 $DGL 0,8
|
||
631 631 000A5 R3114001E bf _rtc_dirty,$?L0032 ;[INF] 4, 5
|
||
632 632 ; line 148 : {
|
||
633 633 000A9 ??bb00_rtc_unlock:
|
||
634 634 ; line 149 : rtc_dirty = 0;
|
||
635 635 $DGL 0,10
|
||
636 636 000A9 R711300 clr1 _rtc_dirty ;[INF] 3, 2
|
||
637 637 ; line 150 : RWAIT = 1;
|
||
638 638 $DGL 0,11
|
||
639 639 000AC 710A9E set1 RTCC1.0 ;[INF] 3, 2
|
||
640 640 ; line 151 : while( !RWST )
|
||
641 641 $DGL 0,12
|
||
642 642 000AF ?L0034:
|
||
643 643 000AF 31929E02 bt RTCC1.1,$?L0035 ;[INF] 4, 5
|
||
644 644 ; line 152 : {;
|
||
645 645 000B3 ??bb01_rtc_unlock:
|
||
646 646 000B3 ??eb01_rtc_unlock:
|
||
647 647 ; line 153 : }
|
||
648 648 $DGL 0,14
|
||
649 649 000B3 EFFA br $?L0034 ;[INF] 2, 3
|
||
650 650 000B5 ?L0035:
|
||
651 651 ; line 154 : memcpy( &SEC, rtc_work, 7 );
|
||
652 652 $DGL 0,15
|
||
653 653 000B5 3492FF movw de,#0FF92H ; -110 ;[INF] 3, 1
|
||
654 654 000B8 R360000 movw hl,#loww (_rtc_work) ;[INF] 3, 1
|
||
655 655 000BB 5207 mov c,#07H ; 7 ;[INF] 2, 1
|
||
656 656 000BD ?L0036:
|
||
657 657 000BD 8B mov a,[hl] ;[INF] 1, 1
|
||
658 658 000BE 99 mov [de],a ;[INF] 1, 1
|
||
659 659 000BF A5 incw de ;[INF] 1, 1
|
||
660 660 000C0 A7 incw hl ;[INF] 1, 1
|
||
661 661 000C1 92 dec c ;[INF] 1, 1
|
||
662 662 000C2 DFF9 bnz $?L0036 ;[INF] 2, 4
|
||
663 663 ; line 155 : RWAIT = 0;
|
||
664 664 $DGL 0,16
|
||
665 665 000C4 710B9E clr1 RTCC1.0 ;[INF] 3, 2
|
||
666 666 000C7 ??eb00_rtc_unlock:
|
||
667 667 ; line 156 : }
|
||
668 668 000C7 ?L0032:
|
||
669 669 ; line 157 :
|
||
670 670 ; line 158 : // <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
671 671 ; line 159 : if( rtc_alarm_dirty )
|
||
672 672 $DGL 0,20
|
||
673 673 000C7 R31240013 bf _rtc_alarm_dirty,$?L0038 ;[INF] 4, 5
|
||
674 674 ; line 160 : {
|
||
675 675 000CB ??bb02_rtc_unlock:
|
||
676 676 ; line 161 : WALE = 0;
|
||
677 677 $DGL 0,22
|
||
678 678 000CB 717B9E clr1 RTCC1.7 ;[INF] 3, 2
|
||
679 679 ; line 162 : ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN];
|
||
680 680 $DGL 0,23
|
||
681 681 000CE R8F3800 mov a,!_vreg_ctr+56 ;[INF] 3, 1
|
||
682 682 000D1 9E9A mov ALARMWM,a ;[INF] 2, 1
|
||
683 683 ; line 163 : ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR];
|
||
684 684 $DGL 0,24
|
||
685 685 000D3 R8F3900 mov a,!_vreg_ctr+57 ;[INF] 3, 1
|
||
686 686 000D6 9E9B mov ALARMWH,a ;[INF] 2, 1
|
||
687 687 ; line 164 : rtc_dirty = 0;
|
||
688 688 $DGL 0,25
|
||
689 689 000D8 R711300 clr1 _rtc_dirty ;[INF] 3, 2
|
||
690 690 ; line 165 : WALE = 1;
|
||
691 691 $DGL 0,26
|
||
692 692 000DB 717A9E set1 RTCC1.7 ;[INF] 3, 2
|
||
693 693 000DE ??eb02_rtc_unlock:
|
||
694 694 ; line 166 : }
|
||
695 695 000DE ?L0038:
|
||
696 696 ; line 167 : }
|
||
697 697 $DGL 0,28
|
||
698 698 000DE ??ef_rtc_unlock:
|
||
699 699 000DE C6 pop hl ;[INF] 1, 1
|
||
700 700 000DF D7 ret ;[INF] 1, 6
|
||
701 701 000E0 ??ee_rtc_unlock:
|
||
702 702 ; line 168 :
|
||
703 703 ; line 169 :
|
||
704 704 ; line 170 :
|
||
705 705 ; line 171 :
|
||
706 706 ; line 172 :
|
||
707 707 ; line 173 : /* ========================================================
|
||
708 708 ; line 174 : RTC <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD>`<60>b<EFBFBD>N<EFBFBD>^<5E>C<EFBFBD>}<7D><><EFBFBD>荞<EFBFBD>݃x<DD83>N<EFBFBD>^
|
||
709 709 ; line 175 : 2^6/fXT<58>i1.953125 ms<6D>j
|
||
710 710 ; line 176 : ======================================================== */
|
||
711 711 ; line 177 : __interrupt void int_rtc_int( )
|
||
712 712 ; line 178 : {
|
||
713 713
|
||
714 714 ----- @@BASE CSEG BASE
|
||
715 715 0003E _int_rtc_int:
|
||
716 716 $DGL 1,147
|
||
717 717 0003E ??bf_int_rtc_int:
|
||
718 718 ; line 179 : renge_flg_interval = 1;
|
||
719 719 $DGL 0,2
|
||
720 720 0003E R710200 set1 _renge_flg_interval ;[INF] 3, 2
|
||
721 721 ; line 180 : }
|
||
722 722 $DGL 0,3
|
||
723 723 00041 ??ef_int_rtc_int:
|
||
724 724 00041 61FC reti ;[INF] 2, 6
|
||
725 725 00043 ??ee_int_rtc_int:
|
||
726 726
|
||
727 727 ----- @@CODEL CSEG
|
||
728 728 END
|
||
729 729
|
||
730 730
|
||
731 731 ; *** Code Information ***
|
||
732 732 ;
|
||
733 733 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c
|
||
734 734 ;
|
||
735 735 ; $FUNC RTC_init(23)
|
||
736 736 ; void=(void)
|
||
737 737 ; CODE SIZE= 87 bytes, CLOCK_SIZE= 57 clocks, STACK_SIZE= 2 bytes
|
||
738 738 ;
|
||
739 739 ; $FUNC int_rtc(72)
|
||
740 740 ; void=(void)
|
||
741 741 ; CODE SIZE= 62 bytes, CLOCK_SIZE= 47 clocks, STACK_SIZE= 2 bytes
|
||
742 742 ;
|
||
743 743 ; $FUNC rtc_buf_reflesh(99)
|
||
744 744 ; void=(void)
|
||
745 745 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 2 bytes
|
||
746 746 ;
|
||
747 747 ; $FUNC set_rtc(123)
|
||
748 748 ; void=(unsigned char adrs:x, unsigned char data:[sp+6])
|
||
749 749 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 4 bytes
|
||
750 750 ;
|
||
751 751 ; $FUNC rtc_unlock(140)
|
||
752 752 ; void=(void)
|
||
753 753 ; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 2 bytes
|
||
754 754 ;
|
||
755 755 ; $FUNC int_rtc_int(178)
|
||
756 756 ; void=(void)
|
||
757 757 ; CODE SIZE= 5 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes
|
||
758 758
|
||
759 759 ; Target chip : uPD79F0104
|
||
760 760 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.3 @@BITS
|
||
00000 00030H @@CNST
|
||
00000 00000H @@R_INIT
|
||
00000 00000H @@INIT
|
||
00000 00008H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H @@CNSTL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 000E0H ROM_CODE
|
||
00000 00043H @@BASE
|
||
00000 00000H @@CODEL
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|