mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
177 lines
9.8 KiB
Plaintext
177 lines
9.8 KiB
Plaintext
|
||
|
||
|
||
78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
|
||
|
||
|
||
|
||
Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\reboot.asm
|
||
Para-file:
|
||
In-file: inter_asm\reboot.asm
|
||
Obj-file: reboot.rel
|
||
Prn-file: reboot.prn
|
||
|
||
Assemble list
|
||
|
||
ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
|
||
|
||
1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:25
|
||
2 2
|
||
3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
|
||
4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
|
||
5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no reboot.c
|
||
6 6 ; In-file : reboot.c
|
||
7 7 ; Asm-file : inter_asm\reboot.asm
|
||
8 8 ; Para-file :
|
||
9 9
|
||
10 10 $PROCESSOR(9F0104)
|
||
11 11 $DEBUG
|
||
12 12 $NODEBUGA
|
||
13 13 $KANJICODE SJIS
|
||
14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
|
||
15 15
|
||
16 16 $DGS FIL_NAM, .file, 019H, 0FFFEH, 03FH, 067H, 01H, 00H
|
||
17 17 $DGS AUX_FIL, reboot.c
|
||
18 18 $DGS MOD_NAM, reboot, 00H, 0FFFEH, 00H, 077H, 00H, 00H
|
||
19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
|
||
20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
|
||
21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
|
||
22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
|
||
23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
|
||
24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
|
||
25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
|
||
26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
|
||
27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
|
||
28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
|
||
29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
|
||
30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
|
||
31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
|
||
32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
|
||
33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
|
||
34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
|
||
35 35 $DGS GLV_SYM, _my_reboot, U, U, 01H, 026H, 01H, 02H
|
||
36 36 $DGS AUX_FUN, 00H, U, U, 019H, 00H, 00H
|
||
37 37 $DGS BEG_FUN, ??bf_my_reboot, U, U, 00H, 065H, 01H, 00H
|
||
38 38 $DGS AUX_BEG, 0EH, 00H, 019H
|
||
39 39 $DGS END_FUN, ??ef_my_reboot, U, U, 00H, 065H, 01H, 00H
|
||
40 40 $DGS AUX_END, 0BH
|
||
41 41
|
||
42 42 PUBLIC _my_reboot
|
||
43 43
|
||
44 44 ----- @@BITS BSEG
|
||
45 45
|
||
46 46 ----- @@CNST CSEG MIRRORP
|
||
47 47
|
||
48 48 ----- @@R_INIT CSEG UNIT64KP
|
||
49 49
|
||
50 50 ----- @@INIT DSEG BASEP
|
||
51 51
|
||
52 52 ----- @@DATA DSEG BASEP
|
||
53 53
|
||
54 54 ----- @@R_INIS CSEG UNIT64KP
|
||
55 55
|
||
56 56 ----- @@INIS DSEG SADDRP
|
||
57 57
|
||
58 58 ----- @@DATS DSEG SADDRP
|
||
59 59
|
||
60 60 ----- LDR_CNSL CSEG PAGE64KP
|
||
61 61
|
||
62 62 ----- @@RLINIT CSEG UNIT64KP
|
||
63 63
|
||
64 64 ----- @@INITL DSEG UNIT64KP
|
||
65 65
|
||
66 66 ----- @@DATAL DSEG UNIT64KP
|
||
67 67
|
||
68 68 ----- @@CALT CSEG CALLT0
|
||
69 69
|
||
70 70 ; line 1 : /********************************************************//*
|
||
71 71 ; line 2 :
|
||
72 72 ; line 3 : <20>ނ<EFBFBD><DE82><EFBFBD><EFBFBD>胊<EFBFBD>u<EFBFBD>[<5B>g
|
||
73 73 ; line 4 :
|
||
74 74 ; line 5 : <20>t<EFBFBD>@<40>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>ɃC<C983><43><EFBFBD><EFBFBD><EFBFBD>C<EFBFBD><43><EFBFBD>A<EFBFBD>Z<EFBFBD><5A><EFBFBD>u<EFBFBD><75><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƁA
|
||
75 75 ; line 6 : <20><><EFBFBD>̃<EFBFBD><CC83>W<EFBFBD><57><EFBFBD>[<5B><><EFBFBD>S<EFBFBD><53><EFBFBD>œK<C593><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>Ȃ邽<C882>ߒǂ<DF92><C782>o<EFBFBD><6F><EFBFBD><EFBFBD>
|
||
76 76 ; line 7 :
|
||
77 77 ; line 8 : **********************************************************/
|
||
78 78 ; line 9 : #pragma SFR
|
||
79 79 ; line 10 :
|
||
80 80 ; line 11 : #include "incs_loader.h"
|
||
81 81 ; line 12 :
|
||
82 82 ; line 13 :
|
||
83 83 ; line 14 : void my_reboot(){
|
||
84 84
|
||
85 85 ----- LDR_CODE CSEG BASE
|
||
86 86 00000 _my_reboot:
|
||
87 87 $DGL 1,19
|
||
88 88 00000 ??bf_my_reboot:
|
||
89 89 ; line 15 : #asm
|
||
90 90
|
||
91 91 $DGL 0,4
|
||
92 92 00000 CEFA06 MOV PSW,#06H ; <20>_<EFBFBD>~<7E>[<5B><>PSW<53><57><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
93 93 $DGL 0,5
|
||
94 94 00003 30D000 MOVW AX,#000d0h ; <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD>̃x<CC83>N<EFBFBD>^<5E>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E><EFBFBD>ł<EFBFBD><C582>܂<EFBFBD><DC82>B
|
||
95 95 $DGL 0,6
|
||
96 96 00006 61DD PUSH PSW
|
||
97 97 $DGL 0,7
|
||
98 98 00008 C1 PUSH AX ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RETI<54>̂<EFBFBD><CC82>߂̃X<CC83>^<5E>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
99 99 $DGL 0,8
|
||
100 100 00009 61FC RETI ; <20><><EFBFBD><EFBFBD><EFBFBD>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g<EFBFBD>E<EFBFBD>x<EFBFBD>N<EFBFBD>^<5E>ɕ<EFBFBD><C995><EFBFBD>
|
||
101 101
|
||
102 102 ; line 16 :
|
||
103 103 ; line 17 : MOV PSW,#06H ; <20>_<EFBFBD>~<7E>[<5B><>PSW<53><57><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
104 104 ; line 18 : MOVW AX,#000d0h ; <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD>̃x<CC83>N<EFBFBD>^<5E>l<EFBFBD><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
105 105 ; <20><><EFBFBD><EFBFBD><EFBFBD>ł<EFBFBD><C582>܂<EFBFBD><DC82>B
|
||
106 106 ; line 19 : PUSH PSW
|
||
107 107 ; line 20 : PUSH AX ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RETI<54>̂<EFBFBD><CC82>߂̃X<CC83>^<5E>b<EFBFBD>N
|
||
108 108 ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
109 109 ; line 21 : RETI ; <20><><EFBFBD><EFBFBD><EFBFBD>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g<EFBFBD>E<EFBFBD>x<EFBFBD>N<EFBFBD>^<5E>ɕ<EFBFBD>
|
||
110 110 ; <20><>
|
||
111 111 ; line 22 :
|
||
112 112 ; line 23 : #endasm
|
||
113 113 ; line 24 : }
|
||
114 114 $DGL 0,11
|
||
115 115 0000B ??ef_my_reboot:
|
||
116 116 0000B D7 ret ;[INF] 1, 6
|
||
117 117 0000C ??ee_my_reboot:
|
||
118 118
|
||
119 119 ----- LDR_CODL CSEG
|
||
120 120
|
||
121 121 ----- @@BASE CSEG BASE
|
||
122 122 END
|
||
123 123
|
||
124 124
|
||
125 125 ; *** Code Information ***
|
||
126 126 ;
|
||
127 127 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\reboot.c
|
||
128 128 ;
|
||
129 129 ; $FUNC my_reboot(14)
|
||
130 130 ; void=(void)
|
||
131 131 ; CODE SIZE= 1 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
132 132
|
||
133 133 ; Target chip : uPD79F0104
|
||
134 134 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.0 @@BITS
|
||
00000 00000H @@CNST
|
||
00000 00000H @@R_INIT
|
||
00000 00000H @@INIT
|
||
00000 00000H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H LDR_CNSL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 0000CH LDR_CODE
|
||
00000 00000H LDR_CODL
|
||
00000 00000H @@BASE
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|