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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
568 lines
40 KiB
Plaintext
568 lines
40 KiB
Plaintext
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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
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Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\main.asm
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Para-file:
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In-file: inter_asm\main.asm
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Obj-file: main.rel
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Prn-file: main.prn
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Assemble list
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ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
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1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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2 2
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3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no main.c
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6 6 ; In-file : main.c
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7 7 ; Asm-file : inter_asm\main.asm
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8 8 ; Para-file :
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9 9
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10 10 $PROCESSOR(9F0104)
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11 11 $DEBUG
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12 12 $NODEBUGA
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13 13 $KANJICODE SJIS
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14 14 $TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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15 15
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16 16 $DGS FIL_NAM, .file, 063H, 0FFFEH, 03FH, 067H, 01H, 00H
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17 17 $DGS AUX_FIL, main.c
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18 18 $DGS MOD_NAM, main, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
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28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
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33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
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34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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36 36 $DGS AUX_TAG, 01H, 01EH
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37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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45 45 $DGS AUX_EOS, 013H, 01H
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46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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47 47 $DGS AUX_TAG, 01H, 025H
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48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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52 52 $DGS AUX_EOS, 01EH, 01H
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53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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54 54 $DGS AUX_TAG, 01H, 02FH
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55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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62 62 $DGS AUX_EOS, 025H, 01H
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63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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64 64 $DGS AUX_TAG, 04H, 041H
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65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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70 70 $DGS AUX_BIT, 00H, 01H
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71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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72 72 $DGS AUX_BIT, 00H, 01H
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73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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74 74 $DGS AUX_BIT, 00H, 01H
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75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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76 76 $DGS AUX_BIT, 00H, 01H
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77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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80 80 $DGS AUX_EOS, 02FH, 04H
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81 81 $DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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82 82 $DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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83 83 $DGS GLV_SYM, _main_loop, U, U, 01H, 026H, 01H, 02H
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84 84 $DGS AUX_FUN, 00H, U, U, 05DH, 00H, 00H
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85 85 $DGS BEG_FUN, ??bf_main_loop, U, U, 00H, 065H, 01H, 00H
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86 86 $DGS AUX_BEG, 021H, 00H, 047H
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87 87 $DGS BEG_BLK, ??bb00_main_loop, U, U, 00H, 064H, 01H, 00H
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88 88 $DGS AUX_BEG, 0EH, 00H, 049H
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89 89 $DGS BEG_BLK, ??bb01_main_loop, U, U, 00H, 064H, 01H, 00H
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90 90 $DGS AUX_BEG, 014H, 00H, 04FH
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91 91 $DGS END_BLK, ??eb01_main_loop, U, U, 00H, 064H, 01H, 00H
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92 92 $DGS AUX_END, 016H
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93 93 $DGS END_BLK, ??eb00_main_loop, U, U, 00H, 064H, 01H, 00H
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94 94 $DGS AUX_END, 017H
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95 95 $DGS BEG_BLK, ??bb02_main_loop, U, U, 00H, 064H, 01H, 00H
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96 96 $DGS AUX_BEG, 019H, 00H, 053H
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97 97 $DGS END_BLK, ??eb02_main_loop, U, U, 00H, 064H, 01H, 00H
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98 98 $DGS AUX_END, 01CH
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99 99 $DGS BEG_BLK, ??bb03_main_loop, U, U, 00H, 064H, 01H, 00H
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100 100 $DGS AUX_BEG, 02EH, 00H, 055H
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101 101 $DGS BEG_BLK, ??bb04_main_loop, U, U, 00H, 064H, 01H, 00H
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102 102 $DGS AUX_BEG, 032H, 00H, 00H
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103 103 $DGS END_BLK, ??eb04_main_loop, U, U, 00H, 064H, 01H, 00H
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104 104 $DGS AUX_END, 034H
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105 105 $DGS END_BLK, ??eb03_main_loop, U, U, 00H, 064H, 01H, 00H
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106 106 $DGS AUX_END, 038H
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107 107 $DGS END_FUN, ??ef_main_loop, U, U, 00H, 065H, 01H, 00H
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108 108 $DGS AUX_END, 039H
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109 109 $DGS STA_SYM, _read_dipsw, U, U, 01H, 03H, 01H, 02H
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110 110 $DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H
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111 111 $DGS BEG_FUN, ??bf_read_dipsw, U, U, 00H, 065H, 01H, 00H
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112 112 $DGS AUX_BEG, 05FH, 00H, 063H
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113 113 $DGS END_FUN, ??ef_read_dipsw, U, U, 00H, 065H, 01H, 00H
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114 114 $DGS AUX_END, 07H
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115 115 $DGS GLV_SYM, _system_status, U, U, 08H, 026H, 01H, 00H
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116 116 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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117 117 $DGS GLV_SYM, _update, U, U, 034CH, 027H, 00H, 00H
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118 118 $DGS GLV_SYM, _pool, U, U, 0DH, 026H, 01H, 03H
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119 119 $DGS AUX_STR, 00H, 00H, 0200H, 0100H, 00H, 00H, 00H, 00H
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120 120 $DGS GLV_SYM, _RTC_init, U, U, 01H, 02H, 01H, 02H
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121 121 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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122 122 $DGS GLV_SYM, _renge_init, U, U, 01H, 02H, 01H, 02H
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123 123 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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124 124 $DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H
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125 125 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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126 126 $DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H
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127 127 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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128 128 $DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
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129 129 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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130 130 $DGS GLV_SYM, _vreg_ctr_init, U, U, 01H, 02H, 01H, 02H
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131 131 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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132 132 $DGS GLV_SYM, _vreg_twl_init, U, U, 01H, 02H, 01H, 02H
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133 133 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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134 134 $DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 02H, 01H, 02H
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135 135 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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136 136 $DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H
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137 137 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
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138 138 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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139 139 $DGS GLV_SYM, _renge_task_interval_run, U, U, 0CH, 02H, 01H, 02H
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140 140 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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141 141 $DGS GLV_SYM, _renge_task_immed_run, U, U, 0CH, 02H, 01H, 02H
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142 142 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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143 143
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144 144 EXTRN _RTC_init
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145 145 EXTRN _renge_init
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146 146 EXTRN _iic_mcu_start
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147 147 EXTRN _PM_init
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148 148 EXTRN _iic_mcu_read_a_byte
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149 149 EXTRN _vreg_ctr_init
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150 150 EXTRN _vreg_twl_init
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151 151 EXTRN _clear_hosu_hist
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152 152 EXTRN _WDT_Restart
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153 153 EXTRN _renge_task_interval_run
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154 154 EXTRN _renge_task_immed_run
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155 155 EXTBIT _renge_task_interval_run_force
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156 156 PUBLIC _system_status
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157 157 PUBLIC _update
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158 158 PUBLIC _pool
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159 159 PUBLIC _main_loop
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160 160
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161 161 ----- @@BITS BSEG
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162 162 00000.0 _update DBIT
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163 163
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164 164 ----- @@CNST CSEG MIRRORP
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165 165 00000 01 _lpf_coeff: DB 01H ; 1
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166 166 00001 02 DB 02H ; 2
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167 167 00002 02 DB 02H ; 2
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168 168 00003 03 DB 03H ; 3
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169 169 00004 03 DB 03H ; 3
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170 170 00005 02 DB 02H ; 2
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171 171 00006 00 DB 00H ; 0
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172 172 00007 FE DB 0FEH ; 254
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173 173 00008 FB DB 0FBH ; 251
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174 174 00009 F7 DB 0F7H ; 247
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175 175 0000A F3 DB 0F3H ; 243
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176 176 0000B F0 DB 0F0H ; 240
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177 177 0000C F0 DB 0F0H ; 240
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178 178 0000D F3 DB 0F3H ; 243
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179 179 0000E FA DB 0FAH ; 250
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180 180 0000F 04 DB 04H ; 4
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181 181 00010 12 DB 012H ; 18
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182 182 00011 25 DB 025H ; 37
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183 183 00012 38 DB 038H ; 56
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184 184 00013 4D DB 04DH ; 77
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185 185 00014 5F DB 05FH ; 95
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186 186 00015 6E DB 06EH ; 110
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187 187 00016 77 DB 077H ; 119
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188 188 00017 7A DB 07AH ; 122
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189 189 00018 77 DB 077H ; 119
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190 190 00019 6E DB 06EH ; 110
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191 191 0001A 5F DB 05FH ; 95
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192 192 0001B 4D DB 04DH ; 77
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193 193 0001C 38 DB 038H ; 56
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194 194 0001D 25 DB 025H ; 37
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195 195 0001E 12 DB 012H ; 18
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196 196 0001F 04 DB 04H ; 4
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197 197 00020 FA DB 0FAH ; 250
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198 198 00021 F3 DB 0F3H ; 243
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199 199 00022 F0 DB 0F0H ; 240
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200 200 00023 F0 DB 0F0H ; 240
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201 201 00024 F3 DB 0F3H ; 243
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202 202 00025 F7 DB 0F7H ; 247
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203 203 00026 FB DB 0FBH ; 251
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204 204 00027 FE DB 0FEH ; 254
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205 205 00028 00 DB 00H ; 0
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206 206 00029 02 DB 02H ; 2
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207 207 0002A 03 DB 03H ; 3
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208 208 0002B 03 DB 03H ; 3
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209 209 0002C 02 DB 02H ; 2
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210 210 0002D 02 DB 02H ; 2
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211 211 0002E 01 DB 01H ; 1
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212 212 0002F 00 DB (1)
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213 213
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214 214 ----- @@R_INIT CSEG UNIT64KP
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215 215
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216 216 ----- @@INIT DSEG BASEP
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217 217
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218 218 ----- @@DATA DSEG BASEP
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219 219 00000 _system_status: DS (4)
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220 220 00004 _pool: DS (512)
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221 221
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222 222 ----- @@R_INIS CSEG UNIT64KP
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223 223
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224 224 ----- @@INIS DSEG SADDRP
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225 225
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226 226 ----- @@DATS DSEG SADDRP
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227 227
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228 228 ----- LDR_CNSL CSEG PAGE64KP
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229 229
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230 230 ----- @@RLINIT CSEG UNIT64KP
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231 231
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232 232 ----- @@INITL DSEG UNIT64KP
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233 233
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234 234 ----- @@DATAL DSEG UNIT64KP
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235 235
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236 236 ----- @@CALT CSEG CALLT0
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237 237
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238 238 ; line 1 : /* ========================================================
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239 239 ; line 2 : MCU CTR BSR
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240 240 ; line 3 : 2008,2009 nintendo
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241 241 ; line 4 : <20>J<EFBFBD><4A><EFBFBD>Z<EFBFBD>p<EFBFBD><70><EFBFBD>@<40><><EFBFBD>c
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242 242 ; line 5 : ======================================================== */
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243 243 ; line 6 :
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244 244 ; line 7 :
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245 245 ; line 8 : // ========================================================
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246 246 ; line 9 : #include "incs_loader.h"
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247 247 ; line 10 :
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248 248 ; line 11 : #include "WDT.h"
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249 249 ; line 12 : #include "rtc.h"
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250 250 ; line 13 : #include "pm.h"
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251 251 ; line 14 : #include "accero.h"
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252 252 ; line 15 : #include "led.h"
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253 253 ; line 16 : #include "adc.h"
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254 254 ; line 17 :
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255 255 ; line 18 :
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256 256 ; line 19 : // ========================================================
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257 257 ; line 20 : static void read_dipsw( );
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258 258 ; line 21 :
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259 259 ; line 22 :
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260 260 ; line 23 : // ========================================================
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261 261 ; line 24 : system_status_ system_status;
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262 262 ; line 25 : bit update;
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263 263 ; line 26 :
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264 264 ; line 27 :
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265 265 ; line 28 : u16 pool[256]; // <20>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>̃<EFBFBD><CC83>[<5B>N<EFBFBD>G<EFBFBD><47><EFBFBD>A
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266 266 ; <20><> <20><><EFBFBD><EFBFBD><EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^
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267 267 ; line 29 : /* ========================================================
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268 268 ; line 30 : <20>{<7B><><EFBFBD>̃G<CC83><47><EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><D690><EFBFBD> loader.c <20>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>܂<EFBFBD>
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269 269 ; line 31 : ======================================================== */
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270 270 ; line 32 : void main_loop( void )
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271 271 ; line 33 : {
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272 272
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273 273 ----- LDR_CODE CSEG BASE
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274 274 00000 _main_loop:
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275 275 $DGL 1,67
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276 276 00000 ??bf_main_loop:
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277 277 ; line 34 :
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278 278 ; line 35 : // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>̂<EFBFBD>
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279 279 ; line 36 : RTC_init( ); // <20><><EFBFBD><EFBFBD><EFBFBD>Ń<EFBFBD><C583>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>肵<EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD>
|
||
280 280 $DGL 0,4
|
||
281 281 00000 RFD0000 call !_RTC_init ;[INF] 3, 3
|
||
282 282 ; line 37 :
|
||
283 283 ; line 38 : renge_init( );
|
||
284 284 $DGL 0,6
|
||
285 285 00003 RFD0000 call !_renge_init ;[INF] 3, 3
|
||
286 286 ; line 39 :
|
||
287 287 ; line 40 : iic_mcu_start( );
|
||
288 288 $DGL 0,8
|
||
289 289 00006 RFD0000 call !_iic_mcu_start ;[INF] 3, 3
|
||
290 290 ; line 41 : EI( );
|
||
291 291 $DGL 0,9
|
||
292 292 00009 717AFA ei ;[INF] 3, 4
|
||
293 293 ; line 42 :
|
||
294 294 ; line 43 : PM_init();
|
||
295 295 $DGL 0,11
|
||
296 296 0000C RFD0000 call !_PM_init ;[INF] 3, 3
|
||
297 297 ; line 44 :
|
||
298 298 ; line 45 : if( system_status.reboot )
|
||
299 299 $DGL 0,13
|
||
300 300 0000F R8F0200 mov a,!_system_status+2 ;[INF] 3, 1
|
||
301 301 00012 313516 bf a.3,$?L0003 ;[INF] 3, 5
|
||
302 302 ; line 46 : {
|
||
303 303 00015 ??bb00_main_loop:
|
||
304 304 ; line 47 : #ifdef _PMIC_TWL_
|
||
305 305 ; line 48 : if( RESET1_n )
|
||
306 306 ; line 49 : #else
|
||
307 307 ; line 50 : if( PM_chk_LDSW() != 0 )
|
||
308 308 $DGL 0,18
|
||
309 309 00015 300300 movw ax,#03H ; 3 ;[INF] 3, 1
|
||
310 310 00018 C1 push ax ;[INF] 1, 1
|
||
311 311 00019 5084 mov x,#084H ; 132 ;[INF] 2, 1
|
||
312 312 0001B RFD0000 call !_iic_mcu_read_a_byte ;[INF] 3, 3
|
||
313 313 0001E C0 pop ax ;[INF] 1, 1
|
||
314 314 0001F 62 mov a,c ;[INF] 1, 1
|
||
315 315 00020 5C01 and a,#01H ; 1 ;[INF] 2, 1
|
||
316 316 00022 D1 cmp0 a ;[INF] 1, 1
|
||
317 317 00023 DD09 bz $?L0004 ;[INF] 2, 4
|
||
318 318 ; line 51 : #endif
|
||
319 319 ; line 52 : {
|
||
320 320 00025 ??bb01_main_loop:
|
||
321 321 ; line 53 : system_status.pwr_state = ON_TRIG;
|
||
322 322 $DGL 0,21
|
||
323 323 00025 RCF000002 mov !_system_status,#02H ; 2 ;[INF] 4, 1
|
||
324 324 00029 ??eb01_main_loop:
|
||
325 325 ; line 54 : }
|
||
326 326 ; line 55 : }
|
||
327 327 $DGL 0,23
|
||
328 328 00029 ??eb00_main_loop:
|
||
329 329 00029 EF03 br $?L0004 ;[INF] 2, 3
|
||
330 330 0002B ?L0003:
|
||
331 331 ; line 56 : else
|
||
332 332 ; line 57 : {
|
||
333 333 0002B ??bb02_main_loop:
|
||
334 334 ; line 58 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>͎<EFBFBD><CD8E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
335 335 ; line 59 : system_status.pwr_state = OFF_TRIG;
|
||
336 336 $DGL 0,27
|
||
337 337 0002B RF50000 clrb !_system_status ;[INF] 3, 1
|
||
338 338 0002E ??eb02_main_loop:
|
||
339 339 ; line 60 : }
|
||
340 340 0002E ?L0004:
|
||
341 341 ; line 61 :
|
||
342 342 ; line 62 : #ifdef _PARRADIUM_
|
||
343 343 ; line 63 : system_status.pwr_state = OFF;
|
||
344 344 ; line 64 : #endif
|
||
345 345 ; line 65 : vreg_ctr_init( );
|
||
346 346 $DGL 0,33
|
||
347 347 0002E RFD0000 call !_vreg_ctr_init ;[INF] 3, 3
|
||
348 348 ; line 66 : vreg_twl_init( );
|
||
349 349 $DGL 0,34
|
||
350 350 00031 RFD0000 call !_vreg_twl_init ;[INF] 3, 3
|
||
351 351 ; line 67 :
|
||
352 352 ; line 68 : read_dipsw( ); // <20><><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>ʼn<EFBFBD><C589><EFBFBD><EFBFBD><EFBFBD><EFBFBD>邩<EFBFBD>H
|
||
353 353 $DGL 0,36
|
||
354 354 00034 RFD5D00 call !_read_dipsw ;[INF] 3, 3
|
||
355 355 ; line 69 :
|
||
356 356 ; line 70 : clear_hosu_hist(); // <20><><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD>A
|
||
357 357 $DGL 0,38
|
||
358 358 00037 RFD0000 call !_clear_hosu_hist ;[INF] 3, 3
|
||
359 359 ; line 71 :
|
||
360 360 ; line 72 : renge_task_interval_run_force = 1;
|
||
361 361 $DGL 0,40
|
||
362 362 0003A R710200 set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
363 363 ; line 73 :
|
||
364 364 ; line 74 : RTCIMK = 0; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28>A<EFBFBD><41><EFBFBD>[<5B><>&<26>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>
|
||
365 365 ; )<29><><EFBFBD><EFBFBD> */
|
||
366 366 $DGL 0,42
|
||
367 367 0003D 712BE7 clr1 MK1H.2 ;[INF] 3, 2
|
||
368 368 ; line 75 :
|
||
369 369 ; line 76 : // <20><><EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>[<5B>v //
|
||
370 370 ; line 77 : while( 1 )
|
||
371 371 00040 ?L0007:
|
||
372 372 ; line 78 : { // <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65>tick<63>A<EFBFBD>܂<EFBFBD><DC82>͊<EFBFBD><CD8A>荞<EFBFBD>݂<EFBFBD>
|
||
373 373 ; <20><><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
374 374 00040 ??bb03_main_loop:
|
||
375 375 ; line 79 : WDT_Restart( );
|
||
376 376 $DGL 0,47
|
||
377 377 00040 RFD0000 call !_WDT_Restart ;[INF] 3, 3
|
||
378 378 ; line 80 : renge_task_interval_run( ); // <20><><EFBFBD><EFBFBD><EFBFBD>ŁA<C581>V<EFBFBD>X<EFBFBD>e<EFBFBD><65>tick<63><6B>
|
||
379 379 ; <20><><EFBFBD>͋<EFBFBD><CD8B><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
380 380 $DGL 0,48
|
||
381 381 00043 RFD0000 call !_renge_task_interval_run ;[INF] 3, 3
|
||
382 382 ; line 81 : while( renge_task_interval_run_force != 0 )
|
||
383 383 $DGL 0,49
|
||
384 384 00046 ?L0009:
|
||
385 385 00046 R31040005 bf _renge_task_interval_run_force,$?L0010 ;[INF] 4, 5
|
||
386 386 ; line 82 : {
|
||
387 387 0004A ??bb04_main_loop:
|
||
388 388 ; line 83 : renge_task_interval_run( );
|
||
389 389 $DGL 0,51
|
||
390 390 0004A RFD0000 call !_renge_task_interval_run ;[INF] 3, 3
|
||
391 391 0004D ??eb04_main_loop:
|
||
392 392 ; line 84 : }
|
||
393 393 $DGL 0,52
|
||
394 394 0004D EFF7 br $?L0009 ;[INF] 2, 3
|
||
395 395 0004F ?L0010:
|
||
396 396 ; line 85 : WDT_Restart( );
|
||
397 397 $DGL 0,53
|
||
398 398 0004F RFD0000 call !_WDT_Restart ;[INF] 3, 3
|
||
399 399 ; line 86 : while( renge_task_immed_run( ) != ERR_SUCCESS );
|
||
400 400 ; // <20><><EFBFBD><EFBFBD><EFBFBD>̃<EFBFBD><CC83>[<5B>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Ɏ<EFBFBD><C98E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
401 401 $DGL 0,54
|
||
402 402 00052 ?L0011:
|
||
403 403 00052 RFD0000 call !_renge_task_immed_run ;[INF] 3, 3
|
||
404 404 00055 D2 cmp0 c ;[INF] 1, 1
|
||
405 405 00056 DFFA bnz $?L0011 ;[INF] 2, 4
|
||
406 406 ; line 87 : HALT( );
|
||
407 407 $DGL 0,55
|
||
408 408 00058 61ED halt ;[INF] 2, 3
|
||
409 409 0005A ??eb03_main_loop:
|
||
410 410 ; line 88 : }
|
||
411 411 $DGL 0,56
|
||
412 412 0005A EFE4 br $?L0007 ;[INF] 2, 3
|
||
413 413 ; line 89 : }
|
||
414 414 $DGL 0,57
|
||
415 415 0005C ??ef_main_loop:
|
||
416 416 0005C D7 ret ;[INF] 1, 6
|
||
417 417 0005D ??ee_main_loop:
|
||
418 418 ; line 90 :
|
||
419 419 ; line 91 :
|
||
420 420 ; line 92 : /* ========================================================
|
||
421 421 ; line 93 : ======================================================== */
|
||
422 422 ; line 94 : static void read_dipsw( )
|
||
423 423 ; line 95 : {
|
||
424 424 0005D _read_dipsw:
|
||
425 425 $DGL 1,93
|
||
426 426 0005D ??bf_read_dipsw:
|
||
427 427 ; line 96 : // <20>\<5C>t<EFBFBD>g<EFBFBD>f<EFBFBD>B<EFBFBD>b<EFBFBD>v<EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>ǂݍ<C782><DD8D><EFBFBD>
|
||
428 428 ; line 97 : // PU4 |= 0x03; // dip sw 0,1
|
||
429 429 ; line 98 : system_status.dipsw0 = ( DIPSW_0 == 0 ) ? 0 : 1;
|
||
430 430 $DGL 0,4
|
||
431 431 0005D 31020403 bt P4.0,$?L0015 ;[INF] 4, 5
|
||
432 432 00061 F6 clrw ax ;[INF] 1, 1
|
||
433 433 00062 EF01 br $?L0016 ;[INF] 2, 3
|
||
434 434 00064 ?L0015:
|
||
435 435 00064 E6 onew ax ;[INF] 1, 1
|
||
436 436 00065 ?L0016:
|
||
437 437 00065 60 mov a,x ;[INF] 1, 1
|
||
438 438 00066 R340200 movw de,#loww (_system_status+2) ;[INF] 3, 1
|
||
439 439 00069 718C mov1 CY,a.0 ;[INF] 2, 1
|
||
440 440 0006B 89 mov a,[de] ;[INF] 1, 1
|
||
441 441 0006C 7189 mov1 a.0,CY ;[INF] 2, 1
|
||
442 442 0006E 99 mov [de],a ;[INF] 1, 1
|
||
443 443 ; line 99 : system_status.dipsw1 = ( DIPSW_1 == 0 ) ? 0 : 1;
|
||
444 444 $DGL 0,5
|
||
445 445 0006F 31120403 bt P4.1,$?L0017 ;[INF] 4, 5
|
||
446 446 00073 F6 clrw ax ;[INF] 1, 1
|
||
447 447 00074 EF01 br $?L0018 ;[INF] 2, 3
|
||
448 448 00076 ?L0017:
|
||
449 449 00076 E6 onew ax ;[INF] 1, 1
|
||
450 450 00077 ?L0018:
|
||
451 451 00077 60 mov a,x ;[INF] 1, 1
|
||
452 452 00078 R340200 movw de,#loww (_system_status+2) ;[INF] 3, 1
|
||
453 453 0007B 718C mov1 CY,a.0 ;[INF] 2, 1
|
||
454 454 0007D 89 mov a,[de] ;[INF] 1, 1
|
||
455 455 0007E 7199 mov1 a.1,CY ;[INF] 2, 1
|
||
456 456 00080 99 mov [de],a ;[INF] 1, 1
|
||
457 457 ; line 100 : // PU4 &= ~0x03;
|
||
458 458 ; line 101 : }
|
||
459 459 $DGL 0,7
|
||
460 460 00081 ??ef_read_dipsw:
|
||
461 461 00081 D7 ret ;[INF] 1, 6
|
||
462 462 00082 ??ee_read_dipsw:
|
||
463 463
|
||
464 464 ----- LDR_CODL CSEG
|
||
465 465
|
||
466 466 ----- @@BASE CSEG BASE
|
||
467 467 END
|
||
468 468
|
||
469 469
|
||
470 470 ; *** Code Information ***
|
||
471 471 ;
|
||
472 472 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c
|
||
473 473 ;
|
||
474 474 ; $FUNC main_loop(33)
|
||
475 475 ; void=(void)
|
||
476 476 ; CODE SIZE= 93 bytes, CLOCK_SIZE= 97 clocks, STACK_SIZE= 6 bytes
|
||
477 477 ;
|
||
478 478 ; $CALL RTC_init(36)
|
||
479 479 ; void=(void)
|
||
480 480 ;
|
||
481 481 ; $CALL renge_init(38)
|
||
482 482 ; void=(void)
|
||
483 483 ;
|
||
484 484 ; $CALL iic_mcu_start(40)
|
||
485 485 ; void=(void)
|
||
486 486 ;
|
||
487 487 ; $CALL PM_init(43)
|
||
488 488 ; void=(void)
|
||
489 489 ;
|
||
490 490 ; $CALL iic_mcu_read_a_byte(50)
|
||
491 491 ; bc=(int:ax, int:[sp+4])
|
||
492 492 ;
|
||
493 493 ; $CALL vreg_ctr_init(65)
|
||
494 494 ; void=(void)
|
||
495 495 ;
|
||
496 496 ; $CALL vreg_twl_init(66)
|
||
497 497 ; void=(void)
|
||
498 498 ;
|
||
499 499 ; $CALL read_dipsw(68)
|
||
500 500 ; void=(void)
|
||
501 501 ;
|
||
502 502 ; $CALL clear_hosu_hist(70)
|
||
503 503 ; void=(void)
|
||
504 504 ;
|
||
505 505 ; $CALL WDT_Restart(79)
|
||
506 506 ; void=(void)
|
||
507 507 ;
|
||
508 508 ; $CALL renge_task_interval_run(80)
|
||
509 509 ; bc=(void)
|
||
510 510 ;
|
||
511 511 ; $CALL renge_task_interval_run(83)
|
||
512 512 ; bc=(void)
|
||
513 513 ;
|
||
514 514 ; $CALL WDT_Restart(85)
|
||
515 515 ; void=(void)
|
||
516 516 ;
|
||
517 517 ; $CALL renge_task_immed_run(86)
|
||
518 518 ; bc=(void)
|
||
519 519 ;
|
||
520 520 ; $FUNC read_dipsw(95)
|
||
521 521 ; void=(void)
|
||
522 522 ; CODE SIZE= 37 bytes, CLOCK_SIZE= 38 clocks, STACK_SIZE= 0 bytes
|
||
523 523
|
||
524 524 ; Target chip : uPD79F0104
|
||
525 525 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.1 @@BITS
|
||
00000 00030H @@CNST
|
||
00000 00000H @@R_INIT
|
||
00000 00000H @@INIT
|
||
00000 00204H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H LDR_CNSL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 00082H LDR_CODE
|
||
00000 00000H LDR_CODL
|
||
00000 00000H @@BASE
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|