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git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
1087 lines
79 KiB
Plaintext
1087 lines
79 KiB
Plaintext
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78K0R Assembler W1.31 Date:13 Jun 2010 Page: 1
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Command: -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff inter_asm\loader.asm
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Para-file:
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In-file: inter_asm\loader.asm
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Obj-file: loader.rel
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Prn-file: loader.prn
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Assemble list
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ALNO STNO ADRS OBJECT M I SOURCE STATEMENT
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1 1 ; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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2 2
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3 3 ; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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4 4 ; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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5 5 ; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no loader.c
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6 6 ; In-file : loader.c
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7 7 ; Asm-file : inter_asm\loader.asm
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8 8 ; Para-file :
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9 9
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10 10 $PROCESSOR(9F0104)
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11 11 $DEBUG
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12 12 $NODEBUGA
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13 13 $KANJICODE SJIS
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14 14 $TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
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15 15
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16 16 $DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H
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17 17 $DGS AUX_FIL, loader.c
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18 18 $DGS MOD_NAM, loader, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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19 19 $DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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20 20 $DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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21 21 $DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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22 22 $DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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23 23 $DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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24 24 $DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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25 25 $DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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26 26 $DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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27 27 $DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
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28 28 $DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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29 29 $DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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30 30 $DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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31 31 $DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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32 32 $DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
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33 33 $DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
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34 34 $DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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35 35 $DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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36 36 $DGS AUX_TAG, 01H, 01EH
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37 37 $DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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38 38 $DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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39 39 $DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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40 40 $DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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41 41 $DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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42 42 $DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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43 43 $DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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44 44 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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45 45 $DGS AUX_EOS, 013H, 01H
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46 46 $DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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47 47 $DGS AUX_TAG, 01H, 025H
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48 48 $DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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49 49 $DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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50 50 $DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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51 51 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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52 52 $DGS AUX_EOS, 01EH, 01H
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53 53 $DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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54 54 $DGS AUX_TAG, 01H, 02FH
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55 55 $DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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56 56 $DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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57 57 $DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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58 58 $DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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59 59 $DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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60 60 $DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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61 61 $DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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62 62 $DGS AUX_EOS, 025H, 01H
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63 63 $DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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64 64 $DGS AUX_TAG, 04H, 041H
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65 65 $DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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66 66 $DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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67 67 $DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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68 68 $DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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69 69 $DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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70 70 $DGS AUX_BIT, 00H, 01H
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71 71 $DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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72 72 $DGS AUX_BIT, 00H, 01H
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73 73 $DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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74 74 $DGS AUX_BIT, 00H, 01H
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75 75 $DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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76 76 $DGS AUX_BIT, 00H, 01H
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77 77 $DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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78 78 $DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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79 79 $DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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80 80 $DGS AUX_EOS, 02FH, 04H
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81 81 $DGS GLV_SYM, _main, U, U, 01H, 026H, 01H, 02H
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82 82 $DGS AUX_FUN, 00H, U, U, 073H, 00H, 00H
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83 83 $DGS BEG_FUN, ??bf_main, U, U, 00H, 065H, 01H, 00H
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84 84 $DGS AUX_BEG, 045H, 02H, 045H
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85 85 $DGS BEG_BLK, ??bb00_main, U, U, 00H, 064H, 01H, 00H
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86 86 $DGS AUX_BEG, 03H, 00H, 047H
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87 87 $DGS BEG_BLK, ??bb01_main, U, U, 00H, 064H, 01H, 00H
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88 88 $DGS AUX_BEG, 06H, 00H, 04BH
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89 89 $DGS END_BLK, ??eb01_main, U, U, 00H, 064H, 01H, 00H
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90 90 $DGS AUX_END, 08H
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91 91 $DGS BEG_BLK, ??bb02_main, U, U, 00H, 064H, 01H, 00H
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92 92 $DGS AUX_BEG, 0AH, 00H, 04FH
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93 93 $DGS END_BLK, ??eb02_main, U, U, 00H, 064H, 01H, 00H
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94 94 $DGS AUX_END, 015H
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95 95 $DGS BEG_BLK, ??bb03_main, U, U, 00H, 064H, 01H, 00H
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96 96 $DGS AUX_BEG, 017H, 00H, 055H
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97 97 $DGS REG_VAR, _pwup_delay0, 06H, 0FFFFH, 010CH, 04H, 01H, 00H
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98 98 $DGS AUX_STR, 00H, 018H, 01H, 00H, 00H, 00H, 00H, 00H
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99 99 $DGS REG_VAR, _pwup_delay1, 07H, 0FFFFH, 010CH, 04H, 01H, 00H
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100 100 $DGS AUX_STR, 00H, 019H, 01H, 00H, 00H, 00H, 00H, 00H
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101 101 $DGS BEG_BLK, ??bb04_main, U, U, 00H, 064H, 01H, 00H
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102 102 $DGS AUX_BEG, 01CH, 00H, 057H
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103 103 $DGS BEG_BLK, ??bb05_main, U, U, 00H, 064H, 01H, 00H
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104 104 $DGS AUX_BEG, 01FH, 00H, 05FH
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105 105 $DGS END_BLK, ??eb05_main, U, U, 00H, 064H, 01H, 00H
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106 106 $DGS AUX_END, 021H
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107 107 $DGS END_BLK, ??eb04_main, U, U, 00H, 064H, 01H, 00H
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108 108 $DGS AUX_END, 023H
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109 109 $DGS END_BLK, ??eb03_main, U, U, 00H, 064H, 01H, 00H
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110 110 $DGS AUX_END, 027H
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111 111 $DGS BEG_BLK, ??bb06_main, U, U, 00H, 064H, 01H, 00H
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112 112 $DGS AUX_BEG, 02AH, 00H, 065H
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113 113 $DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 01H, 00H
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114 114 $DGS AUX_STR, 00H, 02BH, 01H, 00H, 00H, 00H, 00H, 00H
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115 115 $DGS REG_VAR, _comp, 07H, 0FFFFH, 010CH, 04H, 01H, 00H
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116 116 $DGS AUX_STR, 00H, 02CH, 01H, 00H, 00H, 00H, 00H, 00H
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117 117 $DGS BEG_BLK, ??bb07_main, U, U, 00H, 064H, 01H, 00H
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118 118 $DGS AUX_BEG, 031H, 00H, 069H
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119 119 $DGS END_BLK, ??eb07_main, U, U, 00H, 064H, 01H, 00H
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120 120 $DGS AUX_END, 033H
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121 121 $DGS BEG_BLK, ??bb08_main, U, U, 00H, 064H, 01H, 00H
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122 122 $DGS AUX_BEG, 036H, 00H, 00H
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123 123 $DGS END_BLK, ??eb08_main, U, U, 00H, 064H, 01H, 00H
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124 124 $DGS AUX_END, 03AH
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125 125 $DGS END_BLK, ??eb06_main, U, U, 00H, 064H, 01H, 00H
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126 126 $DGS AUX_END, 03BH
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127 127 $DGS END_BLK, ??eb00_main, U, U, 00H, 064H, 01H, 00H
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128 128 $DGS AUX_END, 03FH
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129 129 $DGS END_FUN, ??ef_main, U, U, 00H, 065H, 01H, 00H
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130 130 $DGS AUX_END, 040H
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131 131 $DGS GLV_SYM, _int_kr, U, U, 0E001H, 026H, 01H, 02H
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132 132 $DGS AUX_FUN, 00H, U, U, 079H, 00H, 00H
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133 133 $DGS BEG_FUN, ??bf_int_kr, U, U, 00H, 065H, 01H, 00H
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134 134 $DGS AUX_BEG, 08CH, 00H, 079H
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135 135 $DGS END_FUN, ??ef_int_kr, U, U, 00H, 065H, 01H, 00H
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136 136 $DGS AUX_END, 02H
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137 137 $DGS GLV_SYM, _intp4, U, U, 0E001H, 026H, 01H, 02H
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138 138 $DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H
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139 139 $DGS BEG_FUN, ??bf_intp4, U, U, 00H, 065H, 01H, 00H
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140 140 $DGS AUX_BEG, 095H, 00H, 07FH
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141 141 $DGS END_FUN, ??ef_intp4, U, U, 00H, 065H, 01H, 00H
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142 142 $DGS AUX_END, 02H
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143 143 $DGS GLV_SYM, _intp5, U, U, 0E001H, 026H, 01H, 02H
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144 144 $DGS AUX_FUN, 00H, U, U, 085H, 00H, 00H
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145 145 $DGS BEG_FUN, ??bf_intp5, U, U, 00H, 065H, 01H, 00H
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146 146 $DGS AUX_BEG, 09DH, 00H, 085H
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147 147 $DGS END_FUN, ??ef_intp5, U, U, 00H, 065H, 01H, 00H
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148 148 $DGS AUX_END, 02H
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149 149 $DGS GLV_SYM, _hdwinit, U, U, 01H, 026H, 01H, 02H
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150 150 $DGS AUX_FUN, 00H, U, U, 08BH, 00H, 00H
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151 151 $DGS BEG_FUN, ??bf_hdwinit, U, U, 00H, 065H, 01H, 00H
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152 152 $DGS AUX_BEG, 0A4H, 00H, 08BH
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153 153 $DGS END_FUN, ??ef_hdwinit, U, U, 00H, 065H, 01H, 00H
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154 154 $DGS AUX_END, 015H
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155 155 $DGS STA_SYM, _hdwinit2, U, U, 01H, 03H, 01H, 02H
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156 156 $DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H
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157 157 $DGS BEG_FUN, ??bf_hdwinit2, U, U, 00H, 065H, 01H, 00H
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158 158 $DGS AUX_BEG, 0BCH, 00H, 08FH
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159 159 $DGS BEG_BLK, ??bb00_hdwinit2, U, U, 00H, 064H, 01H, 00H
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160 160 $DGS AUX_BEG, 04H, 00H, 093H
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161 161 $DGS END_BLK, ??eb00_hdwinit2, U, U, 00H, 064H, 01H, 00H
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162 162 $DGS AUX_END, 019H
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163 163 $DGS BEG_BLK, ??bb01_hdwinit2, U, U, 00H, 064H, 01H, 00H
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164 164 $DGS AUX_BEG, 01BH, 00H, 00H
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165 165 $DGS END_BLK, ??eb01_hdwinit2, U, U, 00H, 064H, 01H, 00H
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166 166 $DGS AUX_END, 01FH
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167 167 $DGS END_FUN, ??ef_hdwinit2, U, U, 00H, 065H, 01H, 00H
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168 168 $DGS AUX_END, 0D1H
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169 169 $DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
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170 170 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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171 171 $DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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172 172 $DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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173 173 $DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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174 174 $DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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175 175 $DGS GLV_SYM, _firm_restore, U, U, 0CH, 02H, 01H, 02H
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176 176 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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177 177 $DGS GLV_SYM, _main_loop, U, U, 01H, 02H, 01H, 02H
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178 178 $DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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179 179
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180 180 EXTRN _WDT_Restart
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181 181 EXTRN _system_status
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182 182 EXTRN _vreg_ctr
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183 183 EXTRN _firm_restore
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184 184 EXTRN _main_loop
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185 185 PUBLIC _main
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186 186 PUBLIC _int_kr
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187 187 PUBLIC _intp4
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188 188 PUBLIC _intp5
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189 189 PUBLIC _hdwinit
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190 190
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191 191 ----- @@BITS BSEG
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192 192
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193 193 ----- @@CNST CSEG MIRRORP
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194 194
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195 195 ----- @@R_INIT CSEG UNIT64KP
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196 196
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197 197 ----- @@INIT DSEG BASEP
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198 198
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199 199 ----- @@DATA DSEG BASEP
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200 200
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201 201 ----- @@R_INIS CSEG UNIT64KP
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202 202
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203 203 ----- @@INIS DSEG SADDRP
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204 204
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205 205 ----- @@DATS DSEG SADDRP
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206 206
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207 207 ----- LDR_CNSL CSEG PAGE64KP
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208 208
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209 209 ----- @@RLINIT CSEG UNIT64KP
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210 210
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211 211 ----- @@INITL DSEG UNIT64KP
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212 212
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213 213 ----- @@DATAL DSEG UNIT64KP
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214 214
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215 215 ----- @@CALT CSEG CALLT0
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216 216
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217 217 ; line 1 : /* ========================================================
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218 218 ; line 2 : MCU CTR BSR
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219 219 ; line 3 : 2009/03/30
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220 220 ; line 4 : <20>J<EFBFBD><4A><EFBFBD>Z<EFBFBD>p<EFBFBD><70> <20><><EFBFBD>c
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221 221 ; line 5 :
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222 222 ; line 6 : <20>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>[<5B>_<EFBFBD>[<5B><>
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223 223 ; line 7 : <20>z<EFBFBD>X<EFBFBD>g<EFBFBD>̒ʐM<CA90>ƁA<C681><41><EFBFBD>ȏ<EFBFBD><C88F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>̃`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD><73><EFBFBD>B
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224 224 ; line 8 :
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225 225 ; line 9 : ======================================================== */
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226 226 ; line 10 : #pragma SFR
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227 227 ; line 11 : #pragma di
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228 228 ; line 12 : #pragma ei
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229 229 ; line 13 : #pragma nop
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230 230 ; line 14 : #pragma stop
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231 231 ; line 15 : #pragma halt
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232 232 ; line 16 : #pragma opc
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233 233 ; line 17 :
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234 234 ; line 18 :
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235 235 ; line 19 : #include "incs_loader.h"
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236 236 ; line 20 :
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237 237 ; line 21 : #include "fsl.h"
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238 238 ; line 22 : #include "fsl_user.h"
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239 239 ; line 23 :
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240 240 ; line 24 : #include "i2c_ctr.h"
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241 241 ; line 25 : #include "i2c_mcu.h"
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242 242 ; line 26 : #include "pm.h"
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243 243 ; line 27 : #include "rtc.h"
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244 244 ; line 28 :
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245 245 ; line 29 : #include "reboot.h"
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246 246 ; line 30 :
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247 247 ; line 31 :
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248 248 ; line 32 : // ========================================================
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249 249 ; line 33 : #if (FSL_DATA_BUFFER_SIZE>0)
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250 250 ; line 34 : fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE];
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251 251 ; line 35 : #endif
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252 252 ; line 36 :
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253 253 ; line 37 :
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254 254 ; line 38 :
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255 255 ; line 39 : #ifdef FSL_INT_BACKUP
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256 256 ; line 40 : static fsl_u08 fsl_MK0L_bak_u08; /* if (interrupt back
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257 257 ; up required) */
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258 258 ; line 41 : static fsl_u08 fsl_MK0H_bak_u08; /* {
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259 259 ; */
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260 260 ; line 42 : static fsl_u08 fsl_MK1L_bak_u08; /* reserve space fo
|
||
261 261 ; r backup information */
|
||
262 262 ; line 43 : static fsl_u08 fsl_MK1H_bak_u08; /* of interrupt mas
|
||
263 263 ; k flags */
|
||
264 264 ; line 44 : static fsl_u08 fsl_MK2L_bak_u08; /*
|
||
265 265 ; */
|
||
266 266 ; line 45 : static fsl_u08 fsl_MK2H_bak_u08; /* }
|
||
267 267 ; */
|
||
268 268 ; line 46 : #endif
|
||
269 269 ; line 47 :
|
||
270 270 ; line 48 :
|
||
271 271 ; line 49 :
|
||
272 272 ; line 50 : // magic.c <20>̋L<CC8B>q<EFBFBD>ƈ<EFBFBD><C688><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>悤<EFBFBD>ɒ<EFBFBD><C992>ӁI
|
||
273 273 ; line 51 : #define MGC_LOAD 0x0FF6
|
||
274 274 ; line 52 : #define MGC_FOOT 0x4FF6
|
||
275 275 ; line 53 :
|
||
276 276 ; line 54 :
|
||
277 277 ; line 55 :
|
||
278 278 ; line 56 : // ========================================================
|
||
279 279 ; line 57 : void FSL_Open( void );
|
||
280 280 ; line 58 : void FSL_Close( void );
|
||
281 281 ; line 59 : void hdwinit( void );
|
||
282 282 ; line 60 : void power_save( );
|
||
283 283 ; line 61 : static void hdwinit2( );
|
||
284 284 ; line 62 :
|
||
285 285 ; line 63 : extern void main_loop( );
|
||
286 286 ; line 64 :
|
||
287 287 ; line 65 :
|
||
288 288 ; line 66 :
|
||
289 289 ; line 67 : // ========================================================
|
||
290 290 ; line 68 : void main( )
|
||
291 291 ; line 69 : {
|
||
292 292
|
||
293 293 ----- LDR_CODE CSEG BASE
|
||
294 294 00000 _main:
|
||
295 295 $DGL 1,65
|
||
296 296 00000 C7 push hl ;[INF] 1, 1
|
||
297 297 00001 ??bf_main:
|
||
298 298 ; line 70 : while( 1 )
|
||
299 299 00001 ?L0003:
|
||
300 300 ; line 71 : {
|
||
301 301 00001 ??bb00_main:
|
||
302 302 ; line 72 : WDT_Restart( );
|
||
303 303 $DGL 0,4
|
||
304 304 00001 RFD0000 call !_WDT_Restart ;[INF] 3, 3
|
||
305 305 ; line 73 : if( RTCEN )
|
||
306 306 $DGL 0,5
|
||
307 307 00004 C7 push hl ;[INF] 1, 1
|
||
308 308 00005 36F000 movw hl,#0F0H ; 240 ;[INF] 3, 1
|
||
309 309 00008 71F4 mov1 CY,[hl].7 ;[INF] 2, 1
|
||
310 310 0000A C6 pop hl ;[INF] 1, 1
|
||
311 311 0000B DE06 bnc $?L0005 ;[INF] 2, 4
|
||
312 312 ; line 74 : {
|
||
313 313 0000D ??bb01_main:
|
||
314 314 ; line 75 : system_status.reboot = 1;
|
||
315 315 $DGL 0,7
|
||
316 316 0000D R71300200 set1 !_system_status+2.3 ;[INF] 4, 2
|
||
317 317 00011 ??eb01_main:
|
||
318 318 ; line 76 : }
|
||
319 319 $DGL 0,8
|
||
320 320 00011 EF25 br $?L0008 ;[INF] 2, 3
|
||
321 321 00013 ?L0005:
|
||
322 322 ; line 77 : else if( ( RESF & 0x10 ) != 0) // WDRF,WDT<44>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g
|
||
323 323 $DGL 0,9
|
||
324 324 00013 5110 mov a,#010H ; 16 ;[INF] 2, 1
|
||
325 325 00015 5FA8FF and a,!RESF ;[INF] 3, 1
|
||
326 326 00018 D1 cmp0 a ;[INF] 1, 1
|
||
327 327 00019 DD0D bz $?L0007 ;[INF] 2, 4
|
||
328 328 ; line 78 : {
|
||
329 329 0001B ??bb02_main:
|
||
330 330 ; line 79 : system_status.reboot = 1;
|
||
331 331 $DGL 0,11
|
||
332 332 0001B R71300200 set1 !_system_status+2.3 ;[INF] 4, 2
|
||
333 333 ; line 80 : #ifdef _PMIC_TWL_
|
||
334 334 ; line 81 : // <20>\<5C><><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD><DC82>̂ōċN<C48B><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
335 335 ; line 82 : PM_reset_ast();
|
||
336 336 ; line 83 : /// hdwinit2<74>Ȃ<EFBFBD><C882>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>ɑ<EFBFBD><C991>s<EFBFBD><73><EFBFBD><EFBFBD>
|
||
337 337 ; <20>悢<EFBFBD>i<EFBFBD><69><EFBFBD>ɂ<EFBFBD><C982>ɂ<EFBFBD><C982>I<EFBFBD>j
|
||
338 338 ; line 84 : #endif
|
||
339 339 ; line 85 : vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_
|
||
340 340 ; RESET;
|
||
341 341 $DGL 0,17
|
||
342 342 0001F R71100200 set1 !_vreg_ctr+2.1 ;[INF] 4, 2
|
||
343 343 ; line 86 : // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
|
||
344 344 ; line 87 : // <20><>I2C<32>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɍs<C98D><73>
|
||
345 345 ; line 88 : hdwinit2( );
|
||
346 346 $DGL 0,20
|
||
347 347 00023 RFD8700 call !_hdwinit2 ;[INF] 3, 3
|
||
348 348 00026 ??eb02_main:
|
||
349 349 ; line 89 : }
|
||
350 350 $DGL 0,21
|
||
351 351 00026 EF10 br $?L0008 ;[INF] 2, 3
|
||
352 352 00028 ?L0007:
|
||
353 353 ; line 90 : else
|
||
354 354 ; line 91 : {
|
||
355 355 00028 ??bb03_main:
|
||
356 356 ; line 92 : u8 pwup_delay0 = 0;
|
||
357 357 $DGL 0,24
|
||
358 358 00028 360000 movw hl,#00H ; 0 ;[INF] 3, 1
|
||
359 359 ; line 93 : u8 pwup_delay1 = 0;
|
||
360 360 ; line 94 :
|
||
361 361 ; line 95 : do
|
||
362 362 0002B ?L0009:
|
||
363 363 ; line 96 : { // <20>d<EFBFBD>r<EFBFBD>ڑ<EFBFBD><DA91><EFBFBD><EFBFBD>A16ms<6D>҂<EFBFBD><D282>Ă݂<C482>(<28>`
|
||
364 364 ; <20><><EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><EFBFBD>)
|
||
365 365 0002B ??bb04_main:
|
||
366 366 ; line 97 : pwup_delay0 += 1;
|
||
367 367 $DGL 0,29
|
||
368 368 0002B 86 inc l ;[INF] 1, 1
|
||
369 369 ; line 98 : do
|
||
370 370 0002C ?L0012:
|
||
371 371 ; line 99 : {
|
||
372 372 0002C ??bb05_main:
|
||
373 373 ; line 100 : pwup_delay1 += 1;
|
||
374 374 $DGL 0,32
|
||
375 375 0002C 87 inc h ;[INF] 1, 1
|
||
376 376 0002D ??eb05_main:
|
||
377 377 ; line 101 : }
|
||
378 378 ; line 102 : while( pwup_delay1 != 0 ); // u16<31>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ƃR
|
||
379 379 ; <20><><EFBFBD>p<EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>{<7B><><EFBFBD><EFBFBD><F182BE82>c<EFBFBD>B
|
||
380 380 $DGL 0,34
|
||
381 381 0002D 67 mov a,h ;[INF] 1, 1
|
||
382 382 0002E D1 cmp0 a ;[INF] 1, 1
|
||
383 383 0002F DFFB bnz $?L0012 ;[INF] 2, 4
|
||
384 384 00031 ??eb04_main:
|
||
385 385 ; line 103 : }
|
||
386 386 ; line 104 : while( pwup_delay0 != 0 );
|
||
387 387 $DGL 0,36
|
||
388 388 00031 66 mov a,l ;[INF] 1, 1
|
||
389 389 00032 D1 cmp0 a ;[INF] 1, 1
|
||
390 390 00033 DFF6 bnz $?L0009 ;[INF] 2, 4
|
||
391 391 ; line 105 :
|
||
392 392 ; line 106 : hdwinit2( );
|
||
393 393 $DGL 0,38
|
||
394 394 00035 RFD8700 call !_hdwinit2 ;[INF] 3, 3
|
||
395 395 00038 ??eb03_main:
|
||
396 396 ; line 107 : }
|
||
397 397 00038 ?L0008:
|
||
398 398 ; line 108 :
|
||
399 399 ; line 109 : // <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD><EFBFBD><EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N //
|
||
400 400 ; line 110 : {
|
||
401 401 00038 ??bb06_main:
|
||
402 402 ; line 111 : u8 i;
|
||
403 403 ; line 112 : u8 comp = 0;
|
||
404 404 $DGL 0,44
|
||
405 405 00038 360000 movw hl,#00H ; 0 ;[INF] 3, 1
|
||
406 406 ; line 113 :
|
||
407 407 ; line 114 : // <20><><EFBFBD>[<5B>_<EFBFBD>[<5B>Ɩ{<7B>͓̂<CC82><CD93><EFBFBD><EFBFBD>o<EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>H
|
||
408 408 ; line 115 : /// <20><><EFBFBD>ւ̃A<CC83>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD>̓r<CC93><72><EFBFBD>ŏI<C58F><49><EFBFBD><EFBFBD><EFBFBD>ĂȂ<C482><C882><EFBFBD><EFBFBD>H
|
||
409 409 ; line 116 : for( i = 0; i < sizeof( __TIME__ ); i++ ) // si
|
||
410 410 ; zeof( __TIME__ ) = 8 <20>炵
|
||
411 411 $DGL 0,48
|
||
412 412 0003B ?L0015:
|
||
413 413 0003B 66 mov a,l ;[INF] 1, 1
|
||
414 414 0003C 4C09 cmp a,#09H ; 9 ;[INF] 2, 1
|
||
415 415 0003E DE23 bnc $?L0016 ;[INF] 2, 4
|
||
416 416 ; line 117 : {
|
||
417 417 00040 ??bb07_main:
|
||
418 418 ; line 118 : comp += ( *( __far u8 * )( MGC_LOAD + i ) == *(
|
||
419 419 ; u8 * )( MGC_FOOT + i ) ) ? 0 : 1;
|
||
420 420 $DGL 0,50
|
||
421 421 00040 17 movw ax,hl ;[INF] 1, 1
|
||
422 422 00041 F1 clrb a ;[INF] 1, 1
|
||
423 423 00042 04F60F addw ax,#0FF6H ; 4086 ;[INF] 3, 1
|
||
424 424 00045 C1 push ax ;[INF] 1, 1
|
||
425 425 00046 317B sar a,7 ;[INF] 2, 1
|
||
426 426 00048 9EFD mov ES,a ;[INF] 2, 1
|
||
427 427 0004A C4 pop de ;[INF] 1, 1
|
||
428 428 0004B 1189 mov a,ES:[de] ;[INF] 2, 2
|
||
429 429 0004D 72 mov c,a ;[INF] 1, 1
|
||
430 430 0004E 17 movw ax,hl ;[INF] 1, 1
|
||
431 431 0004F F1 clrb a ;[INF] 1, 1
|
||
432 432 00050 04F64F addw ax,#04FF6H ; 20470 ;[INF] 3, 1
|
||
433 433 00053 14 movw de,ax ;[INF] 1, 1
|
||
434 434 00054 89 mov a,[de] ;[INF] 1, 1
|
||
435 435 00055 6142 cmp c,a ;[INF] 2, 1
|
||
436 436 00057 DF03 bnz $?L0018 ;[INF] 2, 4
|
||
437 437 00059 F6 clrw ax ;[INF] 1, 1
|
||
438 438 0005A EF01 br $?L0019 ;[INF] 2, 3
|
||
439 439 0005C ?L0018:
|
||
440 440 0005C E6 onew ax ;[INF] 1, 1
|
||
441 441 0005D ?L0019:
|
||
442 442 0005D 60 mov a,x ;[INF] 1, 1
|
||
443 443 0005E 6107 add h,a ;[INF] 2, 1
|
||
444 444 00060 ??eb07_main:
|
||
445 445 ; line 119 : }
|
||
446 446 $DGL 0,51
|
||
447 447 00060 86 inc l ;[INF] 1, 1
|
||
448 448 00061 EFD8 br $?L0015 ;[INF] 2, 3
|
||
449 449 00063 ?L0016:
|
||
450 450 ; line 120 :
|
||
451 451 ; line 121 : if( comp != 0 )
|
||
452 452 $DGL 0,53
|
||
453 453 00063 67 mov a,h ;[INF] 1, 1
|
||
454 454 00064 D1 cmp0 a ;[INF] 1, 1
|
||
455 455 00065 61E8 skz ;[INF] 2, 1
|
||
456 456 ; line 122 : {
|
||
457 457 00067 ??bb08_main:
|
||
458 458 ; line 123 : // <20>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>݂<EFBFBD>
|
||
459 459 ; line 124 : firm_restore( );
|
||
460 460 $DGL 0,56
|
||
461 461 00067 RFD0000 call !_firm_restore ;[INF] 3, 3
|
||
462 462 0006A ??eb08_main:
|
||
463 463 ; line 125 : // <20>A<EFBFBD><41><EFBFBD>Ă<EFBFBD><C482>Ȃ<EFBFBD><C882>B<EFBFBD><42><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B
|
||
464 464 ; line 126 : }
|
||
465 465 0006A ?L0020:
|
||
466 466 0006A ??eb06_main:
|
||
467 467 ; line 127 : }
|
||
468 468 ; line 128 :
|
||
469 469 ; line 129 : // <20>ʏ<EFBFBD><CA8F>^<5E>]
|
||
470 470 ; line 130 : main_loop( );
|
||
471 471 $DGL 0,62
|
||
472 472 0006A RFD0000 call !_main_loop ;[INF] 3, 3
|
||
473 473 0006D ??eb00_main:
|
||
474 474 ; line 131 : }
|
||
475 475 $DGL 0,63
|
||
476 476 0006D EF92 br $?L0003 ;[INF] 2, 3
|
||
477 477 ; line 132 : }
|
||
478 478 $DGL 0,64
|
||
479 479 0006F ??ef_main:
|
||
480 480 0006F C6 pop hl ;[INF] 1, 1
|
||
481 481 00070 D7 ret ;[INF] 1, 6
|
||
482 482 00071 ??ee_main:
|
||
483 483 ; line 133 :
|
||
484 484 ; line 134 :
|
||
485 485 ; line 135 :
|
||
486 486 ; line 136 : /* ========================================================
|
||
487 487 ; line 137 : <20>L<EFBFBD>[<5B><><EFBFBD>^<5E>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
488 488 ; line 138 : ======================================================== */
|
||
489 489 ; line 139 : __interrupt void int_kr( )
|
||
490 490 ; line 140 : {
|
||
491 491
|
||
492 492 ----- @@BASE CSEG BASE
|
||
493 493 00000 _int_kr:
|
||
494 494 $DGL 1,115
|
||
495 495 00000 ??bf_int_kr:
|
||
496 496 ; line 141 : }
|
||
497 497 $DGL 0,2
|
||
498 498 00000 ??ef_int_kr:
|
||
499 499 00000 61FC reti ;[INF] 2, 6
|
||
500 500 00002 ??ee_int_kr:
|
||
501 501 ; line 142 :
|
||
502 502 ; line 143 :
|
||
503 503 ; line 144 :
|
||
504 504 ; line 145 : /* ========================================================
|
||
505 505 ; line 146 : ext dc
|
||
506 506 ; line 147 : ======================================================== */
|
||
507 507 ; line 148 : __interrupt void intp4( )
|
||
508 508 ; line 149 : {
|
||
509 509 00002 _intp4:
|
||
510 510 $DGL 1,121
|
||
511 511 00002 ??bf_intp4:
|
||
512 512 ; line 150 : }
|
||
513 513 $DGL 0,2
|
||
514 514 00002 ??ef_intp4:
|
||
515 515 00002 61FC reti ;[INF] 2, 6
|
||
516 516 00004 ??ee_intp4:
|
||
517 517 ; line 151 :
|
||
518 518 ; line 152 :
|
||
519 519 ; line 153 : /* ========================================================
|
||
520 520 ; line 154 : shell close
|
||
521 521 ; line 155 : ======================================================== */
|
||
522 522 ; line 156 : __interrupt void intp5( )
|
||
523 523 ; line 157 : {
|
||
524 524 00004 _intp5:
|
||
525 525 $DGL 1,127
|
||
526 526 00004 ??bf_intp5:
|
||
527 527 ; line 158 : }
|
||
528 528 $DGL 0,2
|
||
529 529 00004 ??ef_intp5:
|
||
530 530 00004 61FC reti ;[INF] 2, 6
|
||
531 531 00006 ??ee_intp5:
|
||
532 532 ; line 159 :
|
||
533 533 ; line 160 :
|
||
534 534 ; line 161 :
|
||
535 535 ; line 162 : // ========================================================
|
||
536 536 ; line 163 : void hdwinit( void )
|
||
537 537 ; line 164 : { // <20>X<EFBFBD>^<5E>[<5B>g<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>[<5B>`<60><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
538 538 ; <20>Ăт܂<D182>
|
||
539 539
|
||
540 540 ----- LDR_CODE CSEG BASE
|
||
541 541 00071 _hdwinit:
|
||
542 542 $DGL 1,133
|
||
543 543 00071 717BFA di ;[INF] 3, 4
|
||
544 544 00074 ??bf_hdwinit:
|
||
545 545 ; line 165 : DI( ); /* <20>}<7D>X<EFBFBD>^<5E><><EFBFBD>荞<EFBFBD>֎~ */
|
||
546 546 ; line 166 :
|
||
547 547 ; line 167 : CMC = 0b00010110; /* X1<58><31><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD>(<28><><EFBFBD>̓|<7C>[<5B>g)<29>AXT1<54>g<EFBFBD>p
|
||
548 548 ; <20>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD>Œ<EFBFBD><C592><EFBFBD><EFBFBD>d<EFBFBD>͔<EFBFBD><CD94>U */
|
||
549 549 $DGL 0,4
|
||
550 550 00074 CEA016 mov CMC,#016H ; 22 ;[INF] 3, 1
|
||
551 551 ; line 168 : CSC = 0b10000000; /* X1<58><31><EFBFBD>U<EFBFBD>Ȃ<EFBFBD><C882>AXT1<54><31><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
552 552 ; <20><><EFBFBD><EFBFBD><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD> */
|
||
553 553 $DGL 0,5
|
||
554 554 00077 CEA180 mov CSC,#080H ; 128 ;[INF] 3, 1
|
||
555 555 ; line 169 : #ifdef _MCU_BSR_
|
||
556 556 ; line 170 : OSMC = 0x01; /* <20>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>W<EFBFBD>X<EFBFBD>^ */
|
||
557 557 $DGL 0,7
|
||
558 558 0007A E5F300 oneb !OSMC ;[INF] 3, 1
|
||
559 559 ; line 171 : #endif
|
||
560 560 ; line 172 : #ifdef _OVERCLOCK_
|
||
561 561 ; line 173 : CKC = 0b00001000; /* CPU/<2F><><EFBFBD>ӃN<D383><4E><EFBFBD>b<EFBFBD>N=fMAIN<49>AfMAIN=
|
||
562 562 ; fMX<4D>AfCLK=fMX */
|
||
563 563 $DGL 0,10
|
||
564 564 0007D CEA408 mov CKC,#08H ; 8 ;[INF] 3, 1
|
||
565 565 ; line 174 : #else
|
||
566 566 ; line 175 : // CKC <20>f<EFBFBD>t<EFBFBD>H<EFBFBD><48><EFBFBD>g<EFBFBD>ł悢
|
||
567 567 ; line 176 : #endif
|
||
568 568 ; line 177 :
|
||
569 569 ; line 178 : /*--- <20><><EFBFBD>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>H<EFBFBD>̐ݒ<CC90> ---*/
|
||
570 570 ; line 179 : /* <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̃f<CC83>t<EFBFBD>H<EFBFBD><48><EFBFBD>g<EFBFBD>́A<CD81>I<EFBFBD>v<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>E<EFBFBD>o<EFBFBD>C<EFBFBD>g<EFBFBD>ɂĎw<C48E>肳
|
||
571 571 ; <20><><EFBFBD><EFBFBD> */
|
||
572 572 ; line 180 : LVIS = 0b00000000; /* VLVI = 4.22<EFBFBD>}0.1V */
|
||
573 573 $DGL 0,17
|
||
574 574 00080 F5AAFF clrb !LVIS ;[INF] 3, 1
|
||
575 575 ; line 181 : LVIM = 0b00000000; /* LVI<56><49><EFBFBD><EFBFBD><EFBFBD>֎~ */
|
||
576 576 $DGL 0,18
|
||
577 577 00083 F5A9FF clrb !LVIM ;[INF] 3, 1
|
||
578 578 ; line 182 : /* <20>d<EFBFBD><64><EFBFBD>d<EFBFBD><64>(VDD)<29><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>d<EFBFBD><64>(VLVI)<29><><EFBFBD>Ɋ<EFBFBD><C98A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||
579 579 ; line 183 : /* <20>d<EFBFBD><64><EFBFBD>d<EFBFBD><64>(VDD)<29><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>d<EFBFBD><64><VLVI)<29>A<EFBFBD>܂<EFBFBD><DC82>͓<EFBFBD><CD93><EFBFBD><EFBFBD>֎~<7E><><EFBFBD>ɒ<EFBFBD><C992>d<EFBFBD><64><EFBFBD><EFBFBD>
|
||
580 580 ; <20>o */
|
||
581 581 ; line 184 : }
|
||
582 582 $DGL 0,21
|
||
583 583 00086 ??ef_hdwinit:
|
||
584 584 00086 D7 ret ;[INF] 1, 6
|
||
585 585 00087 ??ee_hdwinit:
|
||
586 586 ; line 185 :
|
||
587 587 ; line 186 :
|
||
588 588 ; line 187 : void hdwinit2( )
|
||
589 589 ; line 188 : {
|
||
590 590 00087 _hdwinit2:
|
||
591 591 $DGL 1,139
|
||
592 592 00087 ??bf_hdwinit2:
|
||
593 593 ; line 189 : // <20>|<7C>[<5B>g<EFBFBD>ݒ<EFBFBD> /////////////////////////////////////////
|
||
594 594 ; line 190 : if( system_status.reboot ) // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͂<EFBFBD><CD82><EFBFBD><EFBFBD>ɃZ<C983>b<EFBFBD>g
|
||
595 595 ; <20><><EFBFBD><EFBFBD>
|
||
596 596 $DGL 0,3
|
||
597 597 00087 R8F0200 mov a,!_system_status+2 ;[INF] 3, 1
|
||
598 598 0008A 313509 bf a.3,$?L0032 ;[INF] 3, 5
|
||
599 599 ; line 191 : {
|
||
600 600 0008D ??bb00_hdwinit2:
|
||
601 601 ; line 192 : #ifdef _MODEL_TEG2_
|
||
602 602 ; line 193 : P0 = 0b00000011;
|
||
603 603 ; line 194 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
604 604 ; <20><>
|
||
605 605 ; line 195 : P14 = 0b00000001;
|
||
606 606 ; line 196 : #endif
|
||
607 607 ; line 197 : #ifdef _MODEL_WM0_
|
||
608 608 ; line 198 : P0 = 0b00000011;
|
||
609 609 ; line 199 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
610 610 ; <20><>
|
||
611 611 ; line 200 : P14 = 0b00000001;
|
||
612 612 ; line 201 : #endif
|
||
613 613 ; line 202 : #ifdef _MODEL_TS0_
|
||
614 614 ; line 203 : P0 = 0b00000001;
|
||
615 615 ; line 204 : P3 = 0b00000111; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
616 616 ; <20><>
|
||
617 617 ; line 205 : P14 = 0b00000000;
|
||
618 618 ; line 206 : #endif
|
||
619 619 ; line 207 : #ifdef _MODEL_CTR_
|
||
620 620 ; line 208 : P0 = 0b00000001;
|
||
621 621 $DGL 0,21
|
||
622 622 0008D E400 oneb P0 ;[INF] 2, 1
|
||
623 623 ; line 209 : P3 = 0b00000111; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
624 624 ; <20><>
|
||
625 625 $DGL 0,22
|
||
626 626 0008F CD0307 mov P3,#07H ; 7 ;[INF] 3, 1
|
||
627 627 ; line 210 : P14 = 0b00000000;
|
||
628 628 $DGL 0,23
|
||
629 629 00092 F40E clrb P14 ;[INF] 2, 1
|
||
630 630 00094 ??eb00_hdwinit2:
|
||
631 631 ; line 211 : #endif
|
||
632 632 ; line 212 : }
|
||
633 633 $DGL 0,25
|
||
634 634 00094 EF07 br $?L0033 ;[INF] 2, 3
|
||
635 635 00096 ?L0032:
|
||
636 636 ; line 213 : else
|
||
637 637 ; line 214 : {
|
||
638 638 00096 ??bb01_hdwinit2:
|
||
639 639 ; line 215 : P0 = 0b00000000;
|
||
640 640 $DGL 0,28
|
||
641 641 00096 F400 clrb P0 ;[INF] 2, 1
|
||
642 642 ; line 216 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
643 643 ; <20><>
|
||
644 644 $DGL 0,29
|
||
645 645 00098 CD0306 mov P3,#06H ; 6 ;[INF] 3, 1
|
||
646 646 ; line 217 : P14 = 0b00000000;
|
||
647 647 $DGL 0,30
|
||
648 648 0009B F40E clrb P14 ;[INF] 2, 1
|
||
649 649 0009D ??eb01_hdwinit2:
|
||
650 650 ; line 218 : }
|
||
651 651 0009D ?L0033:
|
||
652 652 ; line 219 :
|
||
653 653 ; line 220 : #ifdef _MCU_BSR_
|
||
654 654 ; line 221 : PM0 = 0b11111111; // BSR<53>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD>ł́Areset1<74>͊Ď<CD8A><C48E><EFBFBD>
|
||
655 655 ; <20>݂ɂȂ<C982><C882>B
|
||
656 656 $DGL 0,34
|
||
657 657 0009D CE20FF mov PM0,#0FFH ; 255 ;[INF] 3, 1
|
||
658 658 ; line 222 : #else
|
||
659 659 ; line 223 : PM0 = 0b00000000; // 0<>ŏo<C58F><6F>
|
||
660 660 ; line 224 : #endif
|
||
661 661 ; line 225 : PM3 = 0b11110000; // P31,32<33>͊Ȉ<CD8A>I2C
|
||
662 662 $DGL 0,38
|
||
663 663 000A0 CE23F0 mov PM3,#0F0H ; 240 ;[INF] 3, 1
|
||
664 664 ; line 226 : PM14 = 0b11111100; // debugger[1] <20>Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F>
|
||
665 665 $DGL 0,39
|
||
666 666 000A3 CE2EFC mov PM14,#0FCH ; 252 ;[INF] 3, 1
|
||
667 667 ; line 227 :
|
||
668 668 ; line 228 : P1 = 0b00000000;
|
||
669 669 $DGL 0,41
|
||
670 670 000A6 F401 clrb P1 ;[INF] 2, 1
|
||
671 671 ; line 229 : P2 = 0b00000000;
|
||
672 672 $DGL 0,42
|
||
673 673 000A8 F402 clrb P2 ;[INF] 2, 1
|
||
674 674 ; line 230 : P4 = 0b00000000;
|
||
675 675 $DGL 0,43
|
||
676 676 000AA F404 clrb P4 ;[INF] 2, 1
|
||
677 677 ; line 231 : P5 = 0b00000000;
|
||
678 678 $DGL 0,44
|
||
679 679 000AC F405 clrb P5 ;[INF] 2, 1
|
||
680 680 ; line 232 : P6 = 0b00000000;
|
||
681 681 $DGL 0,45
|
||
682 682 000AE F406 clrb P6 ;[INF] 2, 1
|
||
683 683 ; line 233 : P7 = 0b01000000;
|
||
684 684 $DGL 0,46
|
||
685 685 000B0 CD0740 mov P7,#040H ; 64 ;[INF] 3, 1
|
||
686 686 ; line 234 : P12 = 0b00000000;
|
||
687 687 $DGL 0,47
|
||
688 688 000B3 F40C clrb P12 ;[INF] 2, 1
|
||
689 689 ; line 235 :
|
||
690 690 ; line 236 : #ifdef _MCU_BSR_
|
||
691 691 ; line 237 : P20 = 0b00000000;
|
||
692 692 $DGL 0,50
|
||
693 693 000B5 F51005 clrb !P20 ;[INF] 3, 1
|
||
694 694 ; line 238 : #else
|
||
695 695 ; line 239 : P8 = 0b00000000;
|
||
696 696 ; line 240 : #endif
|
||
697 697 ; line 241 :
|
||
698 698 ; line 242 : P15 = 0b00000000;
|
||
699 699 $DGL 0,55
|
||
700 700 000B8 F40F clrb P15 ;[INF] 2, 1
|
||
701 701 ; line 243 :
|
||
702 702 ; line 244 :
|
||
703 703 ; line 245 : PM1 = 0b00000000;
|
||
704 704 $DGL 0,58
|
||
705 705 000BA F521FF clrb !PM1 ;[INF] 3, 1
|
||
706 706 ; line 246 : PM2 = 0b11101001;
|
||
707 707 $DGL 0,59
|
||
708 708 000BD CE22E9 mov PM2,#0E9H ; 233 ;[INF] 3, 1
|
||
709 709 ; line 247 :
|
||
710 710 ; line 248 : #ifdef _PMIC_CTR_
|
||
711 711 ; line 249 : PM4 = 0b11110111;
|
||
712 712 $DGL 0,62
|
||
713 713 000C0 CE24F7 mov PM4,#0F7H ; 247 ;[INF] 3, 1
|
||
714 714 ; line 250 : #else
|
||
715 715 ; line 251 : PM4 = 0b11111011;
|
||
716 716 ; line 252 : #endif
|
||
717 717 ; line 253 :
|
||
718 718 ; line 254 : PM5 = 0b11110011;
|
||
719 719 $DGL 0,67
|
||
720 720 000C3 CE25F3 mov PM5,#0F3H ; 243 ;[INF] 3, 1
|
||
721 721 ; line 255 : PM6 = 0b11111100; // I2C<32>̃<EFBFBD><CC83>C<EFBFBD><43><EFBFBD><EFBFBD>L<EFBFBD>o<EFBFBD>͂ɂȂ<C982><C882>Ă<EFBFBD><C482><EFBFBD>
|
||
722 722 ; <20><><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD><EFBFBD>OFF<46>Ȃ̂ł<CC82><C582>܂<EFBFBD><DC82>Ȃ<EFBFBD>
|
||
723 723 $DGL 0,68
|
||
724 724 000C6 CE26FC mov PM6,#0FCH ; 252 ;[INF] 3, 1
|
||
725 725 ; line 256 : #ifdef _MODEL_CTR_
|
||
726 726 ; line 257 : PM7 = 0b01011111;
|
||
727 727 $DGL 0,70
|
||
728 728 000C9 CE275F mov PM7,#05FH ; 95 ;[INF] 3, 1
|
||
729 729 ; line 258 : #else
|
||
730 730 ; line 259 : PM7 = 0b00011111;
|
||
731 731 ; line 260 : #endif
|
||
732 732 ; line 261 : PM12 = 0b11111111; // 32kHz<48>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD>̃s<CC83><73><EFBFBD>ݒ<EFBFBD><DD92>͂ǂ<CD82><C782><EFBFBD>
|
||
733 733 ; <20>ł<EFBFBD><C582>悢
|
||
734 734 $DGL 0,74
|
||
735 735 000CC CE2CFF mov PM12,#0FFH ; 255 ;[INF] 3, 1
|
||
736 736 ; line 262 : PM15 = 0b11111111;
|
||
737 737 $DGL 0,75
|
||
738 738 000CF CE2FFF mov PM15,#0FFH ; 255 ;[INF] 3, 1
|
||
739 739 ; line 263 :
|
||
740 740 ; line 264 : #ifdef _MCU_BSR_
|
||
741 741 ; line 265 : #ifdef _MODEL_CTR_
|
||
742 742 ; line 266 : PM20 = 0b11111101;
|
||
743 743 $DGL 0,79
|
||
744 744 000D2 CF1105FD mov !PM20,#0FDH ; 253 ;[INF] 4, 1
|
||
745 745 ; line 267 : #else
|
||
746 746 ; line 268 : PM20 = 0b11111100;
|
||
747 747 ; line 269 : #endif
|
||
748 748 ; line 270 : #else
|
||
749 749 ; line 271 : PM8 = 0b11111111;
|
||
750 750 ; line 272 : #endif
|
||
751 751 ; line 273 :
|
||
752 752 ; line 274 : // <20>v<EFBFBD><76><EFBFBD>A<EFBFBD>b<EFBFBD>v /////////////////////////////////////////
|
||
753 753 ; line 275 : PU0 = 0b00000000; // <20>o<EFBFBD>b<EFBFBD>e<EFBFBD><65><EFBFBD>F<EFBFBD>،<EFBFBD><D88C>ɂ<EFBFBD><C982>ꂼ<EFBFBD><EA82BC><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
754 754 $DGL 0,88
|
||
755 755 000D6 F53000 clrb !PU0 ;[INF] 3, 1
|
||
756 756 ; line 276 : PU1 = 0b00000000;
|
||
757 757 $DGL 0,89
|
||
758 758 000D9 F53100 clrb !PU1 ;[INF] 3, 1
|
||
759 759 ; line 277 : PU3 = 0b00000000; // <20>O<EFBFBD><4F><EFBFBD>Ńv<C583><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>Ȃ<EFBFBD><C882>Ƌ<C68B><EF8D87>
|
||
760 760 ; <20><><EFBFBD><EFBFBD><EFBFBD>BCPU<50><55><EFBFBD>v<EFBFBD><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD>
|
||
761 761 $DGL 0,90
|
||
762 762 000DC F53300 clrb !PU3 ;[INF] 3, 1
|
||
763 763 ; line 278 : PU4 = 0b00000000; // <20>O<EFBFBD><4F><EFBFBD>Ńv<C583><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>Ăق<C482><D982><EFBFBD>tool
|
||
764 764 ; 0,1)
|
||
765 765 $DGL 0,91
|
||
766 766 000DF F53400 clrb !PU4 ;[INF] 3, 1
|
||
767 767 ; line 279 : PU5 = 0b00000011;
|
||
768 768 $DGL 0,92
|
||
769 769 000E2 CF350003 mov !PU5,#03H ; 3 ;[INF] 4, 1
|
||
770 770 ; line 280 : PU7 = 0b00011001;
|
||
771 771 $DGL 0,93
|
||
772 772 000E6 CF370019 mov !PU7,#019H ; 25 ;[INF] 4, 1
|
||
773 773 ; line 281 : PU12 = 0b00000000;
|
||
774 774 $DGL 0,94
|
||
775 775 000EA F53C00 clrb !PU12 ;[INF] 3, 1
|
||
776 776 ; line 282 : PU14 = 0b00000000;
|
||
777 777 $DGL 0,95
|
||
778 778 000ED F53E00 clrb !PU14 ;[INF] 3, 1
|
||
779 779 ; line 283 :
|
||
780 780 ; line 284 : #ifdef _MCU_BSR_
|
||
781 781 ; line 285 : #ifdef _MODEL_CTR_
|
||
782 782 ; line 286 : #ifdef _SW_HOME_ENABLE_
|
||
783 783 ; line 287 : PU20 = 0b00010001;
|
||
784 784 $DGL 0,100
|
||
785 785 000F0 CF120511 mov !PU20,#011H ; 17 ;[INF] 4, 1
|
||
786 786 ; line 288 : #else
|
||
787 787 ; line 289 : PU20 = 0b00000001;
|
||
788 788 ; line 290 : #endif
|
||
789 789 ; line 291 : #else
|
||
790 790 ; line 292 : PU20 = 0b00000000;
|
||
791 791 ; line 293 : #endif
|
||
792 792 ; line 294 : #endif
|
||
793 793 ; line 295 :
|
||
794 794 ; line 296 : // <20>|<7C>[<5B>g<EFBFBD><67><EFBFBD>̓<EFBFBD><CD83>[<5B>h<EFBFBD>E<EFBFBD><45><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ݒ<EFBFBD> /////////////////////
|
||
795 795 ; line 297 : // [0:<3A>ʏ<EFBFBD><CA8F><EFBFBD><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@ 1:TTL<54><4C><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@]
|
||
796 796 ; line 298 : PIM3 = 0b00000000;
|
||
797 797 $DGL 0,111
|
||
798 798 000F4 F54300 clrb !PIM3 ;[INF] 3, 1
|
||
799 799 ; line 299 : PIM7 = 0b00000000;
|
||
800 800 $DGL 0,112
|
||
801 801 000F7 F54700 clrb !PIM7 ;[INF] 3, 1
|
||
802 802 ; line 300 :
|
||
803 803 ; line 301 : // <20>|<7C>[<5B>g<EFBFBD>o<EFBFBD>̓<EFBFBD><CD83>[<5B>h<EFBFBD>E<EFBFBD><45><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ݒ<EFBFBD>
|
||
804 804 ; line 302 : // [0:<3A>ʏ<EFBFBD><CA8F>o<EFBFBD>̓<EFBFBD><CD83>[<5B>h 1:N-ch<63>I<EFBFBD>[<5B>v<EFBFBD><76><EFBFBD>E<EFBFBD>h<EFBFBD><68><EFBFBD>[<5B><><EFBFBD>o<EFBFBD><6F>]
|
||
805 805 ; line 303 : POM3 = 0b00000110;
|
||
806 806 $DGL 0,116
|
||
807 807 000FA CF530006 mov !POM3,#06H ; 6 ;[INF] 4, 1
|
||
808 808 ; line 304 : POM7 = 0b00000000;
|
||
809 809 $DGL 0,117
|
||
810 810 000FE F55700 clrb !POM7 ;[INF] 3, 1
|
||
811 811 ; line 305 :
|
||
812 812 ; line 306 : /*--- <20><><EFBFBD>荞<EFBFBD>ݐݒ<DD90> ---------*/
|
||
813 813 ; line 307 : IF0 = 0x0000; /* <20><><EFBFBD>荞<EFBFBD>ݗv<DD97><76><EFBFBD>t<EFBFBD><74><EFBFBD>O<EFBFBD>N<EFBFBD><4E><EFBFBD>A */
|
||
814 814 $DGL 0,120
|
||
815 815 00101 F6 clrw ax ;[INF] 1, 1
|
||
816 816 00102 BEE0 movw IF0,ax ;[INF] 2, 1
|
||
817 817 ; line 308 : IF1 = 0x0000;
|
||
818 818 $DGL 0,121
|
||
819 819 00104 BEE2 movw IF1,ax ;[INF] 2, 1
|
||
820 820 ; line 309 : #ifdef _MCU_BSR_
|
||
821 821 ; line 310 : IF2 = 0x0000;
|
||
822 822 $DGL 0,123
|
||
823 823 00106 BED0 movw IF2,ax ;[INF] 2, 1
|
||
824 824 ; line 311 : #else
|
||
825 825 ; line 312 : IF2L = 0x00;
|
||
826 826 ; line 313 : #endif
|
||
827 827 ; line 314 :
|
||
828 828 ; line 315 : MK0 = 0xFFFF; /* <20><><EFBFBD>荞<EFBFBD>֎~ */
|
||
829 829 $DGL 0,128
|
||
830 830 00108 CBE4FFFF movw MK0,#0FFFFH ; -1 ;[INF] 4, 1
|
||
831 831 ; line 316 : MK1 = 0xFFFF;
|
||
832 832 $DGL 0,129
|
||
833 833 0010C CBE6FFFF movw MK1,#0FFFFH ; -1 ;[INF] 4, 1
|
||
834 834 ; line 317 :
|
||
835 835 ; line 318 : #ifdef _MCU_BSR_
|
||
836 836 ; line 319 : MK2 = 0xFFFF;
|
||
837 837 $DGL 0,132
|
||
838 838 00110 CBD4FFFF movw MK2,#0FFFFH ; -1 ;[INF] 4, 1
|
||
839 839 ; line 320 : #else
|
||
840 840 ; line 321 : MK2L = 0xFF;
|
||
841 841 ; line 322 : #endif
|
||
842 842 ; line 323 :
|
||
843 843 ; line 324 : PR00L = 0b11111111; /* <20><><EFBFBD>荞<EFBFBD>ݗD<DD97>揇<EFBFBD>ʁA<CA81>S<EFBFBD>Ē<EFBFBD><C492><EFBFBD>(LV3
|
||
844 844 ; ) */
|
||
845 845 $DGL 0,137
|
||
846 846 00114 CEE8FF mov PR00L,#0FFH ; 255 ;[INF] 3, 1
|
||
847 847 ; line 325 : PR10L = 0b11111111;
|
||
848 848 $DGL 0,138
|
||
849 849 00117 CEECFF mov PR10L,#0FFH ; 255 ;[INF] 3, 1
|
||
850 850 ; line 326 : PR00H = 0b11111111;
|
||
851 851 $DGL 0,139
|
||
852 852 0011A CEE9FF mov PR00H,#0FFH ; 255 ;[INF] 3, 1
|
||
853 853 ; line 327 : PR10H = 0b11111111;
|
||
854 854 $DGL 0,140
|
||
855 855 0011D CEEDFF mov PR10H,#0FFH ; 255 ;[INF] 3, 1
|
||
856 856 ; line 328 : PR01L = 0b11111111;
|
||
857 857 $DGL 0,141
|
||
858 858 00120 CEEAFF mov PR01L,#0FFH ; 255 ;[INF] 3, 1
|
||
859 859 ; line 329 : PR11L = 0b11111110;
|
||
860 860 $DGL 0,142
|
||
861 861 00123 CEEEFE mov PR11L,#0FEH ; 254 ;[INF] 3, 1
|
||
862 862 ; line 330 : PR01H = 0b11111111;
|
||
863 863 $DGL 0,143
|
||
864 864 00126 CEEBFF mov PR01H,#0FFH ; 255 ;[INF] 3, 1
|
||
865 865 ; line 331 : PR11H = 0b11111111;
|
||
866 866 $DGL 0,144
|
||
867 867 00129 CEEFFF mov PR11H,#0FFH ; 255 ;[INF] 3, 1
|
||
868 868 ; line 332 : PR02L = 0b11111111;
|
||
869 869 $DGL 0,145
|
||
870 870 0012C CED8FF mov PR02L,#0FFH ; 255 ;[INF] 3, 1
|
||
871 871 ; line 333 : PR12L = 0b11111111;
|
||
872 872 $DGL 0,146
|
||
873 873 0012F CEDCFF mov PR12L,#0FFH ; 255 ;[INF] 3, 1
|
||
874 874 ; line 334 :
|
||
875 875 ; line 335 : /*--- <20>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̗L<CC97><4C><EFBFBD>G<EFBFBD>b<EFBFBD>W<EFBFBD>ݒ<EFBFBD> ---*/
|
||
876 876 ; line 336 : #ifdef _MCU_BSR_
|
||
877 877 ; line 337 : EGP0 = 0b00110001;
|
||
878 878 $DGL 0,150
|
||
879 879 00132 CE3831 mov EGP0,#031H ; 49 ;[INF] 3, 1
|
||
880 880 ; line 338 : EGN0 = 0b01110001;
|
||
881 881 $DGL 0,151
|
||
882 882 00135 CE3971 mov EGN0,#071H ; 113 ;[INF] 3, 1
|
||
883 883 ; line 339 : EGP2 = 0b00001010;
|
||
884 884 $DGL 0,152
|
||
885 885 00138 CF38050A mov !EGP2,#0AH ; 10 ;[INF] 4, 1
|
||
886 886 ; line 340 : EGN2 = 0b00000000;
|
||
887 887 $DGL 0,153
|
||
888 888 0013C F53905 clrb !EGN2 ;[INF] 3, 1
|
||
889 889 ; line 341 : #else
|
||
890 890 ; line 342 : EGP0 = 0b10110001;
|
||
891 891 ; line 343 : EGN0 = 0b01110001;
|
||
892 892 ; line 344 : #endif
|
||
893 893 ; line 345 : /*--- <20>L<EFBFBD>[<5B><><EFBFBD>荞<EFBFBD>ݐݒ<DD90> ---*/
|
||
894 894 ; line 346 : KRM = 0b00000000; /* <20>S<EFBFBD>L<EFBFBD>[<5B><><EFBFBD>荞<EFBFBD>ݐM<DD90><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>Ȃ<EFBFBD>
|
||
895 895 ; */
|
||
896 896 $DGL 0,159
|
||
897 897 0013F F537FF clrb !KRM ;[INF] 3, 1
|
||
898 898 ; line 347 :
|
||
899 899 ; line 348 : /*--- <20>^<5E>C<EFBFBD>}<7D>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
900 900 ; line 349 : TAU0EN = 0; /* <20>^<5E>C<EFBFBD>}<7D>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>ւ̃N
|
||
901 901 ; <20><><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
902 902 $DGL 0,162
|
||
903 903 00142 7108F200 clr1 !PER2.0 ;[INF] 4, 2
|
||
904 904 ; line 350 : TT0 = 0x00ff; /* <20>S<EFBFBD>^<5E>C<EFBFBD>}<7D>E<EFBFBD>`<60><><EFBFBD>l<EFBFBD><6C><EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
905 905 ; */
|
||
906 906 $DGL 0,163
|
||
907 907 00146 90 dec x ;[INF] 1, 1
|
||
908 908 00147 BFB401 movw !TT0,ax ;[INF] 3, 1
|
||
909 909 ; line 351 :
|
||
910 910 ; line 352 : /*--- RTC<54>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
911 911 ; line 353 : // RTCEN = 0; /* RTC<54>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
|
||
912 912 ; <20><><EFBFBD>~ */
|
||
913 913 ; line 354 : // RTCC0 = 0b00000000; /* <20>J<EFBFBD>E<EFBFBD><45><EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
914 914 ; line 355 : // <20>ʓr<CA93><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
915 915 ; line 356 :
|
||
916 916 ; line 357 : #ifndef _MCU_BSR_
|
||
917 917 ; line 358 : /*--- <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^/<2F>v<EFBFBD><76><EFBFBD>O<EFBFBD><4F><EFBFBD>}<7D>u<EFBFBD><75><EFBFBD>E<EFBFBD>Q<EFBFBD>C<EFBFBD><43><EFBFBD>E<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ --
|
||
918 918 ; -*/
|
||
919 919 ; line 359 : OACMPEN = 0; /* <20>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
920 920 ; line 360 : OAM = 0x00; /* <20>v<EFBFBD><76><EFBFBD>O<EFBFBD><4F><EFBFBD>}<7D>u<EFBFBD><75><EFBFBD>E<EFBFBD>Q<EFBFBD>C<EFBFBD><43><EFBFBD>E<EFBFBD>A<EFBFBD>b<EFBFBD>v
|
||
921 921 ; <20>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
922 922 ; line 361 : C0CTL = 0x00; /* <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
923 923 ; line 362 : C1CTL = 0x00; /* <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
924 924 ; line 363 : #endif
|
||
925 925 ; line 364 :
|
||
926 926 ; line 365 : /*--- <20>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD>o<EFBFBD><6F>/<2F>u<EFBFBD>U<EFBFBD>[<5B>o<EFBFBD>͒<EFBFBD><CD92>~ ---*/
|
||
927 927 ; line 366 : CKS0 = 0b00000000;
|
||
928 928 $DGL 0,179
|
||
929 929 0014A F5A5FF clrb !CKS0 ;[INF] 3, 1
|
||
930 930 ; line 367 : CKS1 = 0b00000000;
|
||
931 931 $DGL 0,180
|
||
932 932 0014D F5A6FF clrb !CKS1 ;[INF] 3, 1
|
||
933 933 ; line 368 :
|
||
934 934 ; line 369 : /*--- ADC<44>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
935 935 ; line 370 : ADCEN = 0; /* ADC<44>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
936 936 $DGL 0,183
|
||
937 937 00150 7158F000 clr1 !PER0.5 ;[INF] 4, 2
|
||
938 938 ; line 371 : ADM = 0b00000000; /* <20>ϊ<EFBFBD><CF8A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
939 939 $DGL 0,184
|
||
940 940 00154 F530FF clrb !ADM ;[INF] 3, 1
|
||
941 941 ; line 372 :
|
||
942 942 ; line 373 : /*--- <20>V<EFBFBD><56><EFBFBD>A<EFBFBD><41><EFBFBD>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
943 943 ; line 374 : SAU0EN = 0; /* <20>V<EFBFBD><56><EFBFBD>A<EFBFBD><41><EFBFBD>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g0<67><30>
|
||
944 944 ; <20>̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
945 945 $DGL 0,187
|
||
946 946 00157 7128F000 clr1 !PER0.2 ;[INF] 4, 2
|
||
947 947 ; line 375 : SCR00 = 0x0087; /* <20>e<EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD>l<EFBFBD><6C><EFBFBD>̒ʐM<CA90>֎~ */
|
||
948 948 $DGL 0,188
|
||
949 949 0015B 5087 mov x,#087H ; 135 ;[INF] 2, 1
|
||
950 950 0015D BF1801 movw !SCR00,ax ;[INF] 3, 1
|
||
951 951 ; line 376 : SCR01 = 0x0087;
|
||
952 952 $DGL 0,189
|
||
953 953 00160 BF1A01 movw !SCR01,ax ;[INF] 3, 1
|
||
954 954 ; line 377 : SCR02 = 0x0087;
|
||
955 955 $DGL 0,190
|
||
956 956 00163 BF1C01 movw !SCR02,ax ;[INF] 3, 1
|
||
957 957 ; line 378 : SCR03 = 0x0087;
|
||
958 958 $DGL 0,191
|
||
959 959 00166 BF1E01 movw !SCR03,ax ;[INF] 3, 1
|
||
960 960 ; line 379 :
|
||
961 961 ; line 380 : #ifdef _MCU_BSR_
|
||
962 962 ; line 381 : // IIC<49>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
963 963 ; line 382 : IICA0EN = 0; /* IICA0(CTR)<29>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
964 964 ; */
|
||
965 965 $DGL 0,195
|
||
966 966 00169 7148F000 clr1 !PER0.4 ;[INF] 4, 2
|
||
967 967 ; line 383 : IICCTL00 = 0x00; /* IICA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
968 968 $DGL 0,196
|
||
969 969 0016D F53002 clrb !IICCTL00 ;[INF] 3, 1
|
||
970 970 ; line 384 : IICA1EN = 0; // IICA1(TWL)<29>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
971 971 $DGL 0,197
|
||
972 972 00170 71080105 clr1 !PER3.0 ;[INF] 4, 2
|
||
973 973 ; line 385 : IICCTL01 = 0x00; // IICA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
974 974 $DGL 0,198
|
||
975 975 00174 F55005 clrb !IICCTL01 ;[INF] 3, 1
|
||
976 976 ; line 386 :
|
||
977 977 ; line 387 : #else
|
||
978 978 ; line 388 : /*--- IICA<43>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
979 979 ; line 389 : IICAEN = 0; /* IICA<43>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
980 980 ; line 390 : IICCTL0 = 0x00; /* IICA<43><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
981 981 ; line 391 : #endif
|
||
982 982 ; line 392 :
|
||
983 983 ; line 393 : /*--- DMA<4D>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
984 984 ; line 394 : DRC0 = 0b00000000; /* DMA<4D>`<60><><EFBFBD>l<EFBFBD><6C>0<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD>֎~ */
|
||
985 985 $DGL 0,207
|
||
986 986 00177 F5BCFF clrb !DRC0 ;[INF] 3, 1
|
||
987 987 ; line 395 : DRC1 = 0b00000000; /* DMA<4D>`<60><><EFBFBD>l<EFBFBD><6C>1<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD>֎~ */
|
||
988 988 $DGL 0,208
|
||
989 989 0017A F5BDFF clrb !DRC1 ;[INF] 3, 1
|
||
990 990 ; line 396 : }
|
||
991 991 $DGL 0,209
|
||
992 992 0017D ??ef_hdwinit2:
|
||
993 993 0017D D7 ret ;[INF] 1, 6
|
||
994 994 0017E ??ee_hdwinit2:
|
||
995 995
|
||
996 996 ----- LDR_CODL CSEG
|
||
997 997 END
|
||
998 998
|
||
999 999
|
||
1000 1000 ; *** Code Information ***
|
||
1001 1001 ;
|
||
1002 1002 ; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c
|
||
1003 1003 ;
|
||
1004 1004 ; $FUNC main(69)
|
||
1005 1005 ; void=(void)
|
||
1006 1006 ; CODE SIZE= 113 bytes, CLOCK_SIZE= 109 clocks, STACK_SIZE= 6 bytes
|
||
1007 1007 ;
|
||
1008 1008 ; $CALL WDT_Restart(72)
|
||
1009 1009 ; void=(void)
|
||
1010 1010 ;
|
||
1011 1011 ; $CALL hdwinit2(88)
|
||
1012 1012 ; void=(void)
|
||
1013 1013 ;
|
||
1014 1014 ; $CALL hdwinit2(106)
|
||
1015 1015 ; void=(void)
|
||
1016 1016 ;
|
||
1017 1017 ; $CALL firm_restore(124)
|
||
1018 1018 ; bc=(void)
|
||
1019 1019 ;
|
||
1020 1020 ; $CALL main_loop(130)
|
||
1021 1021 ; void=(void)
|
||
1022 1022 ;
|
||
1023 1023 ; $FUNC int_kr(140)
|
||
1024 1024 ; void=(void)
|
||
1025 1025 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
1026 1026 ;
|
||
1027 1027 ; $FUNC intp4(149)
|
||
1028 1028 ; void=(void)
|
||
1029 1029 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
1030 1030 ;
|
||
1031 1031 ; $FUNC intp5(157)
|
||
1032 1032 ; void=(void)
|
||
1033 1033 ; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
1034 1034 ;
|
||
1035 1035 ; $FUNC hdwinit(164)
|
||
1036 1036 ; void=(void)
|
||
1037 1037 ; CODE SIZE= 22 bytes, CLOCK_SIZE= 16 clocks, STACK_SIZE= 0 bytes
|
||
1038 1038 ;
|
||
1039 1039 ; $FUNC hdwinit2(188)
|
||
1040 1040 ; void=(void)
|
||
1041 1041 ; CODE SIZE= 247 bytes, CLOCK_SIZE= 101 clocks, STACK_SIZE= 0 bytes
|
||
1042 1042
|
||
1043 1043 ; Target chip : uPD79F0104
|
||
1044 1044 ; Device file : E1.00b
|
||
|
||
Segment informations:
|
||
|
||
ADRS LEN NAME
|
||
|
||
00000 00000H.0 @@BITS
|
||
00000 00000H @@CNST
|
||
00000 00000H @@R_INIT
|
||
00000 00000H @@INIT
|
||
00000 00000H @@DATA
|
||
00000 00000H @@R_INIS
|
||
00000 00000H @@INIS
|
||
00000 00000H @@DATS
|
||
00000 00000H LDR_CNSL
|
||
00000 00000H @@RLINIT
|
||
00000 00000H @@INITL
|
||
00000 00000H @@DATAL
|
||
00000 00000H @@CALT
|
||
00000 0017EH LDR_CODE
|
||
00000 00006H @@BASE
|
||
00000 00000H LDR_CODL
|
||
|
||
Target chip : uPD79F0104
|
||
Device file : E1.00b
|
||
Assembly complete, 0 error(s) and 0 warning(s) found. ( 0)
|
||
|