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https://github.com/rvtr/ctr_mcu.git
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dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
761 lines
23 KiB
NASM
761 lines
23 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:24
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no rtc.c
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; In-file : rtc.c
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; Asm-file : inter_asm\rtc.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, rtc.c
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$DGS MOD_NAM, rtc, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNSTL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, ROM_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CODEL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _RTC_init, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 051H, 00H, 00H
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$DGS BEG_FUN, ??bf_RTC_init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 017H, 02H, 047H
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$DGS BEG_BLK, ??bb00_RTC_init, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 04H, 00H, 04BH
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$DGS END_BLK, ??eb00_RTC_init, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 017H
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$DGS BEG_BLK, ??bb01_RTC_init, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 022H, 00H, 00H
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$DGS END_BLK, ??eb01_RTC_init, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 023H
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$DGS END_FUN, ??ef_RTC_init, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 029H
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$DGS GLV_SYM, _int_rtc, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 067H, 00H, 00H
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$DGS BEG_FUN, ??bf_int_rtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 048H, 02H, 055H
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$DGS BEG_BLK, ??bb00_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 057H
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$DGS BEG_BLK, ??bb01_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 08H, 00H, 059H
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$DGS BEG_BLK, ??bb02_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0AH, 00H, 05DH
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$DGS END_BLK, ??eb02_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0AH
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$DGS BEG_BLK, ??bb03_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0EH, 00H, 00H
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$DGS END_BLK, ??eb03_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 010H
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$DGS END_BLK, ??eb01_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS END_BLK, ??eb00_int_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 012H
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$DGS END_FUN, ??ef_int_rtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 013H
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$DGS GLV_SYM, _rtc_buf_reflesh, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 075H, 00H, 00H
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$DGS BEG_FUN, ??bf_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 063H, 02H, 06BH
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$DGS BEG_BLK, ??bb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 06DH
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$DGS BEG_BLK, ??bb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 07H, 00H, 00H
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$DGS END_BLK, ??eb01_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 08H
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$DGS END_BLK, ??eb00_rtc_buf_reflesh, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0DH
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$DGS END_FUN, ??ef_rtc_buf_reflesh, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 0EH
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$DGS GLV_SYM, _set_rtc, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 081H, 00H, 00H
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$DGS BEG_FUN, ??bf_set_rtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 07BH, 02H, 07BH
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$DGS REG_PAR, _adrs, 06H, 0FFFFH, 010CH, 011H, 00H, 00H
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$DGS REG_PAR, _data, 07H, 0FFFFH, 010CH, 011H, 00H, 00H
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$DGS BEG_BLK, ??bb00_set_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 00H
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$DGS END_BLK, ??eb00_set_rtc, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 07H
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$DGS END_FUN, ??ef_set_rtc, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 09H
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$DGS GLV_SYM, _rtc_unlock, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 093H, 00H, 00H
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$DGS BEG_FUN, ??bf_rtc_unlock, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 08CH, 02H, 085H
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$DGS BEG_BLK, ??bb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 09H, 00H, 087H
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$DGS BEG_BLK, ??bb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0DH, 00H, 08DH
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$DGS END_BLK, ??eb01_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 0EH
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$DGS END_BLK, ??eb00_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 011H
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$DGS BEG_BLK, ??bb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 015H, 00H, 00H
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$DGS END_BLK, ??eb02_rtc_unlock, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01BH
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$DGS END_FUN, ??ef_rtc_unlock, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 01CH
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$DGS GLV_SYM, _int_rtc_int, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H
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$DGS BEG_FUN, ??bf_int_rtc_int, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0B2H, 00H, 099H
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$DGS END_FUN, ??ef_int_rtc_int, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 03H
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$DGS GLV_SYM, _rtc_work, U, U, 0CH, 026H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 07H, 07H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _rtc_lock, U, U, 034CH, 027H, 00H, 00H
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$DGS GLV_SYM, _rtc_dirty, U, U, 034CH, 027H, 00H, 00H
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$DGS GLV_SYM, _rtc_alarm_dirty, U, U, 034CH, 027H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _renge_flg_interval, U, U, 034CH, 02H, 00H, 00H
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EXTRN _vreg_ctr
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EXTRN _system_status
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EXTBIT _renge_flg_interval
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PUBLIC _rtc_work
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PUBLIC _rtc_lock
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PUBLIC _rtc_dirty
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PUBLIC _rtc_alarm_dirty
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PUBLIC _RTC_init
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PUBLIC _int_rtc
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PUBLIC _rtc_buf_reflesh
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PUBLIC _set_rtc
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PUBLIC _rtc_unlock
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PUBLIC _int_rtc_int
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@@BITS BSEG
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_rtc_lock DBIT
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_rtc_dirty DBIT
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_rtc_alarm_dirty DBIT
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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DB 025H ; 37
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DB 038H ; 56
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DB 04DH ; 77
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DB 05FH ; 95
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DB 06EH ; 110
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DB 077H ; 119
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DB 07AH ; 122
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DB 077H ; 119
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DB 06EH ; 110
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DB 05FH ; 95
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DB 04DH ; 77
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DB 038H ; 56
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DB 025H ; 37
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DB 012H ; 18
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DB 04H ; 4
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DB 0FAH ; 250
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0F7H ; 247
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DB 0FBH ; 251
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DB 0FEH ; 254
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DB 00H ; 0
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 02H ; 2
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DB 01H ; 1
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DB (1)
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@@R_INIT CSEG UNIT64KP
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@@INIT DSEG BASEP
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@@DATA DSEG BASEP
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_rtc_work: DS (7)
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DS (1)
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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@@CNSTL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : /* ========================================================
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; line 2 : RTC
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; line 3 : ======================================================== */
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; line 4 : #pragma sfr
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; line 5 : #pragma inline
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; line 6 :
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; line 7 :
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; line 8 : #include "incs.h"
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; line 9 :
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; line 10 :
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; line 11 :
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; line 12 : // ========================================================
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; line 13 : u8 rtc_work[7];
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; line 14 : bit rtc_lock;
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; line 15 : bit rtc_dirty;
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; line 16 : bit rtc_alarm_dirty;
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; line 17 :
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; line 18 : /* ========================================================
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; line 19 : <20>y<EFBFBD><79><EFBFBD>t<EFBFBD>F<EFBFBD><46><EFBFBD><EFBFBD><EFBFBD>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD>
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; line 20 : <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̓d<CC93>r<EFBFBD><72><EFBFBD><EFBFBD><EFBFBD>r<EFBFBD>b<EFBFBD>g<EFBFBD>̃Z<CC83>b<EFBFBD>g
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; line 21 : ======================================================== */
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; line 22 : void RTC_init( void )
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; line 23 : {
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ROM_CODE CSEG BASE
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_RTC_init:
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$DGL 1,67
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push hl ;[INF] 1, 1
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??bf_RTC_init:
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; line 24 :
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; line 25 : if( !RTCEN ) // <20>r<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD>烊<EFBFBD>u<EFBFBD>[<5B>g
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$DGL 0,3
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movw hl,#0F0H ; 240 ;[INF] 3, 1
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mov1 CY,[hl].7 ;[INF] 2, 1
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bc $?L0003 ;[INF] 2, 4
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; line 26 : {
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??bb00_RTC_init:
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; line 27 : RTCEN = 1; // <20><><EFBFBD>W<EFBFBD><57><EFBFBD>[<5B><>ON
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$DGL 0,5
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set1 !PER0.7 ;[INF] 4, 2
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; line 28 :
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; line 29 : // RTC<54>ݒ<EFBFBD>
|
||
; line 30 : RTCC0 = 0b00001000; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~<7E>A24<32><34><EFBFBD>Ԑ<EFBFBD><D490>A32k<32>o<EFBFBD>́u<CD81><75>
|
||
; <20><><EFBFBD>Ȃ<EFBFBD><C882>v<EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD>݂Ȃ<DD82> */
|
||
$DGL 0,8
|
||
mov RTCC0,#08H ; 8 ;[INF] 3, 1
|
||
; line 31 : RTCC1 = 0b11000000; /* <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD>ݗL<DD97><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD>n
|
||
; */
|
||
$DGL 0,9
|
||
mov RTCC1,#0C0H ; 192 ;[INF] 3, 1
|
||
; line 32 : RTCC2 = 0b10000000; /* <20>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>:32k/2^6=2ms<6D>ARTCD
|
||
; IV<49>o<EFBFBD>͂Ȃ<CD82> */
|
||
$DGL 0,10
|
||
mov RTCC2,#080H ; 128 ;[INF] 3, 1
|
||
; line 33 :
|
||
; line 34 : SEC = 0x00;
|
||
$DGL 0,12
|
||
clrb !SEC ;[INF] 3, 1
|
||
; line 35 : MIN = 0x00;
|
||
$DGL 0,13
|
||
clrb !MIN ;[INF] 3, 1
|
||
; line 36 : HOUR = 0x15;
|
||
$DGL 0,14
|
||
mov HOUR,#015H ; 21 ;[INF] 3, 1
|
||
; line 37 : DAY = 0x01;
|
||
$DGL 0,15
|
||
oneb !DAY ;[INF] 3, 1
|
||
; line 38 : WEEK = 0x00;
|
||
$DGL 0,16
|
||
clrb !WEEK ;[INF] 3, 1
|
||
; line 39 : MONTH = 0x11;
|
||
$DGL 0,17
|
||
mov MONTH,#011H ; 17 ;[INF] 3, 1
|
||
; line 40 : YEAR = 0x09;
|
||
$DGL 0,18
|
||
mov YEAR,#09H ; 9 ;[INF] 3, 1
|
||
; line 41 :
|
||
; line 42 : ALARMWW = 0x7F;
|
||
$DGL 0,20
|
||
mov ALARMWW,#07FH ; 127 ;[INF] 3, 1
|
||
; line 43 :
|
||
; line 44 : vreg_ctr[VREG_C_MCU_STATUS] |= REG_BIT_RTC_BLACKOUT;
|
||
$DGL 0,22
|
||
set1 !_vreg_ctr+2.0 ;[INF] 4, 2
|
||
??eb00_RTC_init:
|
||
; line 45 : }
|
||
?L0003:
|
||
; line 46 : // <20><><EFBFBD>荞<EFBFBD>ݐݒ<DD90>
|
||
; line 47 : RTCIF = 0;
|
||
$DGL 0,25
|
||
clr1 IF1H.1 ;[INF] 3, 2
|
||
; line 48 : RTCIIF = 0;
|
||
$DGL 0,26
|
||
clr1 IF1H.2 ;[INF] 3, 2
|
||
; line 49 : RTCMK = 1; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)<29>֎~ */
|
||
$DGL 0,27
|
||
set1 MK1H.1 ;[INF] 3, 2
|
||
; line 50 : RTCIMK = 0; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28>A<EFBFBD><41><EFBFBD>[<5B><>&<26>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>
|
||
; )<29><><EFBFBD><EFBFBD> */
|
||
$DGL 0,28
|
||
clr1 MK1H.2 ;[INF] 3, 2
|
||
; line 51 :
|
||
; line 52 : RTCE = 1; /* <20><><EFBFBD><EFBFBD><EFBFBD>J<EFBFBD>n */
|
||
$DGL 0,30
|
||
set1 RTCC0.7 ;[INF] 3, 2
|
||
; line 53 :
|
||
; line 54 : RWAIT = 1;
|
||
$DGL 0,32
|
||
set1 RTCC1.0 ;[INF] 3, 2
|
||
; line 55 : while( !RWST )
|
||
$DGL 0,33
|
||
?L0005:
|
||
bt RTCC1.1,$?L0006 ;[INF] 4, 5
|
||
; line 56 : {;
|
||
??bb01_RTC_init:
|
||
??eb01_RTC_init:
|
||
; line 57 : }
|
||
$DGL 0,35
|
||
br $?L0005 ;[INF] 2, 3
|
||
?L0006:
|
||
; line 58 : RWAIT = 0;
|
||
$DGL 0,36
|
||
clr1 RTCC1.0 ;[INF] 3, 2
|
||
; line 59 :
|
||
; line 60 : rtc_lock = 0;
|
||
$DGL 0,38
|
||
clr1 _rtc_lock ;[INF] 3, 2
|
||
; line 61 : rtc_dirty = 0;
|
||
$DGL 0,39
|
||
clr1 _rtc_dirty ;[INF] 3, 2
|
||
; line 62 : rtc_alarm_dirty = 0;
|
||
$DGL 0,40
|
||
clr1 _rtc_alarm_dirty ;[INF] 3, 2
|
||
; line 63 : }
|
||
$DGL 0,41
|
||
??ef_RTC_init:
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_RTC_init:
|
||
; line 64 :
|
||
; line 65 :
|
||
; line 66 :
|
||
; line 67 : /* ========================================================
|
||
; line 68 : RTC <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
; line 69 : 2^6/fXT<58>i1.953125 ms<6D>j
|
||
; line 70 : ======================================================== */
|
||
; line 71 : __interrupt void int_rtc( )
|
||
; line 72 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_int_rtc:
|
||
$DGL 1,81
|
||
push ax ;[INF] 1, 1
|
||
??bf_int_rtc:
|
||
; line 73 : // <20><><EFBFBD>t<EFBFBD><74><EFBFBD>w<EFBFBD><77><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 74 : if( ( vreg_ctr[VREG_C_RTC_ALARM_DAY] == DAY )
|
||
; line 75 : && ( vreg_ctr[VREG_C_RTC_ALARM_MONTH] == MONTH )
|
||
; line 76 : && ( vreg_ctr[VREG_C_RTC_ALARM_YEAR] == YEAR ) )
|
||
$DGL 0,5
|
||
mov a,!_vreg_ctr+58 ;[INF] 3, 1
|
||
cmp a,!DAY ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
mov a,!_vreg_ctr+59 ;[INF] 3, 1
|
||
cmp a,!MONTH ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
mov a,!_vreg_ctr+60 ;[INF] 3, 1
|
||
cmp a,!YEAR ;[INF] 3, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
; line 77 : {
|
||
??bb00_int_rtc:
|
||
; line 78 : if( ( vreg_ctr[VREG_C_IRQ_MASK1] & REG_BIT_RTC_ALARM ) =
|
||
; = 0 )
|
||
$DGL 0,7
|
||
mov a,!_vreg_ctr+25 ;[INF] 3, 1
|
||
and a,#04H ; 4 ;[INF] 2, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0013 ;[INF] 2, 4
|
||
; line 79 : {
|
||
??bb01_int_rtc:
|
||
; line 80 : vreg_ctr[VREG_C_IRQ1] |= REG_BIT_RTC_ALARM;
|
||
$DGL 0,9
|
||
set1 !_vreg_ctr+17.2 ;[INF] 4, 2
|
||
; line 81 : IRQ0_ast;
|
||
$DGL 0,10
|
||
??bb02_int_rtc:
|
||
clr1 P7.6 ;[INF] 3, 2
|
||
clr1 PM7.6 ;[INF] 3, 2
|
||
??eb02_int_rtc:
|
||
; line 82 : // <20>}<7D>X<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82><EFBFBD>
|
||
; line 83 : if(( system_status.pwr_state == BT_CHARGE ) ||
|
||
$DGL 0,12
|
||
cmp !_system_status,#06H ; 6 ;[INF] 4, 1
|
||
bz $?L0015 ;[INF] 2, 4
|
||
; line 84 : ( system_status.pwr_state == OFF ))
|
||
$DGL 0,13
|
||
cmp !_system_status,#01H ; 1 ;[INF] 4, 1
|
||
sknz ;[INF] 2, 1
|
||
?L0015:
|
||
; line 85 : {
|
||
??bb03_int_rtc:
|
||
; line 86 : system_status.poweron_reason = RTC_ALARM;
|
||
$DGL 0,15
|
||
mov !_system_status+1,#02H ; 2 ;[INF] 4, 1
|
||
??eb03_int_rtc:
|
||
; line 87 : }
|
||
?L0013:
|
||
??eb01_int_rtc:
|
||
; line 88 : }
|
||
??eb00_int_rtc:
|
||
; line 89 : }
|
||
; line 90 : }
|
||
$DGL 0,19
|
||
??ef_int_rtc:
|
||
pop ax ;[INF] 1, 1
|
||
reti ;[INF] 2, 6
|
||
??ee_int_rtc:
|
||
; line 91 :
|
||
; line 92 :
|
||
; line 93 :
|
||
; line 94 : /* ========================================================
|
||
; line 95 : RTC <20>̃<EFBFBD><CC83>[<5B>h
|
||
; line 96 : <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>́Asec,min,hour,week,day,month,year <20>̏<EFBFBD>
|
||
; line 97 : ======================================================== */
|
||
; line 98 : void rtc_buf_reflesh( )
|
||
; line 99 : {
|
||
|
||
ROM_CODE CSEG BASE
|
||
_rtc_buf_reflesh:
|
||
$DGL 1,103
|
||
push hl ;[INF] 1, 1
|
||
??bf_rtc_buf_reflesh:
|
||
; line 100 : if( rtc_lock == 0 )
|
||
$DGL 0,2
|
||
bt _rtc_lock,$?L0018 ;[INF] 4, 5
|
||
; line 101 : {
|
||
??bb00_rtc_buf_reflesh:
|
||
; line 102 : rtc_lock = 1;
|
||
$DGL 0,4
|
||
set1 _rtc_lock ;[INF] 3, 2
|
||
; line 103 : RWAIT = 1;
|
||
$DGL 0,5
|
||
set1 RTCC1.0 ;[INF] 3, 2
|
||
; line 104 : while( !RWST )
|
||
$DGL 0,6
|
||
?L0020:
|
||
bt RTCC1.1,$?L0021 ;[INF] 4, 5
|
||
; line 105 : {;
|
||
??bb01_rtc_buf_reflesh:
|
||
??eb01_rtc_buf_reflesh:
|
||
; line 106 : }
|
||
$DGL 0,8
|
||
br $?L0020 ;[INF] 2, 3
|
||
?L0021:
|
||
; line 107 :
|
||
; line 108 : memcpy( &vreg_ctr[VREG_C_RTC_SEC], &SEC, 7 );
|
||
$DGL 0,10
|
||
movw de,#loww (_vreg_ctr+48) ;[INF] 3, 1
|
||
movw hl,#0FF92H ; -110 ;[INF] 3, 1
|
||
mov c,#07H ; 7 ;[INF] 2, 1
|
||
?L0022:
|
||
mov a,[hl] ;[INF] 1, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw hl ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $?L0022 ;[INF] 2, 4
|
||
; line 109 : RWAIT = 0;
|
||
$DGL 0,11
|
||
clr1 RTCC1.0 ;[INF] 3, 2
|
||
??eb00_rtc_buf_reflesh:
|
||
; line 110 : // renge_task_immed_add( tski_rtc_close );
|
||
; line 111 : }
|
||
?L0018:
|
||
; line 112 : }
|
||
$DGL 0,14
|
||
??ef_rtc_buf_reflesh:
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_rtc_buf_reflesh:
|
||
; line 113 :
|
||
; line 114 :
|
||
; line 115 :
|
||
; line 116 : /* ========================================================
|
||
; line 117 : RTC <20>̃<EFBFBD><CC83>C<EFBFBD>g
|
||
; line 118 : set_rtc_close <20>ƑŎg<C58E><67><EFBFBD>ĉ<EFBFBD><C489><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B
|
||
; line 119 : <20><><EFBFBD><EFBFBD><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@<40>ɃR<C983>s<EFBFBD>[<5B><><EFBFBD>邾<EFBFBD><E982BE><EFBFBD>ŁA
|
||
; line 120 : <20><><EFBFBD>ۂ<EFBFBD>RTC<54>ɃZ<C983>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>̂<EFBFBD>set_rtc_close()<29>ł<EFBFBD><C582>B
|
||
; line 121 : ======================================================== */
|
||
; line 122 : void set_rtc( u8 adrs, u8 data )
|
||
; line 123 : {
|
||
_set_rtc:
|
||
$DGL 1,117
|
||
push hl ;[INF] 1, 1
|
||
mov a,[sp+6] ;[INF] 2, 1
|
||
movw hl,ax ;[INF] 1, 1
|
||
??bf_set_rtc:
|
||
; line 124 : if( rtc_dirty == 0 )
|
||
$DGL 0,2
|
||
bt _rtc_dirty,$?L0026 ;[INF] 4, 5
|
||
; line 125 : {
|
||
??bb00_set_rtc:
|
||
; line 126 : rtc_dirty = 1;
|
||
$DGL 0,4
|
||
set1 _rtc_dirty ;[INF] 3, 2
|
||
; line 127 : memcpy( rtc_work, &SEC, 7 );
|
||
$DGL 0,5
|
||
push hl ;[INF] 1, 1
|
||
movw de,#loww (_rtc_work) ;[INF] 3, 1
|
||
movw ax,#0FF92H ; -110 ;[INF] 3, 1
|
||
movw hl,ax ;[INF] 1, 1
|
||
mov c,#07H ; 7 ;[INF] 2, 1
|
||
?L0028:
|
||
mov a,[hl] ;[INF] 1, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw hl ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $?L0028 ;[INF] 2, 4
|
||
pop hl ;[INF] 1, 1
|
||
??eb00_set_rtc:
|
||
; line 128 : // renge_task_immed_add( tski_rtc_close ); // I2C<32>I<EFBFBD><49><EFBFBD><EFBFBD><EFBFBD>ɍs<C98D><73>
|
||
; line 129 : }
|
||
?L0026:
|
||
; line 130 : rtc_work[adrs] = data;
|
||
$DGL 0,8
|
||
mov a,l ;[INF] 1, 1
|
||
mov b,a ;[INF] 1, 1
|
||
mov a,h ;[INF] 1, 1
|
||
mov _rtc_work[b],a ;[INF] 3, 1
|
||
; line 131 : }
|
||
$DGL 0,9
|
||
??ef_set_rtc:
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_set_rtc:
|
||
; line 132 :
|
||
; line 133 :
|
||
; line 134 :
|
||
; line 135 : /* ========================================================
|
||
; line 136 : <20>K<EFBFBD>v<EFBFBD>Ȃ<EFBFBD><C882>ARTC<54><43><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>̍X<CC8D>V
|
||
; line 137 : ======================================================== */
|
||
; line 138 : // task_status_immed tski_rtc_close(){
|
||
; line 139 : void rtc_unlock( )
|
||
; line 140 : {
|
||
_rtc_unlock:
|
||
$DGL 1,129
|
||
push hl ;[INF] 1, 1
|
||
??bf_rtc_unlock:
|
||
; line 141 : // <20><><EFBFBD>[<5B>h<EFBFBD><68><EFBFBD>b<EFBFBD>N
|
||
; line 142 : // if( rtc_lock != 0 ){
|
||
; line 143 : rtc_lock = 0;
|
||
$DGL 0,4
|
||
clr1 _rtc_lock ;[INF] 3, 2
|
||
; line 144 : // }
|
||
; line 145 :
|
||
; line 146 : // <20><><EFBFBD>C<EFBFBD>g<EFBFBD><67><EFBFBD>b<EFBFBD>N
|
||
; line 147 : if( rtc_dirty != 0 )
|
||
$DGL 0,8
|
||
bf _rtc_dirty,$?L0032 ;[INF] 4, 5
|
||
; line 148 : {
|
||
??bb00_rtc_unlock:
|
||
; line 149 : rtc_dirty = 0;
|
||
$DGL 0,10
|
||
clr1 _rtc_dirty ;[INF] 3, 2
|
||
; line 150 : RWAIT = 1;
|
||
$DGL 0,11
|
||
set1 RTCC1.0 ;[INF] 3, 2
|
||
; line 151 : while( !RWST )
|
||
$DGL 0,12
|
||
?L0034:
|
||
bt RTCC1.1,$?L0035 ;[INF] 4, 5
|
||
; line 152 : {;
|
||
??bb01_rtc_unlock:
|
||
??eb01_rtc_unlock:
|
||
; line 153 : }
|
||
$DGL 0,14
|
||
br $?L0034 ;[INF] 2, 3
|
||
?L0035:
|
||
; line 154 : memcpy( &SEC, rtc_work, 7 );
|
||
$DGL 0,15
|
||
movw de,#0FF92H ; -110 ;[INF] 3, 1
|
||
movw hl,#loww (_rtc_work) ;[INF] 3, 1
|
||
mov c,#07H ; 7 ;[INF] 2, 1
|
||
?L0036:
|
||
mov a,[hl] ;[INF] 1, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
incw de ;[INF] 1, 1
|
||
incw hl ;[INF] 1, 1
|
||
dec c ;[INF] 1, 1
|
||
bnz $?L0036 ;[INF] 2, 4
|
||
; line 155 : RWAIT = 0;
|
||
$DGL 0,16
|
||
clr1 RTCC1.0 ;[INF] 3, 2
|
||
??eb00_rtc_unlock:
|
||
; line 156 : }
|
||
?L0032:
|
||
; line 157 :
|
||
; line 158 : // <20>A<EFBFBD><41><EFBFBD>[<5B><><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
; line 159 : if( rtc_alarm_dirty )
|
||
$DGL 0,20
|
||
bf _rtc_alarm_dirty,$?L0038 ;[INF] 4, 5
|
||
; line 160 : {
|
||
??bb02_rtc_unlock:
|
||
; line 161 : WALE = 0;
|
||
$DGL 0,22
|
||
clr1 RTCC1.7 ;[INF] 3, 2
|
||
; line 162 : ALARMWM = vreg_ctr[VREG_C_RTC_ALARM_MIN];
|
||
$DGL 0,23
|
||
mov a,!_vreg_ctr+56 ;[INF] 3, 1
|
||
mov ALARMWM,a ;[INF] 2, 1
|
||
; line 163 : ALARMWH = vreg_ctr[VREG_C_RTC_ALARM_HOUR];
|
||
$DGL 0,24
|
||
mov a,!_vreg_ctr+57 ;[INF] 3, 1
|
||
mov ALARMWH,a ;[INF] 2, 1
|
||
; line 164 : rtc_dirty = 0;
|
||
$DGL 0,25
|
||
clr1 _rtc_dirty ;[INF] 3, 2
|
||
; line 165 : WALE = 1;
|
||
$DGL 0,26
|
||
set1 RTCC1.7 ;[INF] 3, 2
|
||
??eb02_rtc_unlock:
|
||
; line 166 : }
|
||
?L0038:
|
||
; line 167 : }
|
||
$DGL 0,28
|
||
??ef_rtc_unlock:
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_rtc_unlock:
|
||
; line 168 :
|
||
; line 169 :
|
||
; line 170 :
|
||
; line 171 :
|
||
; line 172 :
|
||
; line 173 : /* ========================================================
|
||
; line 174 : RTC <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD>`<60>b<EFBFBD>N<EFBFBD>^<5E>C<EFBFBD>}<7D><><EFBFBD>荞<EFBFBD>݃x<DD83>N<EFBFBD>^
|
||
; line 175 : 2^6/fXT<58>i1.953125 ms<6D>j
|
||
; line 176 : ======================================================== */
|
||
; line 177 : __interrupt void int_rtc_int( )
|
||
; line 178 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_int_rtc_int:
|
||
$DGL 1,147
|
||
??bf_int_rtc_int:
|
||
; line 179 : renge_flg_interval = 1;
|
||
$DGL 0,2
|
||
set1 _renge_flg_interval ;[INF] 3, 2
|
||
; line 180 : }
|
||
$DGL 0,3
|
||
??ef_int_rtc_int:
|
||
reti ;[INF] 2, 6
|
||
??ee_int_rtc_int:
|
||
|
||
@@CODEL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\rtc.c
|
||
;
|
||
; $FUNC RTC_init(23)
|
||
; void=(void)
|
||
; CODE SIZE= 87 bytes, CLOCK_SIZE= 57 clocks, STACK_SIZE= 2 bytes
|
||
;
|
||
; $FUNC int_rtc(72)
|
||
; void=(void)
|
||
; CODE SIZE= 62 bytes, CLOCK_SIZE= 47 clocks, STACK_SIZE= 2 bytes
|
||
;
|
||
; $FUNC rtc_buf_reflesh(99)
|
||
; void=(void)
|
||
; CODE SIZE= 37 bytes, CLOCK_SIZE= 39 clocks, STACK_SIZE= 2 bytes
|
||
;
|
||
; $FUNC set_rtc(123)
|
||
; void=(unsigned char adrs:x, unsigned char data:[sp+6])
|
||
; CODE SIZE= 37 bytes, CLOCK_SIZE= 36 clocks, STACK_SIZE= 4 bytes
|
||
;
|
||
; $FUNC rtc_unlock(140)
|
||
; void=(void)
|
||
; CODE SIZE= 63 bytes, CLOCK_SIZE= 56 clocks, STACK_SIZE= 2 bytes
|
||
;
|
||
; $FUNC int_rtc_int(178)
|
||
; void=(void)
|
||
; CODE SIZE= 5 bytes, CLOCK_SIZE= 8 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|