mirror of
https://github.com/rvtr/ctr_mcu.git
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dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
526 lines
16 KiB
NASM
526 lines
16 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no main.c
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; In-file : main.c
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; Asm-file : inter_asm\main.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 00H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 063H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, main.c
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$DGS MOD_NAM, main, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS STA_SYM, _lpf_coeff, U, U, 05002H, 03H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 02FH, 02FH, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _main_loop, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 05DH, 00H, 00H
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$DGS BEG_FUN, ??bf_main_loop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 021H, 00H, 047H
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$DGS BEG_BLK, ??bb00_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0EH, 00H, 049H
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$DGS BEG_BLK, ??bb01_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 014H, 00H, 04FH
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$DGS END_BLK, ??eb01_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 016H
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$DGS END_BLK, ??eb00_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 017H
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$DGS BEG_BLK, ??bb02_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 019H, 00H, 053H
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$DGS END_BLK, ??eb02_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01CH
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$DGS BEG_BLK, ??bb03_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02EH, 00H, 055H
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$DGS BEG_BLK, ??bb04_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 032H, 00H, 00H
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$DGS END_BLK, ??eb04_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 034H
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$DGS END_BLK, ??eb03_main_loop, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 038H
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$DGS END_FUN, ??ef_main_loop, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 039H
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$DGS STA_SYM, _read_dipsw, U, U, 01H, 03H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 063H, 00H, 00H
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$DGS BEG_FUN, ??bf_read_dipsw, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 05FH, 00H, 063H
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$DGS END_FUN, ??ef_read_dipsw, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 07H
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$DGS GLV_SYM, _system_status, U, U, 08H, 026H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _update, U, U, 034CH, 027H, 00H, 00H
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$DGS GLV_SYM, _pool, U, U, 0DH, 026H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 0200H, 0100H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _RTC_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _renge_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_start, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _PM_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _iic_mcu_read_a_byte, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_twl_init, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _clear_hosu_hist, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _renge_task_interval_run_force, U, U, 034CH, 02H, 00H, 00H
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$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _renge_task_interval_run, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _renge_task_immed_run, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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EXTRN _RTC_init
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EXTRN _renge_init
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EXTRN _iic_mcu_start
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EXTRN _PM_init
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EXTRN _iic_mcu_read_a_byte
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EXTRN _vreg_ctr_init
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EXTRN _vreg_twl_init
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EXTRN _clear_hosu_hist
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EXTRN _WDT_Restart
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EXTRN _renge_task_interval_run
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EXTRN _renge_task_immed_run
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EXTBIT _renge_task_interval_run_force
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PUBLIC _system_status
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PUBLIC _update
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PUBLIC _pool
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PUBLIC _main_loop
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@@BITS BSEG
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_update DBIT
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@@CNST CSEG MIRRORP
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_lpf_coeff: DB 01H ; 1
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DB 02H ; 2
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 00H ; 0
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DB 0FEH ; 254
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DB 0FBH ; 251
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DB 0F7H ; 247
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0FAH ; 250
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DB 04H ; 4
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DB 012H ; 18
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DB 025H ; 37
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DB 038H ; 56
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DB 04DH ; 77
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DB 05FH ; 95
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DB 06EH ; 110
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DB 077H ; 119
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DB 07AH ; 122
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DB 077H ; 119
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DB 06EH ; 110
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DB 05FH ; 95
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DB 04DH ; 77
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DB 038H ; 56
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DB 025H ; 37
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DB 012H ; 18
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DB 04H ; 4
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DB 0FAH ; 250
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DB 0F3H ; 243
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DB 0F0H ; 240
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DB 0F0H ; 240
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DB 0F3H ; 243
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DB 0F7H ; 247
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DB 0FBH ; 251
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DB 0FEH ; 254
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DB 00H ; 0
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DB 02H ; 2
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DB 03H ; 3
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DB 03H ; 3
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DB 02H ; 2
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DB 02H ; 2
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DB 01H ; 1
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DB (1)
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@@R_INIT CSEG UNIT64KP
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@@INIT DSEG BASEP
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@@DATA DSEG BASEP
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_system_status: DS (4)
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_pool: DS (512)
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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LDR_CNSL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : /* ========================================================
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; line 2 : MCU CTR BSR
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; line 3 : 2008,2009 nintendo
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; line 4 : <20>J<EFBFBD><4A><EFBFBD>Z<EFBFBD>p<EFBFBD><70><EFBFBD>@<40><><EFBFBD>c
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; line 5 : ======================================================== */
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; line 6 :
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; line 7 :
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; line 8 : // ========================================================
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; line 9 : #include "incs_loader.h"
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; line 10 :
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; line 11 : #include "WDT.h"
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; line 12 : #include "rtc.h"
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; line 13 : #include "pm.h"
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; line 14 : #include "accero.h"
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; line 15 : #include "led.h"
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; line 16 : #include "adc.h"
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; line 17 :
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; line 18 :
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; line 19 : // ========================================================
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; line 20 : static void read_dipsw( );
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; line 21 :
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; line 22 :
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; line 23 : // ========================================================
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; line 24 : system_status_ system_status;
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; line 25 : bit update;
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; line 26 :
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; line 27 :
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; line 28 : u16 pool[256]; // <20>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>̃<EFBFBD><CC83>[<5B>N<EFBFBD>G<EFBFBD><47><EFBFBD>A
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; <20><> <20><><EFBFBD><EFBFBD><EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>^
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; line 29 : /* ========================================================
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; line 30 : <20>{<7B><><EFBFBD>̃G<CC83><47><EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><D690><EFBFBD> loader.c <20>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>܂<EFBFBD>
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; line 31 : ======================================================== */
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; line 32 : void main_loop( void )
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; line 33 : {
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LDR_CODE CSEG BASE
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_main_loop:
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$DGL 1,67
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??bf_main_loop:
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; line 34 :
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; line 35 : // <20>d<EFBFBD>r<EFBFBD><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>̂<EFBFBD>
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; line 36 : RTC_init( ); // <20><><EFBFBD><EFBFBD><EFBFBD>Ń<EFBFBD><C583>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD>肵<EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD>
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$DGL 0,4
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call !_RTC_init ;[INF] 3, 3
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; line 37 :
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; line 38 : renge_init( );
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$DGL 0,6
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call !_renge_init ;[INF] 3, 3
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; line 39 :
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; line 40 : iic_mcu_start( );
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$DGL 0,8
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call !_iic_mcu_start ;[INF] 3, 3
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; line 41 : EI( );
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$DGL 0,9
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ei ;[INF] 3, 4
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; line 42 :
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; line 43 : PM_init();
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$DGL 0,11
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call !_PM_init ;[INF] 3, 3
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; line 44 :
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; line 45 : if( system_status.reboot )
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$DGL 0,13
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mov a,!_system_status+2 ;[INF] 3, 1
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bf a.3,$?L0003 ;[INF] 3, 5
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; line 46 : {
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??bb00_main_loop:
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; line 47 : #ifdef _PMIC_TWL_
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; line 48 : if( RESET1_n )
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; line 49 : #else
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; line 50 : if( PM_chk_LDSW() != 0 )
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$DGL 0,18
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movw ax,#03H ; 3 ;[INF] 3, 1
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push ax ;[INF] 1, 1
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mov x,#084H ; 132 ;[INF] 2, 1
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call !_iic_mcu_read_a_byte ;[INF] 3, 3
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pop ax ;[INF] 1, 1
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mov a,c ;[INF] 1, 1
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and a,#01H ; 1 ;[INF] 2, 1
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cmp0 a ;[INF] 1, 1
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bz $?L0004 ;[INF] 2, 4
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; line 51 : #endif
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; line 52 : {
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??bb01_main_loop:
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; line 53 : system_status.pwr_state = ON_TRIG;
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$DGL 0,21
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mov !_system_status,#02H ; 2 ;[INF] 4, 1
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??eb01_main_loop:
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; line 54 : }
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; line 55 : }
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$DGL 0,23
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??eb00_main_loop:
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br $?L0004 ;[INF] 2, 3
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?L0003:
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; line 56 : else
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; line 57 : {
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||
??bb02_main_loop:
|
||
; line 58 : // <20><><EFBFBD>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>͎<EFBFBD><CD8E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>Ȃ<EFBFBD>
|
||
; line 59 : system_status.pwr_state = OFF_TRIG;
|
||
$DGL 0,27
|
||
clrb !_system_status ;[INF] 3, 1
|
||
??eb02_main_loop:
|
||
; line 60 : }
|
||
?L0004:
|
||
; line 61 :
|
||
; line 62 : #ifdef _PARRADIUM_
|
||
; line 63 : system_status.pwr_state = OFF;
|
||
; line 64 : #endif
|
||
; line 65 : vreg_ctr_init( );
|
||
$DGL 0,33
|
||
call !_vreg_ctr_init ;[INF] 3, 3
|
||
; line 66 : vreg_twl_init( );
|
||
$DGL 0,34
|
||
call !_vreg_twl_init ;[INF] 3, 3
|
||
; line 67 :
|
||
; line 68 : read_dipsw( ); // <20><><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>ʼn<EFBFBD><C589><EFBFBD><EFBFBD><EFBFBD><EFBFBD>邩<EFBFBD>H
|
||
$DGL 0,36
|
||
call !_read_dipsw ;[INF] 3, 3
|
||
; line 69 :
|
||
; line 70 : clear_hosu_hist(); // <20><><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD>A
|
||
$DGL 0,38
|
||
call !_clear_hosu_hist ;[INF] 3, 3
|
||
; line 71 :
|
||
; line 72 : renge_task_interval_run_force = 1;
|
||
$DGL 0,40
|
||
set1 _renge_task_interval_run_force ;[INF] 3, 2
|
||
; line 73 :
|
||
; line 74 : RTCIMK = 0; /* <20><><EFBFBD>荞<EFBFBD><E88D9E>(<28>A<EFBFBD><41><EFBFBD>[<5B><>&<26>C<EFBFBD><43><EFBFBD>^<5E>[<5B>o<EFBFBD><6F>
|
||
; )<29><><EFBFBD><EFBFBD> */
|
||
$DGL 0,42
|
||
clr1 MK1H.2 ;[INF] 3, 2
|
||
; line 75 :
|
||
; line 76 : // <20><><EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>[<5B>v //
|
||
; line 77 : while( 1 )
|
||
?L0007:
|
||
; line 78 : { // <20>V<EFBFBD>X<EFBFBD>e<EFBFBD><65>tick<63>A<EFBFBD>܂<EFBFBD><DC82>͊<EFBFBD><CD8A>荞<EFBFBD>݂<EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD><DC82>B
|
||
??bb03_main_loop:
|
||
; line 79 : WDT_Restart( );
|
||
$DGL 0,47
|
||
call !_WDT_Restart ;[INF] 3, 3
|
||
; line 80 : renge_task_interval_run( ); // <20><><EFBFBD><EFBFBD><EFBFBD>ŁA<C581>V<EFBFBD>X<EFBFBD>e<EFBFBD><65>tick<63><6B>
|
||
; <20><><EFBFBD>͋<EFBFBD><CD8B><EFBFBD><EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
$DGL 0,48
|
||
call !_renge_task_interval_run ;[INF] 3, 3
|
||
; line 81 : while( renge_task_interval_run_force != 0 )
|
||
$DGL 0,49
|
||
?L0009:
|
||
bf _renge_task_interval_run_force,$?L0010 ;[INF] 4, 5
|
||
; line 82 : {
|
||
??bb04_main_loop:
|
||
; line 83 : renge_task_interval_run( );
|
||
$DGL 0,51
|
||
call !_renge_task_interval_run ;[INF] 3, 3
|
||
??eb04_main_loop:
|
||
; line 84 : }
|
||
$DGL 0,52
|
||
br $?L0009 ;[INF] 2, 3
|
||
?L0010:
|
||
; line 85 : WDT_Restart( );
|
||
$DGL 0,53
|
||
call !_WDT_Restart ;[INF] 3, 3
|
||
; line 86 : while( renge_task_immed_run( ) != ERR_SUCCESS );
|
||
; // <20><><EFBFBD><EFBFBD><EFBFBD>̃<EFBFBD><CC83>[<5B>v<EFBFBD><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>x<EFBFBD>Ɏ<EFBFBD><C98E>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD>܂<EFBFBD>
|
||
$DGL 0,54
|
||
?L0011:
|
||
call !_renge_task_immed_run ;[INF] 3, 3
|
||
cmp0 c ;[INF] 1, 1
|
||
bnz $?L0011 ;[INF] 2, 4
|
||
; line 87 : HALT( );
|
||
$DGL 0,55
|
||
halt ;[INF] 2, 3
|
||
??eb03_main_loop:
|
||
; line 88 : }
|
||
$DGL 0,56
|
||
br $?L0007 ;[INF] 2, 3
|
||
; line 89 : }
|
||
$DGL 0,57
|
||
??ef_main_loop:
|
||
ret ;[INF] 1, 6
|
||
??ee_main_loop:
|
||
; line 90 :
|
||
; line 91 :
|
||
; line 92 : /* ========================================================
|
||
; line 93 : ======================================================== */
|
||
; line 94 : static void read_dipsw( )
|
||
; line 95 : {
|
||
_read_dipsw:
|
||
$DGL 1,93
|
||
??bf_read_dipsw:
|
||
; line 96 : // <20>\<5C>t<EFBFBD>g<EFBFBD>f<EFBFBD>B<EFBFBD>b<EFBFBD>v<EFBFBD>X<EFBFBD>C<EFBFBD>b<EFBFBD>`<60>ǂݍ<C782><DD8D><EFBFBD>
|
||
; line 97 : // PU4 |= 0x03; // dip sw 0,1
|
||
; line 98 : system_status.dipsw0 = ( DIPSW_0 == 0 ) ? 0 : 1;
|
||
$DGL 0,4
|
||
bt P4.0,$?L0015 ;[INF] 4, 5
|
||
clrw ax ;[INF] 1, 1
|
||
br $?L0016 ;[INF] 2, 3
|
||
?L0015:
|
||
onew ax ;[INF] 1, 1
|
||
?L0016:
|
||
mov a,x ;[INF] 1, 1
|
||
movw de,#loww (_system_status+2) ;[INF] 3, 1
|
||
mov1 CY,a.0 ;[INF] 2, 1
|
||
mov a,[de] ;[INF] 1, 1
|
||
mov1 a.0,CY ;[INF] 2, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
; line 99 : system_status.dipsw1 = ( DIPSW_1 == 0 ) ? 0 : 1;
|
||
$DGL 0,5
|
||
bt P4.1,$?L0017 ;[INF] 4, 5
|
||
clrw ax ;[INF] 1, 1
|
||
br $?L0018 ;[INF] 2, 3
|
||
?L0017:
|
||
onew ax ;[INF] 1, 1
|
||
?L0018:
|
||
mov a,x ;[INF] 1, 1
|
||
movw de,#loww (_system_status+2) ;[INF] 3, 1
|
||
mov1 CY,a.0 ;[INF] 2, 1
|
||
mov a,[de] ;[INF] 1, 1
|
||
mov1 a.1,CY ;[INF] 2, 1
|
||
mov [de],a ;[INF] 1, 1
|
||
; line 100 : // PU4 &= ~0x03;
|
||
; line 101 : }
|
||
$DGL 0,7
|
||
??ef_read_dipsw:
|
||
ret ;[INF] 1, 6
|
||
??ee_read_dipsw:
|
||
|
||
LDR_CODL CSEG
|
||
|
||
@@BASE CSEG BASE
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\main.c
|
||
;
|
||
; $FUNC main_loop(33)
|
||
; void=(void)
|
||
; CODE SIZE= 93 bytes, CLOCK_SIZE= 97 clocks, STACK_SIZE= 6 bytes
|
||
;
|
||
; $CALL RTC_init(36)
|
||
; void=(void)
|
||
;
|
||
; $CALL renge_init(38)
|
||
; void=(void)
|
||
;
|
||
; $CALL iic_mcu_start(40)
|
||
; void=(void)
|
||
;
|
||
; $CALL PM_init(43)
|
||
; void=(void)
|
||
;
|
||
; $CALL iic_mcu_read_a_byte(50)
|
||
; bc=(int:ax, int:[sp+4])
|
||
;
|
||
; $CALL vreg_ctr_init(65)
|
||
; void=(void)
|
||
;
|
||
; $CALL vreg_twl_init(66)
|
||
; void=(void)
|
||
;
|
||
; $CALL read_dipsw(68)
|
||
; void=(void)
|
||
;
|
||
; $CALL clear_hosu_hist(70)
|
||
; void=(void)
|
||
;
|
||
; $CALL WDT_Restart(79)
|
||
; void=(void)
|
||
;
|
||
; $CALL renge_task_interval_run(80)
|
||
; bc=(void)
|
||
;
|
||
; $CALL renge_task_interval_run(83)
|
||
; bc=(void)
|
||
;
|
||
; $CALL WDT_Restart(85)
|
||
; void=(void)
|
||
;
|
||
; $CALL renge_task_immed_run(86)
|
||
; bc=(void)
|
||
;
|
||
; $FUNC read_dipsw(95)
|
||
; void=(void)
|
||
; CODE SIZE= 37 bytes, CLOCK_SIZE= 38 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|