mirror of
https://github.com/rvtr/ctr_mcu.git
synced 2025-10-31 13:51:10 -04:00
dc469bd4c6
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_mcu@193 013db118-44a6-b54f-8bf7-843cb86687b1
1045 lines
33 KiB
NASM
1045 lines
33 KiB
NASM
; 78K0R C Compiler V2.10 Assembler Source Date:13 Jun 2010 Time:19:31:23
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; Command : -c9F0104 -yC:\Program Files\NEC Electronics Tools\DEV -_msgoff -i
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; renge -iC:\Program Files\NEC Electronics Tools\FSL78K0R_Type02ES\
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; V1.20\inc78k0r -ms -qvjl3wt -sainter_asm -zp -no loader.c
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; In-file : loader.c
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; Asm-file : inter_asm\loader.asm
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; Para-file :
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$PROCESSOR(9F0104)
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$DEBUG
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$NODEBUGA
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$KANJICODE SJIS
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$TOL_INF 03FH, 0210H, 02H, 00H, 00H, 00H, 00H
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$DGS FIL_NAM, .file, 099H, 0FFFEH, 03FH, 067H, 01H, 00H
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$DGS AUX_FIL, loader.c
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$DGS MOD_NAM, loader, 00H, 0FFFEH, 00H, 077H, 00H, 00H
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$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CNSL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@RLINIT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@INITL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@DATAL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODE, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, LDR_CODL, U, U, 00H, 078H, 00H, 00H
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$DGS SEC_NAM, @@BASE, U, U, 00H, 078H, 00H, 00H
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$DGS ENM_TAG, _pwr_state_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 01EH
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$DGS MEB_ENM, _OFF_TRIG, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _OFF, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON_TRIG, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _ON, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP_TRIG, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _SLEEP, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _BT_CHARGE, 06H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 013H, 01H
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$DGS ENM_TAG, _poweron_reason_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 025H
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$DGS MEB_ENM, _NONE, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _PWSW, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _RTC_ALARM, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 01EH, 01H
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$DGS ENM_TAG, _model_, 00H, 0FFFEH, 0AH, 0FH, 01H, 00H
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$DGS AUX_TAG, 01H, 02FH
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$DGS MEB_ENM, _MODEL_JIKKI, 00H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_TS_BOARD, 01H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_SHIROBAKO, 02H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED1, 03H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED2, 04H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS MEB_ENM, _MODEL_RESERVED3, 05H, 0FFFFH, 04H, 010H, 00H, 00H
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$DGS END_STR, .eos, 01H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 025H, 01H
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$DGS STR_STR, .0fake, 00H, 0FFFEH, 08H, 0AH, 01H, 00H
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$DGS AUX_TAG, 04H, 041H
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$DGS MEB_STR, _pwr_state, 00H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 013H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS MEB_STR, _poweron_reason, 01H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 01EH, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BIT_FLD, _dipsw0, 010H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw1, 011H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _dipsw2, 012H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS BIT_FLD, _reboot, 013H, 0FFFFH, 0CH, 012H, 01H, 00H
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$DGS AUX_BIT, 00H, 01H
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$DGS MEB_STR, _model, 03H, 0FFFFH, 0AH, 08H, 01H, 00H
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$DGS AUX_STR, 025H, 00H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS END_STR, .eos, 04H, 0FFFFH, 00H, 066H, 01H, 00H
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$DGS AUX_EOS, 02FH, 04H
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$DGS GLV_SYM, _main, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 073H, 00H, 00H
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$DGS BEG_FUN, ??bf_main, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 045H, 02H, 045H
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$DGS BEG_BLK, ??bb00_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 03H, 00H, 047H
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$DGS BEG_BLK, ??bb01_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 06H, 00H, 04BH
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$DGS END_BLK, ??eb01_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 08H
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$DGS BEG_BLK, ??bb02_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 0AH, 00H, 04FH
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$DGS END_BLK, ??eb02_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 015H
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$DGS BEG_BLK, ??bb03_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 017H, 00H, 055H
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$DGS REG_VAR, _pwup_delay0, 06H, 0FFFFH, 010CH, 04H, 01H, 00H
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$DGS AUX_STR, 00H, 018H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS REG_VAR, _pwup_delay1, 07H, 0FFFFH, 010CH, 04H, 01H, 00H
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$DGS AUX_STR, 00H, 019H, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BEG_BLK, ??bb04_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01CH, 00H, 057H
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$DGS BEG_BLK, ??bb05_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01FH, 00H, 05FH
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$DGS END_BLK, ??eb05_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 021H
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$DGS END_BLK, ??eb04_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 023H
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$DGS END_BLK, ??eb03_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 027H
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$DGS BEG_BLK, ??bb06_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 02AH, 00H, 065H
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$DGS REG_VAR, _i, 06H, 0FFFFH, 010CH, 04H, 01H, 00H
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$DGS AUX_STR, 00H, 02BH, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS REG_VAR, _comp, 07H, 0FFFFH, 010CH, 04H, 01H, 00H
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$DGS AUX_STR, 00H, 02CH, 01H, 00H, 00H, 00H, 00H, 00H
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$DGS BEG_BLK, ??bb07_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 031H, 00H, 069H
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$DGS END_BLK, ??eb07_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 033H
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$DGS BEG_BLK, ??bb08_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 036H, 00H, 00H
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$DGS END_BLK, ??eb08_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03AH
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$DGS END_BLK, ??eb06_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03BH
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$DGS END_BLK, ??eb00_main, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 03FH
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$DGS END_FUN, ??ef_main, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 040H
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$DGS GLV_SYM, _int_kr, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 079H, 00H, 00H
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$DGS BEG_FUN, ??bf_int_kr, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 08CH, 00H, 079H
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$DGS END_FUN, ??ef_int_kr, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 02H
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$DGS GLV_SYM, _intp4, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 07FH, 00H, 00H
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$DGS BEG_FUN, ??bf_intp4, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 095H, 00H, 07FH
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$DGS END_FUN, ??ef_intp4, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 02H
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$DGS GLV_SYM, _intp5, U, U, 0E001H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 085H, 00H, 00H
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$DGS BEG_FUN, ??bf_intp5, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 09DH, 00H, 085H
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$DGS END_FUN, ??ef_intp5, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 02H
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$DGS GLV_SYM, _hdwinit, U, U, 01H, 026H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 08BH, 00H, 00H
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$DGS BEG_FUN, ??bf_hdwinit, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0A4H, 00H, 08BH
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$DGS END_FUN, ??ef_hdwinit, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 015H
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$DGS STA_SYM, _hdwinit2, U, U, 01H, 03H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 099H, 00H, 00H
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$DGS BEG_FUN, ??bf_hdwinit2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_BEG, 0BCH, 00H, 08FH
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$DGS BEG_BLK, ??bb00_hdwinit2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 04H, 00H, 093H
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$DGS END_BLK, ??eb00_hdwinit2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 019H
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$DGS BEG_BLK, ??bb01_hdwinit2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_BEG, 01BH, 00H, 00H
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$DGS END_BLK, ??eb01_hdwinit2, U, U, 00H, 064H, 01H, 00H
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$DGS AUX_END, 01FH
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$DGS END_FUN, ??ef_hdwinit2, U, U, 00H, 065H, 01H, 00H
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$DGS AUX_END, 0D1H
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$DGS GLV_SYM, _WDT_Restart, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _system_status, U, U, 08H, 02H, 01H, 00H
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$DGS AUX_STR, 02FH, 00H, 04H, 00H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _vreg_ctr, U, U, 0CH, 02H, 01H, 03H
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$DGS AUX_STR, 00H, 00H, 01H, 01H, 00H, 00H, 00H, 00H
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$DGS GLV_SYM, _firm_restore, U, U, 0CH, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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$DGS GLV_SYM, _main_loop, U, U, 01H, 02H, 01H, 02H
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$DGS AUX_FUN, 00H, U, U, 00H, 00H, 00H
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EXTRN _WDT_Restart
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EXTRN _system_status
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EXTRN _vreg_ctr
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EXTRN _firm_restore
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EXTRN _main_loop
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PUBLIC _main
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PUBLIC _int_kr
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PUBLIC _intp4
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PUBLIC _intp5
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PUBLIC _hdwinit
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@@BITS BSEG
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@@CNST CSEG MIRRORP
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@@R_INIT CSEG UNIT64KP
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@@INIT DSEG BASEP
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@@DATA DSEG BASEP
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@@R_INIS CSEG UNIT64KP
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@@INIS DSEG SADDRP
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@@DATS DSEG SADDRP
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LDR_CNSL CSEG PAGE64KP
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@@RLINIT CSEG UNIT64KP
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@@INITL DSEG UNIT64KP
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@@DATAL DSEG UNIT64KP
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@@CALT CSEG CALLT0
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; line 1 : /* ========================================================
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; line 2 : MCU CTR BSR
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; line 3 : 2009/03/30
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; line 4 : <20>J<EFBFBD><4A><EFBFBD>Z<EFBFBD>p<EFBFBD><70> <20><><EFBFBD>c
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; line 5 :
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; line 6 : <20>u<EFBFBD>[<5B>g<EFBFBD><67><EFBFBD>[<5B>_<EFBFBD>[<5B><>
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; line 7 : <20>z<EFBFBD>X<EFBFBD>g<EFBFBD>̒ʐM<CA90>ƁA<C681><41><EFBFBD>ȏ<EFBFBD><C88F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>t<EFBFBD>@<40>[<5B><><EFBFBD>̃`<60>F<EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD>s<EFBFBD><73><EFBFBD>B
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; line 8 :
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; line 9 : ======================================================== */
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; line 10 : #pragma SFR
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; line 11 : #pragma di
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; line 12 : #pragma ei
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; line 13 : #pragma nop
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; line 14 : #pragma stop
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; line 15 : #pragma halt
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; line 16 : #pragma opc
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; line 17 :
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; line 18 :
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; line 19 : #include "incs_loader.h"
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; line 20 :
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; line 21 : #include "fsl.h"
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; line 22 : #include "fsl_user.h"
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; line 23 :
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; line 24 : #include "i2c_ctr.h"
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; line 25 : #include "i2c_mcu.h"
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; line 26 : #include "pm.h"
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; line 27 : #include "rtc.h"
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; line 28 :
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; line 29 : #include "reboot.h"
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; line 30 :
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; line 31 :
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; line 32 : // ========================================================
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; line 33 : #if (FSL_DATA_BUFFER_SIZE>0)
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; line 34 : fsl_u08 fsl_data_buffer[FSL_DATA_BUFFER_SIZE];
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; line 35 : #endif
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; line 36 :
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; line 37 :
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; line 38 :
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; line 39 : #ifdef FSL_INT_BACKUP
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; line 40 : static fsl_u08 fsl_MK0L_bak_u08; /* if (interrupt back
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; up required) */
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; line 41 : static fsl_u08 fsl_MK0H_bak_u08; /* {
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; */
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; line 42 : static fsl_u08 fsl_MK1L_bak_u08; /* reserve space fo
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; r backup information */
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; line 43 : static fsl_u08 fsl_MK1H_bak_u08; /* of interrupt mas
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; k flags */
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; line 44 : static fsl_u08 fsl_MK2L_bak_u08; /*
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; */
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; line 45 : static fsl_u08 fsl_MK2H_bak_u08; /* }
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; */
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; line 46 : #endif
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; line 47 :
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; line 48 :
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; line 49 :
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; line 50 : // magic.c <20>̋L<CC8B>q<EFBFBD>ƈ<EFBFBD><C688><EFBFBD><EFBFBD>Ȃ<EFBFBD><C882>悤<EFBFBD>ɒ<EFBFBD><C992>ӁI
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; line 51 : #define MGC_LOAD 0x0FF6
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; line 52 : #define MGC_FOOT 0x4FF6
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; line 53 :
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; line 54 :
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; line 55 :
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; line 56 : // ========================================================
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; line 57 : void FSL_Open( void );
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; line 58 : void FSL_Close( void );
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; line 59 : void hdwinit( void );
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; line 60 : void power_save( );
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; line 61 : static void hdwinit2( );
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; line 62 :
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; line 63 : extern void main_loop( );
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; line 64 :
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; line 65 :
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; line 66 :
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; line 67 : // ========================================================
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; line 68 : void main( )
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; line 69 : {
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|
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LDR_CODE CSEG BASE
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_main:
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$DGL 1,65
|
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push hl ;[INF] 1, 1
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??bf_main:
|
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; line 70 : while( 1 )
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?L0003:
|
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; line 71 : {
|
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??bb00_main:
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; line 72 : WDT_Restart( );
|
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$DGL 0,4
|
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call !_WDT_Restart ;[INF] 3, 3
|
||
; line 73 : if( RTCEN )
|
||
$DGL 0,5
|
||
push hl ;[INF] 1, 1
|
||
movw hl,#0F0H ; 240 ;[INF] 3, 1
|
||
mov1 CY,[hl].7 ;[INF] 2, 1
|
||
pop hl ;[INF] 1, 1
|
||
bnc $?L0005 ;[INF] 2, 4
|
||
; line 74 : {
|
||
??bb01_main:
|
||
; line 75 : system_status.reboot = 1;
|
||
$DGL 0,7
|
||
set1 !_system_status+2.3 ;[INF] 4, 2
|
||
??eb01_main:
|
||
; line 76 : }
|
||
$DGL 0,8
|
||
br $?L0008 ;[INF] 2, 3
|
||
?L0005:
|
||
; line 77 : else if( ( RESF & 0x10 ) != 0) // WDRF,WDT<44>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g
|
||
$DGL 0,9
|
||
mov a,#010H ; 16 ;[INF] 2, 1
|
||
and a,!RESF ;[INF] 3, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bz $?L0007 ;[INF] 2, 4
|
||
; line 78 : {
|
||
??bb02_main:
|
||
; line 79 : system_status.reboot = 1;
|
||
$DGL 0,11
|
||
set1 !_system_status+2.3 ;[INF] 4, 2
|
||
; line 80 : #ifdef _PMIC_TWL_
|
||
; line 81 : // <20>\<5C><><EFBFBD><EFBFBD><EFBFBD>Ă<EFBFBD><C482>܂<EFBFBD><DC82>̂ōċN<C48B><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 82 : PM_reset_ast();
|
||
; line 83 : /// hdwinit2<74>Ȃ<EFBFBD><C882>Ń<EFBFBD><C583>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>ɑ<EFBFBD><C991>s<EFBFBD><73><EFBFBD><EFBFBD>
|
||
; <20>悢<EFBFBD>i<EFBFBD><69><EFBFBD>ɂ<EFBFBD><C982>ɂ<EFBFBD><C982>I<EFBFBD>j
|
||
; line 84 : #endif
|
||
; line 85 : vreg_ctr[ VREG_C_MCU_STATUS ] |= REG_BIT_STATUS_WDT_
|
||
; RESET;
|
||
$DGL 0,17
|
||
set1 !_vreg_ctr+2.1 ;[INF] 4, 2
|
||
; line 86 : // set_irq( VREG_C_IRQ0, REG_BIT_IRQ_WDT_RESET );
|
||
; line 87 : // <20><>I2C<32>̏<EFBFBD><CC8F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɍs<C98D><73>
|
||
; line 88 : hdwinit2( );
|
||
$DGL 0,20
|
||
call !_hdwinit2 ;[INF] 3, 3
|
||
??eb02_main:
|
||
; line 89 : }
|
||
$DGL 0,21
|
||
br $?L0008 ;[INF] 2, 3
|
||
?L0007:
|
||
; line 90 : else
|
||
; line 91 : {
|
||
??bb03_main:
|
||
; line 92 : u8 pwup_delay0 = 0;
|
||
$DGL 0,24
|
||
movw hl,#00H ; 0 ;[INF] 3, 1
|
||
; line 93 : u8 pwup_delay1 = 0;
|
||
; line 94 :
|
||
; line 95 : do
|
||
?L0009:
|
||
; line 96 : { // <20>d<EFBFBD>r<EFBFBD>ڑ<EFBFBD><DA91><EFBFBD><EFBFBD>A16ms<6D>҂<EFBFBD><D282>Ă݂<C482>(<28>`
|
||
; <20><><EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><EFBFBD>)
|
||
??bb04_main:
|
||
; line 97 : pwup_delay0 += 1;
|
||
$DGL 0,29
|
||
inc l ;[INF] 1, 1
|
||
; line 98 : do
|
||
?L0012:
|
||
; line 99 : {
|
||
??bb05_main:
|
||
; line 100 : pwup_delay1 += 1;
|
||
$DGL 0,32
|
||
inc h ;[INF] 1, 1
|
||
??eb05_main:
|
||
; line 101 : }
|
||
; line 102 : while( pwup_delay1 != 0 ); // u16<31>ɂ<EFBFBD><C982><EFBFBD><EFBFBD>ƃR
|
||
; <20><><EFBFBD>p<EFBFBD>C<EFBFBD><43><EFBFBD><EFBFBD><EFBFBD>{<7B><><EFBFBD><EFBFBD><F182BE82>c<EFBFBD>B
|
||
$DGL 0,34
|
||
mov a,h ;[INF] 1, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0012 ;[INF] 2, 4
|
||
??eb04_main:
|
||
; line 103 : }
|
||
; line 104 : while( pwup_delay0 != 0 );
|
||
$DGL 0,36
|
||
mov a,l ;[INF] 1, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
bnz $?L0009 ;[INF] 2, 4
|
||
; line 105 :
|
||
; line 106 : hdwinit2( );
|
||
$DGL 0,38
|
||
call !_hdwinit2 ;[INF] 3, 3
|
||
??eb03_main:
|
||
; line 107 : }
|
||
?L0008:
|
||
; line 108 :
|
||
; line 109 : // <20>t<EFBFBD>@<40>[<5B><><EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD><EFBFBD><EFBFBD>`<60>F<EFBFBD>b<EFBFBD>N //
|
||
; line 110 : {
|
||
??bb06_main:
|
||
; line 111 : u8 i;
|
||
; line 112 : u8 comp = 0;
|
||
$DGL 0,44
|
||
movw hl,#00H ; 0 ;[INF] 3, 1
|
||
; line 113 :
|
||
; line 114 : // <20><><EFBFBD>[<5B>_<EFBFBD>[<5B>Ɩ{<7B>͓̂<CC82><CD93><EFBFBD><EFBFBD>o<EFBFBD>[<5B>W<EFBFBD><57><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>H
|
||
; line 115 : /// <20><><EFBFBD>ւ̃A<CC83>b<EFBFBD>v<EFBFBD>f<EFBFBD>[<5B>g<EFBFBD>̓r<CC93><72><EFBFBD>ŏI<C58F><49><EFBFBD><EFBFBD><EFBFBD>ĂȂ<C482><C882><EFBFBD><EFBFBD>H
|
||
; line 116 : for( i = 0; i < sizeof( __TIME__ ); i++ ) // si
|
||
; zeof( __TIME__ ) = 8 <20>炵
|
||
$DGL 0,48
|
||
?L0015:
|
||
mov a,l ;[INF] 1, 1
|
||
cmp a,#09H ; 9 ;[INF] 2, 1
|
||
bnc $?L0016 ;[INF] 2, 4
|
||
; line 117 : {
|
||
??bb07_main:
|
||
; line 118 : comp += ( *( __far u8 * )( MGC_LOAD + i ) == *(
|
||
; u8 * )( MGC_FOOT + i ) ) ? 0 : 1;
|
||
$DGL 0,50
|
||
movw ax,hl ;[INF] 1, 1
|
||
clrb a ;[INF] 1, 1
|
||
addw ax,#0FF6H ; 4086 ;[INF] 3, 1
|
||
push ax ;[INF] 1, 1
|
||
sar a,7 ;[INF] 2, 1
|
||
mov ES,a ;[INF] 2, 1
|
||
pop de ;[INF] 1, 1
|
||
mov a,ES:[de] ;[INF] 2, 2
|
||
mov c,a ;[INF] 1, 1
|
||
movw ax,hl ;[INF] 1, 1
|
||
clrb a ;[INF] 1, 1
|
||
addw ax,#04FF6H ; 20470 ;[INF] 3, 1
|
||
movw de,ax ;[INF] 1, 1
|
||
mov a,[de] ;[INF] 1, 1
|
||
cmp c,a ;[INF] 2, 1
|
||
bnz $?L0018 ;[INF] 2, 4
|
||
clrw ax ;[INF] 1, 1
|
||
br $?L0019 ;[INF] 2, 3
|
||
?L0018:
|
||
onew ax ;[INF] 1, 1
|
||
?L0019:
|
||
mov a,x ;[INF] 1, 1
|
||
add h,a ;[INF] 2, 1
|
||
??eb07_main:
|
||
; line 119 : }
|
||
$DGL 0,51
|
||
inc l ;[INF] 1, 1
|
||
br $?L0015 ;[INF] 2, 3
|
||
?L0016:
|
||
; line 120 :
|
||
; line 121 : if( comp != 0 )
|
||
$DGL 0,53
|
||
mov a,h ;[INF] 1, 1
|
||
cmp0 a ;[INF] 1, 1
|
||
skz ;[INF] 2, 1
|
||
; line 122 : {
|
||
??bb08_main:
|
||
; line 123 : // <20>t<EFBFBD>@<40>[<5B><><EFBFBD><EFBFBD><EFBFBD>X<EFBFBD>g<EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>݂<EFBFBD>
|
||
; line 124 : firm_restore( );
|
||
$DGL 0,56
|
||
call !_firm_restore ;[INF] 3, 3
|
||
??eb08_main:
|
||
; line 125 : // <20>A<EFBFBD><41><EFBFBD>Ă<EFBFBD><C482>Ȃ<EFBFBD><C882>B<EFBFBD><42><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B
|
||
; line 126 : }
|
||
?L0020:
|
||
??eb06_main:
|
||
; line 127 : }
|
||
; line 128 :
|
||
; line 129 : // <20>ʏ<EFBFBD><CA8F>^<5E>]
|
||
; line 130 : main_loop( );
|
||
$DGL 0,62
|
||
call !_main_loop ;[INF] 3, 3
|
||
??eb00_main:
|
||
; line 131 : }
|
||
$DGL 0,63
|
||
br $?L0003 ;[INF] 2, 3
|
||
; line 132 : }
|
||
$DGL 0,64
|
||
??ef_main:
|
||
pop hl ;[INF] 1, 1
|
||
ret ;[INF] 1, 6
|
||
??ee_main:
|
||
; line 133 :
|
||
; line 134 :
|
||
; line 135 :
|
||
; line 136 : /* ========================================================
|
||
; line 137 : <20>L<EFBFBD>[<5B><><EFBFBD>^<5E>[<5B><><EFBFBD><EFBFBD><EFBFBD>荞<EFBFBD><E88D9E>
|
||
; line 138 : ======================================================== */
|
||
; line 139 : __interrupt void int_kr( )
|
||
; line 140 : {
|
||
|
||
@@BASE CSEG BASE
|
||
_int_kr:
|
||
$DGL 1,115
|
||
??bf_int_kr:
|
||
; line 141 : }
|
||
$DGL 0,2
|
||
??ef_int_kr:
|
||
reti ;[INF] 2, 6
|
||
??ee_int_kr:
|
||
; line 142 :
|
||
; line 143 :
|
||
; line 144 :
|
||
; line 145 : /* ========================================================
|
||
; line 146 : ext dc
|
||
; line 147 : ======================================================== */
|
||
; line 148 : __interrupt void intp4( )
|
||
; line 149 : {
|
||
_intp4:
|
||
$DGL 1,121
|
||
??bf_intp4:
|
||
; line 150 : }
|
||
$DGL 0,2
|
||
??ef_intp4:
|
||
reti ;[INF] 2, 6
|
||
??ee_intp4:
|
||
; line 151 :
|
||
; line 152 :
|
||
; line 153 : /* ========================================================
|
||
; line 154 : shell close
|
||
; line 155 : ======================================================== */
|
||
; line 156 : __interrupt void intp5( )
|
||
; line 157 : {
|
||
_intp5:
|
||
$DGL 1,127
|
||
??bf_intp5:
|
||
; line 158 : }
|
||
$DGL 0,2
|
||
??ef_intp5:
|
||
reti ;[INF] 2, 6
|
||
??ee_intp5:
|
||
; line 159 :
|
||
; line 160 :
|
||
; line 161 :
|
||
; line 162 : // ========================================================
|
||
; line 163 : void hdwinit( void )
|
||
; line 164 : { // <20>X<EFBFBD>^<5E>[<5B>g<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>[<5B>`<60><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20>Ăт܂<D182>
|
||
|
||
LDR_CODE CSEG BASE
|
||
_hdwinit:
|
||
$DGL 1,133
|
||
di ;[INF] 3, 4
|
||
??bf_hdwinit:
|
||
; line 165 : DI( ); /* <20>}<7D>X<EFBFBD>^<5E><><EFBFBD>荞<EFBFBD>֎~ */
|
||
; line 166 :
|
||
; line 167 : CMC = 0b00010110; /* X1<58><31><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD>(<28><><EFBFBD>̓|<7C>[<5B>g)<29>AXT1<54>g<EFBFBD>p
|
||
; <20>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD>̐<EFBFBD><CC90><EFBFBD><EFBFBD>Œ<EFBFBD><C592><EFBFBD><EFBFBD>d<EFBFBD>͔<EFBFBD><CD94>U */
|
||
$DGL 0,4
|
||
mov CMC,#016H ; 22 ;[INF] 3, 1
|
||
; line 168 : CSC = 0b10000000; /* X1<58><31><EFBFBD>U<EFBFBD>Ȃ<EFBFBD><C882>AXT1<54><31><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>U<EFBFBD><55><EFBFBD><EFBFBD> */
|
||
$DGL 0,5
|
||
mov CSC,#080H ; 128 ;[INF] 3, 1
|
||
; line 169 : #ifdef _MCU_BSR_
|
||
; line 170 : OSMC = 0x01; /* <20>B<EFBFBD><42><EFBFBD><EFBFBD><EFBFBD>W<EFBFBD>X<EFBFBD>^ */
|
||
$DGL 0,7
|
||
oneb !OSMC ;[INF] 3, 1
|
||
; line 171 : #endif
|
||
; line 172 : #ifdef _OVERCLOCK_
|
||
; line 173 : CKC = 0b00001000; /* CPU/<2F><><EFBFBD>ӃN<D383><4E><EFBFBD>b<EFBFBD>N=fMAIN<49>AfMAIN=
|
||
; fMX<4D>AfCLK=fMX */
|
||
$DGL 0,10
|
||
mov CKC,#08H ; 8 ;[INF] 3, 1
|
||
; line 174 : #else
|
||
; line 175 : // CKC <20>f<EFBFBD>t<EFBFBD>H<EFBFBD><48><EFBFBD>g<EFBFBD>ł悢
|
||
; line 176 : #endif
|
||
; line 177 :
|
||
; line 178 : /*--- <20><><EFBFBD>d<EFBFBD><64><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>H<EFBFBD>̐ݒ<CC90> ---*/
|
||
; line 179 : /* <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̃f<CC83>t<EFBFBD>H<EFBFBD><48><EFBFBD>g<EFBFBD>́A<CD81>I<EFBFBD>v<EFBFBD>V<EFBFBD><56><EFBFBD><EFBFBD><EFBFBD>E<EFBFBD>o<EFBFBD>C<EFBFBD>g<EFBFBD>ɂĎw<C48E>肳
|
||
; <20><><EFBFBD><EFBFBD> */
|
||
; line 180 : LVIS = 0b00000000; /* VLVI = 4.22<EFBFBD>}0.1V */
|
||
$DGL 0,17
|
||
clrb !LVIS ;[INF] 3, 1
|
||
; line 181 : LVIM = 0b00000000; /* LVI<56><49><EFBFBD><EFBFBD><EFBFBD>֎~ */
|
||
$DGL 0,18
|
||
clrb !LVIM ;[INF] 3, 1
|
||
; line 182 : /* <20>d<EFBFBD><64><EFBFBD>d<EFBFBD><64>(VDD)<29><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>d<EFBFBD><64>(VLVI)<29><><EFBFBD>Ɋ<EFBFBD><C98A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||
; line 183 : /* <20>d<EFBFBD><64><EFBFBD>d<EFBFBD><64>(VDD)<29><><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD>d<EFBFBD><64><VLVI)<29>A<EFBFBD>܂<EFBFBD><DC82>͓<EFBFBD><CD93><EFBFBD><EFBFBD>֎~<7E><><EFBFBD>ɒ<EFBFBD><C992>d<EFBFBD><64><EFBFBD><EFBFBD>
|
||
; <20>o */
|
||
; line 184 : }
|
||
$DGL 0,21
|
||
??ef_hdwinit:
|
||
ret ;[INF] 1, 6
|
||
??ee_hdwinit:
|
||
; line 185 :
|
||
; line 186 :
|
||
; line 187 : void hdwinit2( )
|
||
; line 188 : {
|
||
_hdwinit2:
|
||
$DGL 1,139
|
||
??bf_hdwinit2:
|
||
; line 189 : // <20>|<7C>[<5B>g<EFBFBD>ݒ<EFBFBD> /////////////////////////////////////////
|
||
; line 190 : if( system_status.reboot ) // <20><><EFBFBD>Z<EFBFBD>b<EFBFBD>g<EFBFBD>s<EFBFBD><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͂<EFBFBD><CD82><EFBFBD><EFBFBD>ɃZ<C983>b<EFBFBD>g
|
||
; <20><><EFBFBD><EFBFBD>
|
||
$DGL 0,3
|
||
mov a,!_system_status+2 ;[INF] 3, 1
|
||
bf a.3,$?L0032 ;[INF] 3, 5
|
||
; line 191 : {
|
||
??bb00_hdwinit2:
|
||
; line 192 : #ifdef _MODEL_TEG2_
|
||
; line 193 : P0 = 0b00000011;
|
||
; line 194 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
; <20><>
|
||
; line 195 : P14 = 0b00000001;
|
||
; line 196 : #endif
|
||
; line 197 : #ifdef _MODEL_WM0_
|
||
; line 198 : P0 = 0b00000011;
|
||
; line 199 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
; <20><>
|
||
; line 200 : P14 = 0b00000001;
|
||
; line 201 : #endif
|
||
; line 202 : #ifdef _MODEL_TS0_
|
||
; line 203 : P0 = 0b00000001;
|
||
; line 204 : P3 = 0b00000111; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
; <20><>
|
||
; line 205 : P14 = 0b00000000;
|
||
; line 206 : #endif
|
||
; line 207 : #ifdef _MODEL_CTR_
|
||
; line 208 : P0 = 0b00000001;
|
||
$DGL 0,21
|
||
oneb P0 ;[INF] 2, 1
|
||
; line 209 : P3 = 0b00000111; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
; <20><>
|
||
$DGL 0,22
|
||
mov P3,#07H ; 7 ;[INF] 3, 1
|
||
; line 210 : P14 = 0b00000000;
|
||
$DGL 0,23
|
||
clrb P14 ;[INF] 2, 1
|
||
??eb00_hdwinit2:
|
||
; line 211 : #endif
|
||
; line 212 : }
|
||
$DGL 0,25
|
||
br $?L0033 ;[INF] 2, 3
|
||
?L0032:
|
||
; line 213 : else
|
||
; line 214 : {
|
||
??bb01_hdwinit2:
|
||
; line 215 : P0 = 0b00000000;
|
||
$DGL 0,28
|
||
clrb P0 ;[INF] 2, 1
|
||
; line 216 : P3 = 0b00000110; // <20>Ȉ<EFBFBD>I2C<32>͏o<CD8F>̓<EFBFBD><CD83>b<EFBFBD>`<60><>1<EFBFBD>ɂ<EFBFBD>
|
||
; <20><>
|
||
$DGL 0,29
|
||
mov P3,#06H ; 6 ;[INF] 3, 1
|
||
; line 217 : P14 = 0b00000000;
|
||
$DGL 0,30
|
||
clrb P14 ;[INF] 2, 1
|
||
??eb01_hdwinit2:
|
||
; line 218 : }
|
||
?L0033:
|
||
; line 219 :
|
||
; line 220 : #ifdef _MCU_BSR_
|
||
; line 221 : PM0 = 0b11111111; // BSR<53>}<7D>C<EFBFBD>R<EFBFBD><52><EFBFBD>ł́Areset1<74>͊Ď<CD8A><C48E><EFBFBD>
|
||
; <20>݂ɂȂ<C982><C882>B
|
||
$DGL 0,34
|
||
mov PM0,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 222 : #else
|
||
; line 223 : PM0 = 0b00000000; // 0<>ŏo<C58F><6F>
|
||
; line 224 : #endif
|
||
; line 225 : PM3 = 0b11110000; // P31,32<33>͊Ȉ<CD8A>I2C
|
||
$DGL 0,38
|
||
mov PM3,#0F0H ; 240 ;[INF] 3, 1
|
||
; line 226 : PM14 = 0b11111100; // debugger[1] <20>Ƃ肠<C682><E882A0><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F>
|
||
$DGL 0,39
|
||
mov PM14,#0FCH ; 252 ;[INF] 3, 1
|
||
; line 227 :
|
||
; line 228 : P1 = 0b00000000;
|
||
$DGL 0,41
|
||
clrb P1 ;[INF] 2, 1
|
||
; line 229 : P2 = 0b00000000;
|
||
$DGL 0,42
|
||
clrb P2 ;[INF] 2, 1
|
||
; line 230 : P4 = 0b00000000;
|
||
$DGL 0,43
|
||
clrb P4 ;[INF] 2, 1
|
||
; line 231 : P5 = 0b00000000;
|
||
$DGL 0,44
|
||
clrb P5 ;[INF] 2, 1
|
||
; line 232 : P6 = 0b00000000;
|
||
$DGL 0,45
|
||
clrb P6 ;[INF] 2, 1
|
||
; line 233 : P7 = 0b01000000;
|
||
$DGL 0,46
|
||
mov P7,#040H ; 64 ;[INF] 3, 1
|
||
; line 234 : P12 = 0b00000000;
|
||
$DGL 0,47
|
||
clrb P12 ;[INF] 2, 1
|
||
; line 235 :
|
||
; line 236 : #ifdef _MCU_BSR_
|
||
; line 237 : P20 = 0b00000000;
|
||
$DGL 0,50
|
||
clrb !P20 ;[INF] 3, 1
|
||
; line 238 : #else
|
||
; line 239 : P8 = 0b00000000;
|
||
; line 240 : #endif
|
||
; line 241 :
|
||
; line 242 : P15 = 0b00000000;
|
||
$DGL 0,55
|
||
clrb P15 ;[INF] 2, 1
|
||
; line 243 :
|
||
; line 244 :
|
||
; line 245 : PM1 = 0b00000000;
|
||
$DGL 0,58
|
||
clrb !PM1 ;[INF] 3, 1
|
||
; line 246 : PM2 = 0b11101001;
|
||
$DGL 0,59
|
||
mov PM2,#0E9H ; 233 ;[INF] 3, 1
|
||
; line 247 :
|
||
; line 248 : #ifdef _PMIC_CTR_
|
||
; line 249 : PM4 = 0b11110111;
|
||
$DGL 0,62
|
||
mov PM4,#0F7H ; 247 ;[INF] 3, 1
|
||
; line 250 : #else
|
||
; line 251 : PM4 = 0b11111011;
|
||
; line 252 : #endif
|
||
; line 253 :
|
||
; line 254 : PM5 = 0b11110011;
|
||
$DGL 0,67
|
||
mov PM5,#0F3H ; 243 ;[INF] 3, 1
|
||
; line 255 : PM6 = 0b11111100; // I2C<32>̃<EFBFBD><CC83>C<EFBFBD><43><EFBFBD><EFBFBD>L<EFBFBD>o<EFBFBD>͂ɂȂ<C982><C882>Ă<EFBFBD><C482><EFBFBD>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD>V<EFBFBD>X<EFBFBD>e<EFBFBD><65><EFBFBD><EFBFBD>OFF<46>Ȃ̂ł<CC82><C582>܂<EFBFBD><DC82>Ȃ<EFBFBD>
|
||
$DGL 0,68
|
||
mov PM6,#0FCH ; 252 ;[INF] 3, 1
|
||
; line 256 : #ifdef _MODEL_CTR_
|
||
; line 257 : PM7 = 0b01011111;
|
||
$DGL 0,70
|
||
mov PM7,#05FH ; 95 ;[INF] 3, 1
|
||
; line 258 : #else
|
||
; line 259 : PM7 = 0b00011111;
|
||
; line 260 : #endif
|
||
; line 261 : PM12 = 0b11111111; // 32kHz<48>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD>̃s<CC83><73><EFBFBD>ݒ<EFBFBD><DD92>͂ǂ<CD82><C782><EFBFBD>
|
||
; <20>ł<EFBFBD><C582>悢
|
||
$DGL 0,74
|
||
mov PM12,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 262 : PM15 = 0b11111111;
|
||
$DGL 0,75
|
||
mov PM15,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 263 :
|
||
; line 264 : #ifdef _MCU_BSR_
|
||
; line 265 : #ifdef _MODEL_CTR_
|
||
; line 266 : PM20 = 0b11111101;
|
||
$DGL 0,79
|
||
mov !PM20,#0FDH ; 253 ;[INF] 4, 1
|
||
; line 267 : #else
|
||
; line 268 : PM20 = 0b11111100;
|
||
; line 269 : #endif
|
||
; line 270 : #else
|
||
; line 271 : PM8 = 0b11111111;
|
||
; line 272 : #endif
|
||
; line 273 :
|
||
; line 274 : // <20>v<EFBFBD><76><EFBFBD>A<EFBFBD>b<EFBFBD>v /////////////////////////////////////////
|
||
; line 275 : PU0 = 0b00000000; // <20>o<EFBFBD>b<EFBFBD>e<EFBFBD><65><EFBFBD>F<EFBFBD>،<EFBFBD><D88C>ɂ<EFBFBD><C982>ꂼ<EFBFBD><EA82BC><EFBFBD>Z<EFBFBD>b<EFBFBD>g
|
||
$DGL 0,88
|
||
clrb !PU0 ;[INF] 3, 1
|
||
; line 276 : PU1 = 0b00000000;
|
||
$DGL 0,89
|
||
clrb !PU1 ;[INF] 3, 1
|
||
; line 277 : PU3 = 0b00000000; // <20>O<EFBFBD><4F><EFBFBD>Ńv<C583><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>Ȃ<EFBFBD><C882>Ƌ<C68B><EF8D87>
|
||
; <20><><EFBFBD><EFBFBD><EFBFBD>BCPU<50><55><EFBFBD>v<EFBFBD><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD><EFBFBD>
|
||
$DGL 0,90
|
||
clrb !PU3 ;[INF] 3, 1
|
||
; line 278 : PU4 = 0b00000000; // <20>O<EFBFBD><4F><EFBFBD>Ńv<C583><76><EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD><76><EFBFBD>Ăق<C482><D982><EFBFBD>tool
|
||
; 0,1)
|
||
$DGL 0,91
|
||
clrb !PU4 ;[INF] 3, 1
|
||
; line 279 : PU5 = 0b00000011;
|
||
$DGL 0,92
|
||
mov !PU5,#03H ; 3 ;[INF] 4, 1
|
||
; line 280 : PU7 = 0b00011001;
|
||
$DGL 0,93
|
||
mov !PU7,#019H ; 25 ;[INF] 4, 1
|
||
; line 281 : PU12 = 0b00000000;
|
||
$DGL 0,94
|
||
clrb !PU12 ;[INF] 3, 1
|
||
; line 282 : PU14 = 0b00000000;
|
||
$DGL 0,95
|
||
clrb !PU14 ;[INF] 3, 1
|
||
; line 283 :
|
||
; line 284 : #ifdef _MCU_BSR_
|
||
; line 285 : #ifdef _MODEL_CTR_
|
||
; line 286 : #ifdef _SW_HOME_ENABLE_
|
||
; line 287 : PU20 = 0b00010001;
|
||
$DGL 0,100
|
||
mov !PU20,#011H ; 17 ;[INF] 4, 1
|
||
; line 288 : #else
|
||
; line 289 : PU20 = 0b00000001;
|
||
; line 290 : #endif
|
||
; line 291 : #else
|
||
; line 292 : PU20 = 0b00000000;
|
||
; line 293 : #endif
|
||
; line 294 : #endif
|
||
; line 295 :
|
||
; line 296 : // <20>|<7C>[<5B>g<EFBFBD><67><EFBFBD>̓<EFBFBD><CD83>[<5B>h<EFBFBD>E<EFBFBD><45><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ݒ<EFBFBD> /////////////////////
|
||
; line 297 : // [0:<3A>ʏ<EFBFBD><CA8F><EFBFBD><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@ 1:TTL<54><4C><EFBFBD>̓o<CD83>b<EFBFBD>t<EFBFBD>@]
|
||
; line 298 : PIM3 = 0b00000000;
|
||
$DGL 0,111
|
||
clrb !PIM3 ;[INF] 3, 1
|
||
; line 299 : PIM7 = 0b00000000;
|
||
$DGL 0,112
|
||
clrb !PIM7 ;[INF] 3, 1
|
||
; line 300 :
|
||
; line 301 : // <20>|<7C>[<5B>g<EFBFBD>o<EFBFBD>̓<EFBFBD><CD83>[<5B>h<EFBFBD>E<EFBFBD><45><EFBFBD>W<EFBFBD>X<EFBFBD>^<5E>ݒ<EFBFBD>
|
||
; line 302 : // [0:<3A>ʏ<EFBFBD><CA8F>o<EFBFBD>̓<EFBFBD><CD83>[<5B>h 1:N-ch<63>I<EFBFBD>[<5B>v<EFBFBD><76><EFBFBD>E<EFBFBD>h<EFBFBD><68><EFBFBD>[<5B><><EFBFBD>o<EFBFBD><6F>]
|
||
; line 303 : POM3 = 0b00000110;
|
||
$DGL 0,116
|
||
mov !POM3,#06H ; 6 ;[INF] 4, 1
|
||
; line 304 : POM7 = 0b00000000;
|
||
$DGL 0,117
|
||
clrb !POM7 ;[INF] 3, 1
|
||
; line 305 :
|
||
; line 306 : /*--- <20><><EFBFBD>荞<EFBFBD>ݐݒ<DD90> ---------*/
|
||
; line 307 : IF0 = 0x0000; /* <20><><EFBFBD>荞<EFBFBD>ݗv<DD97><76><EFBFBD>t<EFBFBD><74><EFBFBD>O<EFBFBD>N<EFBFBD><4E><EFBFBD>A */
|
||
$DGL 0,120
|
||
clrw ax ;[INF] 1, 1
|
||
movw IF0,ax ;[INF] 2, 1
|
||
; line 308 : IF1 = 0x0000;
|
||
$DGL 0,121
|
||
movw IF1,ax ;[INF] 2, 1
|
||
; line 309 : #ifdef _MCU_BSR_
|
||
; line 310 : IF2 = 0x0000;
|
||
$DGL 0,123
|
||
movw IF2,ax ;[INF] 2, 1
|
||
; line 311 : #else
|
||
; line 312 : IF2L = 0x00;
|
||
; line 313 : #endif
|
||
; line 314 :
|
||
; line 315 : MK0 = 0xFFFF; /* <20><><EFBFBD>荞<EFBFBD>֎~ */
|
||
$DGL 0,128
|
||
movw MK0,#0FFFFH ; -1 ;[INF] 4, 1
|
||
; line 316 : MK1 = 0xFFFF;
|
||
$DGL 0,129
|
||
movw MK1,#0FFFFH ; -1 ;[INF] 4, 1
|
||
; line 317 :
|
||
; line 318 : #ifdef _MCU_BSR_
|
||
; line 319 : MK2 = 0xFFFF;
|
||
$DGL 0,132
|
||
movw MK2,#0FFFFH ; -1 ;[INF] 4, 1
|
||
; line 320 : #else
|
||
; line 321 : MK2L = 0xFF;
|
||
; line 322 : #endif
|
||
; line 323 :
|
||
; line 324 : PR00L = 0b11111111; /* <20><><EFBFBD>荞<EFBFBD>ݗD<DD97>揇<EFBFBD>ʁA<CA81>S<EFBFBD>Ē<EFBFBD><C492><EFBFBD>(LV3
|
||
; ) */
|
||
$DGL 0,137
|
||
mov PR00L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 325 : PR10L = 0b11111111;
|
||
$DGL 0,138
|
||
mov PR10L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 326 : PR00H = 0b11111111;
|
||
$DGL 0,139
|
||
mov PR00H,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 327 : PR10H = 0b11111111;
|
||
$DGL 0,140
|
||
mov PR10H,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 328 : PR01L = 0b11111111;
|
||
$DGL 0,141
|
||
mov PR01L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 329 : PR11L = 0b11111110;
|
||
$DGL 0,142
|
||
mov PR11L,#0FEH ; 254 ;[INF] 3, 1
|
||
; line 330 : PR01H = 0b11111111;
|
||
$DGL 0,143
|
||
mov PR01H,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 331 : PR11H = 0b11111111;
|
||
$DGL 0,144
|
||
mov PR11H,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 332 : PR02L = 0b11111111;
|
||
$DGL 0,145
|
||
mov PR02L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 333 : PR12L = 0b11111111;
|
||
$DGL 0,146
|
||
mov PR12L,#0FFH ; 255 ;[INF] 3, 1
|
||
; line 334 :
|
||
; line 335 : /*--- <20>O<EFBFBD><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̗L<CC97><4C><EFBFBD>G<EFBFBD>b<EFBFBD>W<EFBFBD>ݒ<EFBFBD> ---*/
|
||
; line 336 : #ifdef _MCU_BSR_
|
||
; line 337 : EGP0 = 0b00110001;
|
||
$DGL 0,150
|
||
mov EGP0,#031H ; 49 ;[INF] 3, 1
|
||
; line 338 : EGN0 = 0b01110001;
|
||
$DGL 0,151
|
||
mov EGN0,#071H ; 113 ;[INF] 3, 1
|
||
; line 339 : EGP2 = 0b00001010;
|
||
$DGL 0,152
|
||
mov !EGP2,#0AH ; 10 ;[INF] 4, 1
|
||
; line 340 : EGN2 = 0b00000000;
|
||
$DGL 0,153
|
||
clrb !EGN2 ;[INF] 3, 1
|
||
; line 341 : #else
|
||
; line 342 : EGP0 = 0b10110001;
|
||
; line 343 : EGN0 = 0b01110001;
|
||
; line 344 : #endif
|
||
; line 345 : /*--- <20>L<EFBFBD>[<5B><><EFBFBD>荞<EFBFBD>ݐݒ<DD90> ---*/
|
||
; line 346 : KRM = 0b00000000; /* <20>S<EFBFBD>L<EFBFBD>[<5B><><EFBFBD>荞<EFBFBD>ݐM<DD90><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>Ȃ<EFBFBD>
|
||
; */
|
||
$DGL 0,159
|
||
clrb !KRM ;[INF] 3, 1
|
||
; line 347 :
|
||
; line 348 : /*--- <20>^<5E>C<EFBFBD>}<7D>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 349 : TAU0EN = 0; /* <20>^<5E>C<EFBFBD>}<7D>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>ւ̃N
|
||
; <20><><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
$DGL 0,162
|
||
clr1 !PER2.0 ;[INF] 4, 2
|
||
; line 350 : TT0 = 0x00ff; /* <20>S<EFBFBD>^<5E>C<EFBFBD>}<7D>E<EFBFBD>`<60><><EFBFBD>l<EFBFBD><6C><EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
; */
|
||
$DGL 0,163
|
||
dec x ;[INF] 1, 1
|
||
movw !TT0,ax ;[INF] 3, 1
|
||
; line 351 :
|
||
; line 352 : /*--- RTC<54>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 353 : // RTCEN = 0; /* RTC<54>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
|
||
; <20><><EFBFBD>~ */
|
||
; line 354 : // RTCC0 = 0b00000000; /* <20>J<EFBFBD>E<EFBFBD><45><EFBFBD>^<5E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 355 : // <20>ʓr<CA93><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
; line 356 :
|
||
; line 357 : #ifndef _MCU_BSR_
|
||
; line 358 : /*--- <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^/<2F>v<EFBFBD><76><EFBFBD>O<EFBFBD><4F><EFBFBD>}<7D>u<EFBFBD><75><EFBFBD>E<EFBFBD>Q<EFBFBD>C<EFBFBD><43><EFBFBD>E<EFBFBD>A<EFBFBD>b<EFBFBD>v<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ --
|
||
; -*/
|
||
; line 359 : OACMPEN = 0; /* <20>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 360 : OAM = 0x00; /* <20>v<EFBFBD><76><EFBFBD>O<EFBFBD><4F><EFBFBD>}<7D>u<EFBFBD><75><EFBFBD>E<EFBFBD>Q<EFBFBD>C<EFBFBD><43><EFBFBD>E<EFBFBD>A<EFBFBD>b<EFBFBD>v
|
||
; <20>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 361 : C0CTL = 0x00; /* <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 362 : C1CTL = 0x00; /* <20>R<EFBFBD><52><EFBFBD>p<EFBFBD><70><EFBFBD>[<5B>^1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 363 : #endif
|
||
; line 364 :
|
||
; line 365 : /*--- <20>N<EFBFBD><4E><EFBFBD>b<EFBFBD>N<EFBFBD>o<EFBFBD><6F>/<2F>u<EFBFBD>U<EFBFBD>[<5B>o<EFBFBD>͒<EFBFBD><CD92>~ ---*/
|
||
; line 366 : CKS0 = 0b00000000;
|
||
$DGL 0,179
|
||
clrb !CKS0 ;[INF] 3, 1
|
||
; line 367 : CKS1 = 0b00000000;
|
||
$DGL 0,180
|
||
clrb !CKS1 ;[INF] 3, 1
|
||
; line 368 :
|
||
; line 369 : /*--- ADC<44>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 370 : ADCEN = 0; /* ADC<44>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
$DGL 0,183
|
||
clr1 !PER0.5 ;[INF] 4, 2
|
||
; line 371 : ADM = 0b00000000; /* <20>ϊ<EFBFBD><CF8A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
$DGL 0,184
|
||
clrb !ADM ;[INF] 3, 1
|
||
; line 372 :
|
||
; line 373 : /*--- <20>V<EFBFBD><56><EFBFBD>A<EFBFBD><41><EFBFBD>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 374 : SAU0EN = 0; /* <20>V<EFBFBD><56><EFBFBD>A<EFBFBD><41><EFBFBD>E<EFBFBD>A<EFBFBD><41><EFBFBD>C<EFBFBD>E<EFBFBD><45><EFBFBD>j<EFBFBD>b<EFBFBD>g0<67><30>
|
||
; <20>̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
$DGL 0,187
|
||
clr1 !PER0.2 ;[INF] 4, 2
|
||
; line 375 : SCR00 = 0x0087; /* <20>e<EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD>l<EFBFBD><6C><EFBFBD>̒ʐM<CA90>֎~ */
|
||
$DGL 0,188
|
||
mov x,#087H ; 135 ;[INF] 2, 1
|
||
movw !SCR00,ax ;[INF] 3, 1
|
||
; line 376 : SCR01 = 0x0087;
|
||
$DGL 0,189
|
||
movw !SCR01,ax ;[INF] 3, 1
|
||
; line 377 : SCR02 = 0x0087;
|
||
$DGL 0,190
|
||
movw !SCR02,ax ;[INF] 3, 1
|
||
; line 378 : SCR03 = 0x0087;
|
||
$DGL 0,191
|
||
movw !SCR03,ax ;[INF] 3, 1
|
||
; line 379 :
|
||
; line 380 : #ifdef _MCU_BSR_
|
||
; line 381 : // IIC<49>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
; line 382 : IICA0EN = 0; /* IICA0(CTR)<29>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
; */
|
||
$DGL 0,195
|
||
clr1 !PER0.4 ;[INF] 4, 2
|
||
; line 383 : IICCTL00 = 0x00; /* IICA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
$DGL 0,196
|
||
clrb !IICCTL00 ;[INF] 3, 1
|
||
; line 384 : IICA1EN = 0; // IICA1(TWL)<29>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
$DGL 0,197
|
||
clr1 !PER3.0 ;[INF] 4, 2
|
||
; line 385 : IICCTL01 = 0x00; // IICA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~
|
||
$DGL 0,198
|
||
clrb !IICCTL01 ;[INF] 3, 1
|
||
; line 386 :
|
||
; line 387 : #else
|
||
; line 388 : /*--- IICA<43>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 389 : IICAEN = 0; /* IICA<43>ւ̃N<CC83><4E><EFBFBD>b<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 390 : IICCTL0 = 0x00; /* IICA<43><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ */
|
||
; line 391 : #endif
|
||
; line 392 :
|
||
; line 393 : /*--- DMA<4D>̓<EFBFBD><CC93><EFBFBD><EFBFBD><EFBFBD><EFBFBD>~ ---*/
|
||
; line 394 : DRC0 = 0b00000000; /* DMA<4D>`<60><><EFBFBD>l<EFBFBD><6C>0<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD>֎~ */
|
||
$DGL 0,207
|
||
clrb !DRC0 ;[INF] 3, 1
|
||
; line 395 : DRC1 = 0b00000000; /* DMA<4D>`<60><><EFBFBD>l<EFBFBD><6C>1<EFBFBD>̓<EFBFBD><CC93><EFBFBD><EFBFBD>֎~ */
|
||
$DGL 0,208
|
||
clrb !DRC1 ;[INF] 3, 1
|
||
; line 396 : }
|
||
$DGL 0,209
|
||
??ef_hdwinit2:
|
||
ret ;[INF] 1, 6
|
||
??ee_hdwinit2:
|
||
|
||
LDR_CODL CSEG
|
||
END
|
||
|
||
|
||
; *** Code Information ***
|
||
;
|
||
; $FILE C:\78k_data\yav-mcu-basara\branches\0.10(fix)\loader.c
|
||
;
|
||
; $FUNC main(69)
|
||
; void=(void)
|
||
; CODE SIZE= 113 bytes, CLOCK_SIZE= 109 clocks, STACK_SIZE= 6 bytes
|
||
;
|
||
; $CALL WDT_Restart(72)
|
||
; void=(void)
|
||
;
|
||
; $CALL hdwinit2(88)
|
||
; void=(void)
|
||
;
|
||
; $CALL hdwinit2(106)
|
||
; void=(void)
|
||
;
|
||
; $CALL firm_restore(124)
|
||
; bc=(void)
|
||
;
|
||
; $CALL main_loop(130)
|
||
; void=(void)
|
||
;
|
||
; $FUNC int_kr(140)
|
||
; void=(void)
|
||
; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC intp4(149)
|
||
; void=(void)
|
||
; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC intp5(157)
|
||
; void=(void)
|
||
; CODE SIZE= 2 bytes, CLOCK_SIZE= 6 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC hdwinit(164)
|
||
; void=(void)
|
||
; CODE SIZE= 22 bytes, CLOCK_SIZE= 16 clocks, STACK_SIZE= 0 bytes
|
||
;
|
||
; $FUNC hdwinit2(188)
|
||
; void=(void)
|
||
; CODE SIZE= 247 bytes, CLOCK_SIZE= 101 clocks, STACK_SIZE= 0 bytes
|
||
|
||
; Target chip : uPD79F0104
|
||
; Device file : E1.00b
|